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This commit is contained in:
Gabriel Lima
2022-06-08 12:56:38 -03:00
parent 9aa4fc0663
commit fea00eaa8a
41 changed files with 475 additions and 465 deletions
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12
Aula20220608.gise
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@@ -102,7 +102,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1654702959" xil_pn:in_ck="-4144913829261074638" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-2610007826355223435" xil_pn:start_ts="1654702949">
<transform xil_pn:end_ts="1654703554" xil_pn:in_ck="-4144913829261074638" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-2610007826355223435" xil_pn:start_ts="1654703544">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@@ -124,7 +124,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1654702973" xil_pn:in_ck="6717519187032307095" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7902521214899444903" xil_pn:start_ts="1654702967">
<transform xil_pn:end_ts="1654703563" xil_pn:in_ck="6717519187032307095" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7902521214899444903" xil_pn:start_ts="1654703556">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@@ -134,7 +134,7 @@
<outfile xil_pn:name="textovhdl.ngd"/>
<outfile xil_pn:name="textovhdl_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1654702984" xil_pn:in_ck="6717519187032307096" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-3180699873896808002" xil_pn:start_ts="1654702973">
<transform xil_pn:end_ts="1654703574" xil_pn:in_ck="6717519187032307096" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-3180699873896808002" xil_pn:start_ts="1654703563">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
@@ -147,7 +147,7 @@
<outfile xil_pn:name="textovhdl_summary.xml"/>
<outfile xil_pn:name="textovhdl_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1654703000" xil_pn:in_ck="-717353726922960719" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1178055513630676559" xil_pn:start_ts="1654702984">
<transform xil_pn:end_ts="1654703593" xil_pn:in_ck="-717353726922960719" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1178055513630676559" xil_pn:start_ts="1654703574">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@@ -162,7 +162,7 @@
<outfile xil_pn:name="textovhdl_pad.txt"/>
<outfile xil_pn:name="textovhdl_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1654703024" xil_pn:in_ck="-4144913829261083515" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1654703011">
<transform xil_pn:end_ts="1654703607" xil_pn:in_ck="-4144913829261083515" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1654703595">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
@@ -180,7 +180,7 @@
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
</transform>
<transform xil_pn:end_ts="1654703000" xil_pn:in_ck="6717519187032306964" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1654702993">
<transform xil_pn:end_ts="1654703593" xil_pn:in_ck="6717519187032306964" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1654703587">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>

2
_ngo/netlist.lst
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@@ -1,2 +1,2 @@
C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.ngc 1654702958
C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.ngc 1654703553
OK

2
_xmsgs/xst.xmsgs
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@@ -23,7 +23,7 @@
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DIPSW</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd</arg>&quot; line <arg fmt="%s" index="2">48</arg>: Output port &lt;<arg fmt="%s" index="3">ENOUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">UC4</arg>&gt; is unconnected or connected to loadless signal.
<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd</arg>&quot; line <arg fmt="%s" index="2">48</arg>: Output port &lt;<arg fmt="%s" index="3">ENOUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">UC4</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">num7</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.

28
par_usage_statistics.html
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@@ -5,21 +5,21 @@
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>544</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>544</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>521</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>4.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>4.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>5.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>5.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>6.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>6.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>6.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>6.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>6.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>6.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>4.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>5.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>5.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>6.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>6.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>6.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>6.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>6.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>6.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>6.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>1.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>1.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>3.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>0.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>1.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>3.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>1.4</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>1.1</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
@@ -27,6 +27,6 @@
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0569</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0572</xtag-par-property-value></TD></TR>
</xtag-section>
</TABLE>

2
textovhdl.bgn
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@@ -5,7 +5,7 @@ C:\Xilinx\14.7\ISE_DS\ISE\.
"textovhdl" is an NCD, version 3.2, device xc6slx16, package csg324, speed -2
Opened constraints file textovhdl.pcf.
Wed Jun 08 12:43:37 2022
Wed Jun 08 12:53:20 2022
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 textovhdl.ncd

BIN
textovhdl.bit
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Binary file not shown.

2
textovhdl.bld
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@@ -31,7 +31,7 @@ NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 4
Total memory usage is 161520 kilobytes
Total memory usage is 161264 kilobytes
Writing NGD file "textovhdl.ngd" ...
Total REAL time to NGDBUILD completion: 4 sec

6
textovhdl.cmd_log
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@@ -26,3 +26,9 @@ map -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0 -re
par -w -intstyle ise -ol high -mt off textovhdl_map.ncd textovhdl.ncd textovhdl.pcf
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml textovhdl.twx textovhdl.ncd -o textovhdl.twr textovhdl.pcf -ucf restricoes.ucf
bitgen -intstyle ise -f textovhdl.ut textovhdl.ncd
xst -intstyle ise -ifn "C:/Users/Gabriel/Xilinx/Aula20220608/textovhdl.xst" -ofn "C:/Users/Gabriel/Xilinx/Aula20220608/textovhdl.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc restricoes.ucf -p xc6slx16-csg324-2 textovhdl.ngc textovhdl.ngd
map -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o textovhdl_map.ncd textovhdl.ngd textovhdl.pcf
par -w -intstyle ise -ol high -mt off textovhdl_map.ncd textovhdl.ncd textovhdl.pcf
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml textovhdl.twx textovhdl.ncd -o textovhdl.twr textovhdl.pcf -ucf restricoes.ucf
bitgen -intstyle ise -f textovhdl.ut textovhdl.ncd

2
textovhdl.drc
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@@ -1,7 +1,7 @@
Release 14.7 Drc P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Wed Jun 08 12:43:37 2022
Wed Jun 08 12:53:20 2022
drc -z textovhdl.ncd textovhdl.pcf

2
textovhdl.ncd
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File diff suppressed because one or more lines are too long

2
textovhdl.ngc
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File diff suppressed because one or more lines are too long

2
textovhdl.ngd
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File diff suppressed because one or more lines are too long

2
textovhdl.ngr
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File diff suppressed because one or more lines are too long

2
textovhdl.pad
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@@ -1,7 +1,7 @@
Release 14.7 - par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Wed Jun 08 12:43:12 2022
Wed Jun 08 12:53:05 2022
# NOTE: This file is designed to be imported into a spreadsheet program

48
textovhdl.par
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@@ -1,7 +1,7 @@
Release 14.7 par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
GABRIEL-E5400:: Wed Jun 08 12:43:05 2022
GABRIEL-E5400:: Wed Jun 08 12:52:57 2022
par -w -intstyle ise -ol high -mt off textovhdl_map.ncd textovhdl.ncd
textovhdl.pcf
@@ -45,7 +45,7 @@ Slice Logic Utilization:
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 41 out of 2,278 1%
Number of occupied Slices: 42 out of 2,278 1%
Number of MUXCYs used: 44 out of 4,556 1%
Number of LUT Flip Flop pairs used: 132
Number with an unused Flip Flop: 56 out of 132 42%
@@ -93,8 +93,8 @@ Specific Feature Utilization:
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 4 secs
Finished initial Timing Analysis. REAL time: 4 secs
Starting initial Timing Analysis. REAL time: 5 secs
Finished initial Timing Analysis. REAL time: 5 secs
WARNING:Par:288 - The signal GPIO<5>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO<7>_IBUF has no load. PAR will not attempt to route this signal.
@@ -111,28 +111,28 @@ WARNING:Par:288 - The signal GPIO<4>_IBUF has no load. PAR will not attempt to
Starting Router
Phase 1 : 586 unrouted; REAL time: 4 secs
Phase 1 : 586 unrouted; REAL time: 5 secs
Phase 2 : 514 unrouted; REAL time: 4 secs
Phase 2 : 514 unrouted; REAL time: 6 secs
Phase 3 : 55 unrouted; REAL time: 5 secs
Phase 3 : 80 unrouted; REAL time: 6 secs
Phase 4 : 55 unrouted; (Par is working to improve performance) REAL time: 5 secs
Phase 4 : 80 unrouted; (Par is working to improve performance) REAL time: 7 secs
Updating file: textovhdl.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 6 secs
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 6 secs
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 6 secs
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 6 secs
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 6 secs
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs
Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 6 secs
Total REAL time to Router completion: 6 secs
Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs
Total REAL time to Router completion: 7 secs
Total CPU time to Router completion: 6 secs
Partition Implementation Status
@@ -153,17 +153,17 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net tog | SETUP | N/A| 1.051ns| N/A| 0
gleled | HOLD | 0.454ns| | 0| 0
Autotimespec constraint for clock net tog | SETUP | N/A| 0.990ns| N/A| 0
gleled | HOLD | 0.436ns| | 0| 0
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net CLK | SETUP | N/A| 3.484ns| N/A| 0
Autotimespec constraint for clock net CLK | SETUP | N/A| 3.836ns| N/A| 0
27MHz_BUFGP | HOLD | 0.530ns| | 0| 0
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net con | SETUP | N/A| 3.450ns| N/A| 0
t100k_8_BUFG | HOLD | 0.402ns| | 0| 0
Autotimespec constraint for clock net con | SETUP | N/A| 3.725ns| N/A| 0
t100k_8_BUFG | HOLD | 0.282ns| | 0| 0
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net con | SETUP | N/A| 2.554ns| N/A| 0
taux_5_BUFG | HOLD | 0.434ns| | 0| 0
Autotimespec constraint for clock net con | SETUP | N/A| 2.602ns| N/A| 0
taux_5_BUFG | HOLD | 0.404ns| | 0| 0
----------------------------------------------------------------------------------------------------------
@@ -181,8 +181,8 @@ All signals are completely routed.
WARNING:Par:283 - There are 12 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 6 secs
Total CPU time to PAR completion: 6 secs
Total REAL time to PAR completion: 8 secs
Total CPU time to PAR completion: 7 secs
Peak Memory Usage: 309 MB

2
textovhdl.pcf
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@@ -1,5 +1,5 @@
//! **************************************************************************
// Written by: Map P.20131013 on Wed Jun 08 12:43:02 2022
// Written by: Map P.20131013 on Wed Jun 08 12:52:52 2022
//! **************************************************************************
SCHEMATIC START;

2
textovhdl.ptwx
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@@ -329,4 +329,4 @@
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net toggleled</twConstName><twConstData type="SETUP" best="1.051" units="ns" score="0"/><twConstData type="HOLD" slack="0.454" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net CLK27MHz_BUFGP</twConstName><twConstData type="SETUP" best="3.484" units="ns" score="0"/><twConstData type="HOLD" slack="0.530" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net cont100k_8_BUFG</twConstName><twConstData type="SETUP" best="3.450" units="ns" score="0"/><twConstData type="HOLD" slack="0.402" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net contaux_5_BUFG</twConstName><twConstData type="SETUP" best="2.554" units="ns" score="0"/><twConstData type="HOLD" slack="0.434" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="10">0</twUnmetConstCnt><twInfo anchorID="11">INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</twInfo></twSumRpt></twBody></twReport>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net toggleled</twConstName><twConstData type="SETUP" best="0.990" units="ns" score="0"/><twConstData type="HOLD" slack="0.436" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net CLK27MHz_BUFGP</twConstName><twConstData type="SETUP" best="3.836" units="ns" score="0"/><twConstData type="HOLD" slack="0.530" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net cont100k_8_BUFG</twConstName><twConstData type="SETUP" best="3.725" units="ns" score="0"/><twConstData type="HOLD" slack="0.282" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net contaux_5_BUFG</twConstName><twConstData type="SETUP" best="2.602" units="ns" score="0"/><twConstData type="HOLD" slack="0.404" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="10">0</twUnmetConstCnt><twInfo anchorID="11">INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</twInfo></twSumRpt></twBody></twReport>

8
textovhdl.syr
View File

@@ -10,7 +10,7 @@ Total CPU time to Xst completion: 0.11 secs
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.11 secs
Total CPU time to Xst completion: 0.12 secs
--> Reading design: textovhdl.prj
@@ -156,7 +156,7 @@ WARNING:Xst:653 - Signal <num0> is used but never assigned. This sourceless sign
Found 4-bit register for signal <bLeds>.
Found 24-bit register for signal <cont100k>.
Found 24-bit register for signal <contaux>.
Found 2-bit register for signal <ffmicro<19:18>>.
Found 2-bit register for signal <ffmicro<18:17>>.
Found 24-bit adder for signal <contaux[23]_GND_5_o_add_9_OUT> created at line 81.
Found 24-bit subtractor for signal <GND_5_o_GND_5_o_sub_8_OUT<23:0>> created at line 79.
Summary:
@@ -670,11 +670,11 @@ toggleled | 2.260| | | |
Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 7.06 secs
Total CPU time to Xst completion: 6.97 secs
-->
Total memory usage is 259080 kilobytes
Total memory usage is 258824 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 38 ( 0 filtered)

8
textovhdl.twr
View File

@@ -37,7 +37,7 @@ Clock CLK27MHz to Pad
|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
------------+-----------------+------------+-----------------+------------+------------------+--------+
GPIO<0> | 9.718(R)| SLOW | 4.138(R)| FAST |CLK27MHz_BUFGP | 0.000|
GPIO<0> | 9.716(R)| SLOW | 4.139(R)| FAST |CLK27MHz_BUFGP | 0.000|
------------+-----------------+------------+-----------------+------------+------------------+--------+
Clock to Setup on destination clock CLK27MHz
@@ -45,18 +45,18 @@ Clock to Setup on destination clock CLK27MHz
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK27MHz | 3.484| | | |
CLK27MHz | 3.836| | | |
---------------+---------+---------+---------+---------+
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
GPIO<6> |LEDS<3> | 9.673|
GPIO<6> |LEDS<3> | 9.433|
---------------+---------------+---------+
Analysis completed Wed Jun 08 12:43:19 2022
Analysis completed Wed Jun 08 12:53:12 2022
--------------------------------------------------------------------------------
Trace Settings:

2
textovhdl.twx
View File

@@ -333,7 +333,7 @@
-n 3 -fastpaths -xml textovhdl.twx textovhdl.ncd -o textovhdl.twr textovhdl.pcf
-ucf restricoes.ucf
</twCmdLine><twDesign>textovhdl.ncd</twDesign><twDesignPath>textovhdl.ncd</twDesignPath><twPCF>textovhdl.pcf</twPCF><twPcfPath>textovhdl.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="csg324"><twDevName>xc6slx16</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-2</twSpeedGrade><twSpeedVer>PRODUCTION 1.23 2013-10-13</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:2698 - No timing constraints found, doing default enumeration.</twInfo><twInfo anchorID="3">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="4">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="5">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twDataSheet anchorID="6" twNameLen="15"><twClk2OutList anchorID="7" twDestWidth="7" twPhaseWidth="14"><twSrc>CLK27MHz</twSrc><twClk2Out twOutPad = "GPIO&lt;0&gt;" twMinTime = "4.138" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "9.718" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK27MHz_BUFGP" twClkPhase="0.000" ></twClk2Out></twClk2OutList><twClk2SUList anchorID="8" twDestWidth="8"><twDest>CLK27MHz</twDest><twClk2SU><twSrc>CLK27MHz</twSrc><twRiseRise>3.484</twRiseRise></twClk2SU></twClk2SUList><twPad2PadList anchorID="9" twSrcWidth="7" twDestWidth="7"><twPad2Pad><twSrc>GPIO&lt;6&gt;</twSrc><twDest>LEDS&lt;3&gt;</twDest><twDel>9.673</twDel></twPad2Pad></twPad2PadList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twFoot><twTimestamp>Wed Jun 08 12:43:19 2022 </twTimestamp></twFoot><twClientInfo anchorID="10"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
</twCmdLine><twDesign>textovhdl.ncd</twDesign><twDesignPath>textovhdl.ncd</twDesignPath><twPCF>textovhdl.pcf</twPCF><twPcfPath>textovhdl.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="csg324"><twDevName>xc6slx16</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-2</twSpeedGrade><twSpeedVer>PRODUCTION 1.23 2013-10-13</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:2698 - No timing constraints found, doing default enumeration.</twInfo><twInfo anchorID="3">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="4">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="5">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twDataSheet anchorID="6" twNameLen="15"><twClk2OutList anchorID="7" twDestWidth="7" twPhaseWidth="14"><twSrc>CLK27MHz</twSrc><twClk2Out twOutPad = "GPIO&lt;0&gt;" twMinTime = "4.139" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "9.716" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK27MHz_BUFGP" twClkPhase="0.000" ></twClk2Out></twClk2OutList><twClk2SUList anchorID="8" twDestWidth="8"><twDest>CLK27MHz</twDest><twClk2SU><twSrc>CLK27MHz</twSrc><twRiseRise>3.836</twRiseRise></twClk2SU></twClk2SUList><twPad2PadList anchorID="9" twSrcWidth="7" twDestWidth="7"><twPad2Pad><twSrc>GPIO&lt;6&gt;</twSrc><twDest>LEDS&lt;3&gt;</twDest><twDel>9.433</twDel></twPad2Pad></twPad2PadList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twFoot><twTimestamp>Wed Jun 08 12:53:12 2022 </twTimestamp></twFoot><twClientInfo anchorID="10"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
Peak Memory Usage: 219 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>

2
textovhdl.unroutes
View File

@@ -1,7 +1,7 @@
Release 14.7 - par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Wed Jun 08 12:43:12 2022
Wed Jun 08 12:53:05 2022
All signals are completely routed.

2
textovhdl.vhd
View File

@@ -53,7 +53,7 @@ process (clk100k)
begin
if (clk100k'event and clk100k = '1') then
ffmicro <= contmicro;
toggleled <= andcontzero and (not ffmicro(19)) and ffmicro(18);
toggleled <= andcontzero and (not ffmicro(18)) and ffmicro(17);
end if;
end process;

2
textovhdl_guide.ncd
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File diff suppressed because one or more lines are too long

22
textovhdl_map.map
View File

@@ -10,7 +10,7 @@ Target Device : xc6slx16
Target Package : csg324
Target Speed : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Wed Jun 08 12:42:55 2022
Mapped Date : Wed Jun 08 12:52:44 2022
Mapping design into LUTs...
Running directed packing...
@@ -49,21 +49,21 @@ Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:7ce1aa2f) REAL time: 6 secs
Phase 9.8 Global Placement
..........
...
Phase 9.8 Global Placement (Checksum:dba6c2e8) REAL time: 6 secs
......
.....
Phase 9.8 Global Placement (Checksum:1d5364ab) REAL time: 7 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:dba6c2e8) REAL time: 6 secs
Phase 10.5 Local Placement Optimization (Checksum:1d5364ab) REAL time: 7 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:941e67b8) REAL time: 7 secs
Phase 11.18 Placement Optimization (Checksum:710eadcb) REAL time: 7 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:941e67b8) REAL time: 7 secs
Phase 12.5 Local Placement Optimization (Checksum:710eadcb) REAL time: 7 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:93cf0c93) REAL time: 7 secs
Phase 13.34 Placement Validation (Checksum:710eadcb) REAL time: 7 secs
Total REAL time to Placer completion: 7 secs
Total CPU time to Placer completion: 7 secs
@@ -95,7 +95,7 @@ Slice Logic Utilization:
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 41 out of 2,278 1%
Number of occupied Slices: 42 out of 2,278 1%
Number of MUXCYs used: 44 out of 4,556 1%
Number of LUT Flip Flop pairs used: 132
Number with an unused Flip Flop: 56 out of 132 42%
@@ -142,8 +142,8 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.39
Peak Memory Usage: 349 MB
Total REAL time to MAP completion: 7 secs
Peak Memory Usage: 352 MB
Total REAL time to MAP completion: 8 secs
Total CPU time to MAP completion: 7 secs
Mapping completed.

8
textovhdl_map.mrp
View File

@@ -10,7 +10,7 @@ Target Device : xc6slx16
Target Package : csg324
Target Speed : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Wed Jun 08 12:42:55 2022
Mapped Date : Wed Jun 08 12:52:44 2022
Design Summary
--------------
@@ -35,7 +35,7 @@ Slice Logic Utilization:
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 41 out of 2,278 1%
Number of occupied Slices: 42 out of 2,278 1%
Number of MUXCYs used: 44 out of 4,556 1%
Number of LUT Flip Flop pairs used: 132
Number with an unused Flip Flop: 56 out of 132 42%
@@ -82,8 +82,8 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.39
Peak Memory Usage: 349 MB
Total REAL time to MAP completion: 7 secs
Peak Memory Usage: 352 MB
Total REAL time to MAP completion: 8 secs
Total CPU time to MAP completion: 7 secs
Table of Contents

2
textovhdl_map.ncd
View File

File diff suppressed because one or more lines are too long

2
textovhdl_map.ngm
View File

File diff suppressed because one or more lines are too long

10
textovhdl_map.xrpt
View File

@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Map" timeStamp="Wed Jun 08 12:43:02 2022">
<application stringID="Map" timeStamp="Wed Jun 08 12:52:53 2022">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@@ -117,8 +117,8 @@
<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="0"/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="356940"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="7 secs "/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="360012"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="8 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="7 secs "/>
</section>
<section stringID="MAP_SLICE_REPORTING">
@@ -151,10 +151,10 @@
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="2"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item>
<item AVAILABLE="2278" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="41">
<item AVAILABLE="2278" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="42">
<item AVAILABLE="595" dataType="int" stringID="MAP_NUM_SLICEL" value="11"/>
<item AVAILABLE="544" dataType="int" stringID="MAP_NUM_SLICEM" value="0"/>
<item AVAILABLE="1139" dataType="int" stringID="MAP_NUM_SLICEX" value="30"/>
<item AVAILABLE="1139" dataType="int" stringID="MAP_NUM_SLICEX" value="31"/>
</item>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="132">
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="56"/>

2
textovhdl_ngdbuild.xrpt
View File

@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Wed Jun 08 12:42:52 2022">
<application stringID="NgdBuild" timeStamp="Wed Jun 08 12:52:42 2022">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>

2
textovhdl_pad.csv
View File

@@ -1,7 +1,7 @@
#Release 14.7 - par P.20131013 (nt64)
#Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
#Wed Jun 08 12:43:12 2022
#Wed Jun 08 12:53:05 2022
#
## NOTE: This file is designed to be imported into a spreadsheet program
1 #Release 14.7 - par P.20131013 (nt64)
2 #Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
3 #Wed Jun 08 12:43:12 2022 #Wed Jun 08 12:53:05 2022
4 #
5 ## NOTE: This file is designed to be imported into a spreadsheet program
6 # such as Microsoft Excel for viewing, printing and sorting. The |
7 # character is used as the data field separator. This file is also designed

2
textovhdl_pad.txt
View File

@@ -1,7 +1,7 @@
Release 14.7 - par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Wed Jun 08 12:43:12 2022
Wed Jun 08 12:53:05 2022
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:

14
textovhdl_par.xrpt
View File

@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="par" timeStamp="Wed Jun 08 12:43:09 2022">
<application stringID="par" timeStamp="Wed Jun 08 12:53:02 2022">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@@ -59,12 +59,12 @@
</task>
<task stringID="PAR_PAR">
<section stringID="PAR_DESIGN_SUMMARY">
<item stringID="PAR_REAL_TIME_COMPLETION_ROUTER" value="6 secs "/>
<item stringID="PAR_REAL_TIME_COMPLETION_ROUTER" value="7 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="6 secs "/>
<item dataType="int" stringID="PAR_UNROUTES" value="0"/>
<item dataType="float" stringID="PAR_TIMING_SCORE" value="0.000000"/>
<item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="6 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="6 secs "/>
<item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="8 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="7 secs "/>
</section>
</task>
<task stringID="PAR_par">
@@ -2296,7 +2296,7 @@
</task>
</application>
<application stringID="Par" timeStamp="Wed Jun 08 12:43:09 2022">
<application stringID="Par" timeStamp="Wed Jun 08 12:53:02 2022">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@@ -2371,10 +2371,10 @@
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_CARRY4" value="2"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item>
<item AVAILABLE="2278" dataType="int" stringID="PAR_OCCUPIED_SLICES" value="41">
<item AVAILABLE="2278" dataType="int" stringID="PAR_OCCUPIED_SLICES" value="42">
<item AVAILABLE="595" dataType="int" stringID="PAR_NUM_SLICEL" value="11"/>
<item AVAILABLE="544" dataType="int" stringID="PAR_NUM_SLICEM" value="0"/>
<item AVAILABLE="1139" dataType="int" stringID="PAR_NUM_SLICEX" value="30"/>
<item AVAILABLE="1139" dataType="int" stringID="PAR_NUM_SLICEX" value="31"/>
</item>
<item dataType="int" stringID="PAR_OCCUPIED_LUT_AND_FF" value="132">
<item dataType="int" stringID="PAR_OCCUPIED_LUT_ONLY" value="56"/>

27
textovhdl_summary.html
View File

@@ -2,7 +2,7 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>textovhdl Project Status (06/08/2022 - 12:43:44)</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>textovhdl Project Status (06/08/2022 - 12:53:27)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>Aula20220608.xise</TD>
@@ -19,12 +19,13 @@
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc6slx16-2csg324</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>&nbsp;</TD>
<TD>
No Errors</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD>&nbsp;</TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/*.xmsgs?&DataKey=Warning'>56 Warnings (0 new)</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
@@ -155,7 +156,7 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
<TD ALIGN=RIGHT>41</TD>
<TD ALIGN=RIGHT>42</TD>
<TD ALIGN=RIGHT>2,278</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
@@ -390,21 +391,21 @@ System Settings</A>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Jun 8 12:42:38 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/xst.xmsgs?&DataKey=Warning'>38 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/xst.xmsgs?&DataKey=Info'>3 Infos (1 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl.bld'>Translation Report</A></TD><TD>Current</TD><TD>Wed Jun 8 12:42:52 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>4 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Wed Jun 8 12:43:03 2022</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Wed Jun 8 12:43:12 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/par.xmsgs?&DataKey=Warning'>14 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/par.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Jun 8 12:52:33 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/xst.xmsgs?&DataKey=Warning'>38 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/xst.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl.bld'>Translation Report</A></TD><TD>Current</TD><TD>Wed Jun 8 12:52:42 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>4 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Wed Jun 8 12:52:53 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/map.xmsgs?&DataKey=Info'>8 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Wed Jun 8 12:53:05 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/par.xmsgs?&DataKey=Warning'>14 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/par.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Wed Jun 8 12:43:19 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/trce.xmsgs?&DataKey=Info'>4 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Wed Jun 8 12:43:41 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Wed Jun 8 12:53:12 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/trce.xmsgs?&DataKey=Info'>4 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Wed Jun 8 12:53:25 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Jun 8 12:43:42 2022</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Jun 8 12:43:43 2022</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Jun 8 12:53:25 2022</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Jun 8 12:53:27 2022</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 06/08/2022 - 12:43:44</center>
<br><center><b>Date Generated:</b> 06/08/2022 - 12:53:27</center>
</BODY></HTML>

2
textovhdl_summary.xml
View File

@@ -4,7 +4,7 @@
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DesignSummary rev="8">
<DesignSummary rev="10">
<CmdHistory>
</CmdHistory>
</DesignSummary>

544
textovhdl_usage.xml
View File

@@ -4,468 +4,466 @@
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DeviceUsageSummary rev="8">
<DesignStatistics TimeStamp="Wed Jun 08 12:43:41 2022"><group name="NetStatistics">
<item name="NumNets_Active" rev="8">
<DeviceUsageSummary rev="10">
<DesignStatistics TimeStamp="Wed Jun 08 12:53:24 2022"><group name="NetStatistics">
<item name="NumNets_Active" rev="10">
<attrib name="value" value="185"/></item>
<item name="NumNets_Vcc" rev="8">
<item name="NumNets_Vcc" rev="10">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Active_BOUNCEACROSS" rev="8">
<attrib name="value" value="6"/></item>
<item name="NumNodesOfType_Active_BOUNCEIN" rev="8">
<attrib name="value" value="24"/></item>
<item name="NumNodesOfType_Active_BUFGOUT" rev="8">
<attrib name="value" value="3"/></item>
<item name="NumNodesOfType_Active_BUFHINP2OUT" rev="8">
<item name="NumNodesOfType_Active_BOUNCEACROSS" rev="10">
<attrib name="value" value="4"/></item>
<item name="NumNodesOfType_Active_CLKPIN" rev="8">
<attrib name="value" value="30"/></item>
<item name="NumNodesOfType_Active_CLKPINFEED" rev="8">
<attrib name="value" value="12"/></item>
<item name="NumNodesOfType_Active_CNTRLPIN" rev="8">
<item name="NumNodesOfType_Active_BOUNCEIN" rev="10">
<attrib name="value" value="23"/></item>
<item name="NumNodesOfType_Active_DOUBLE" rev="8">
<attrib name="value" value="95"/></item>
<item name="NumNodesOfType_Active_GENERIC" rev="8">
<attrib name="value" value="10"/></item>
<item name="NumNodesOfType_Active_GLOBAL" rev="8">
<attrib name="value" value="26"/></item>
<item name="NumNodesOfType_Active_INPUT" rev="8">
<attrib name="value" value="11"/></item>
<item name="NumNodesOfType_Active_IOBIN2OUT" rev="8">
<attrib name="value" value="8"/></item>
<item name="NumNodesOfType_Active_IOBOUTPUT" rev="8">
<attrib name="value" value="8"/></item>
<item name="NumNodesOfType_Active_LUTINPUT" rev="8">
<attrib name="value" value="470"/></item>
<item name="NumNodesOfType_Active_OUTBOUND" rev="8">
<attrib name="value" value="145"/></item>
<item name="NumNodesOfType_Active_OUTPUT" rev="8">
<attrib name="value" value="157"/></item>
<item name="NumNodesOfType_Active_PADINPUT" rev="8">
<attrib name="value" value="7"/></item>
<item name="NumNodesOfType_Active_PADOUTPUT" rev="8">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Active_PINBOUNCE" rev="8">
<attrib name="value" value="75"/></item>
<item name="NumNodesOfType_Active_PINFEED" rev="8">
<attrib name="value" value="525"/></item>
<item name="NumNodesOfType_Active_QUAD" rev="8">
<attrib name="value" value="42"/></item>
<item name="NumNodesOfType_Active_REGINPUT" rev="8">
<item name="NumNodesOfType_Active_BUFGOUT" rev="10">
<attrib name="value" value="3"/></item>
<item name="NumNodesOfType_Active_SINGLE" rev="8">
<attrib name="value" value="237"/></item>
<item name="NumNodesOfType_Vcc_HVCCOUT" rev="8">
<attrib name="value" value="13"/></item>
<item name="NumNodesOfType_Vcc_LUTINPUT" rev="8">
<item name="NumNodesOfType_Active_BUFHINP2OUT" rev="10">
<attrib name="value" value="4"/></item>
<item name="NumNodesOfType_Active_CLKPIN" rev="10">
<attrib name="value" value="30"/></item>
<item name="NumNodesOfType_Active_CLKPINFEED" rev="10">
<attrib name="value" value="12"/></item>
<item name="NumNodesOfType_Active_CNTRLPIN" rev="10">
<attrib name="value" value="23"/></item>
<item name="NumNodesOfType_Active_DOUBLE" rev="10">
<attrib name="value" value="113"/></item>
<item name="NumNodesOfType_Active_GENERIC" rev="10">
<attrib name="value" value="10"/></item>
<item name="NumNodesOfType_Active_GLOBAL" rev="10">
<attrib name="value" value="27"/></item>
<item name="NumNodesOfType_Active_INPUT" rev="10">
<attrib name="value" value="11"/></item>
<item name="NumNodesOfType_Active_IOBIN2OUT" rev="10">
<attrib name="value" value="8"/></item>
<item name="NumNodesOfType_Active_IOBOUTPUT" rev="10">
<attrib name="value" value="8"/></item>
<item name="NumNodesOfType_Active_LUTINPUT" rev="10">
<attrib name="value" value="470"/></item>
<item name="NumNodesOfType_Active_OUTBOUND" rev="10">
<attrib name="value" value="141"/></item>
<item name="NumNodesOfType_Active_OUTPUT" rev="10">
<attrib name="value" value="152"/></item>
<item name="NumNodesOfType_Active_PADINPUT" rev="10">
<attrib name="value" value="7"/></item>
<item name="NumNodesOfType_Active_PADOUTPUT" rev="10">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Active_PINBOUNCE" rev="10">
<attrib name="value" value="76"/></item>
<item name="NumNodesOfType_Active_PINFEED" rev="10">
<attrib name="value" value="525"/></item>
<item name="NumNodesOfType_Active_QUAD" rev="10">
<attrib name="value" value="40"/></item>
<item name="NumNodesOfType_Active_REGINPUT" rev="10">
<attrib name="value" value="3"/></item>
<item name="NumNodesOfType_Active_SINGLE" rev="10">
<attrib name="value" value="224"/></item>
<item name="NumNodesOfType_Vcc_HVCCOUT" rev="10">
<attrib name="value" value="14"/></item>
<item name="NumNodesOfType_Vcc_LUTINPUT" rev="10">
<attrib name="value" value="42"/></item>
<item name="NumNodesOfType_Vcc_PINFEED" rev="8">
<item name="NumNodesOfType_Vcc_PINFEED" rev="10">
<attrib name="value" value="42"/></item>
</group>
<group name="SiteStatistics">
<item name="BUFG-BUFGMUX" rev="8">
<item name="BUFG-BUFGMUX" rev="10">
<attrib name="value" value="3"/></item>
<item name="IOB-IOBM" rev="8">
<item name="IOB-IOBM" rev="10">
<attrib name="value" value="10"/></item>
<item name="IOB-IOBS" rev="8">
<item name="IOB-IOBS" rev="10">
<attrib name="value" value="11"/></item>
<item name="SLICEL-SLICEM" rev="8">
<item name="SLICEL-SLICEM" rev="10">
<attrib name="value" value="11"/></item>
<item name="SLICEX-SLICEL" rev="8">
<attrib name="value" value="10"/></item>
<item name="SLICEX-SLICEM" rev="8">
<attrib name="value" value="6"/></item>
<item name="SLICEX-SLICEL" rev="10">
<attrib name="value" value="11"/></item>
<item name="SLICEX-SLICEM" rev="10">
<attrib name="value" value="3"/></item>
</group>
<group name="MiscellaneousStatistics">
<item name="AGG_BONDED_IO" rev="7">
<item name="AGG_BONDED_IO" rev="9">
<attrib name="value" value="21"/></item>
<item name="AGG_IO" rev="7">
<item name="AGG_IO" rev="9">
<attrib name="value" value="21"/></item>
<item name="AGG_LOCED_IO" rev="7">
<item name="AGG_LOCED_IO" rev="9">
<attrib name="value" value="21"/></item>
<item name="AGG_SLICE" rev="7">
<attrib name="value" value="41"/></item>
<item name="NUM_BONDED_IOB" rev="7">
<item name="AGG_SLICE" rev="9">
<attrib name="value" value="42"/></item>
<item name="NUM_BONDED_IOB" rev="9">
<attrib name="value" value="21"/></item>
<item name="NUM_BSFULL" rev="7">
<item name="NUM_BSFULL" rev="9">
<attrib name="value" value="73"/></item>
<item name="NUM_BSLUTONLY" rev="7">
<item name="NUM_BSLUTONLY" rev="9">
<attrib name="value" value="56"/></item>
<item name="NUM_BSREGONLY" rev="7">
<item name="NUM_BSREGONLY" rev="9">
<attrib name="value" value="3"/></item>
<item name="NUM_BSUSED" rev="7">
<item name="NUM_BSUSED" rev="9">
<attrib name="value" value="132"/></item>
<item name="NUM_BUFG" rev="7">
<item name="NUM_BUFG" rev="9">
<attrib name="value" value="3"/></item>
<item name="NUM_LOCED_IOB" rev="7">
<item name="NUM_LOCED_IOB" rev="9">
<attrib name="value" value="21"/></item>
<item name="NUM_LOGIC_O5ANDO6" rev="7">
<item name="NUM_LOGIC_O5ANDO6" rev="9">
<attrib name="value" value="30"/></item>
<item name="NUM_LOGIC_O5ONLY" rev="7">
<item name="NUM_LOGIC_O5ONLY" rev="9">
<attrib name="value" value="12"/></item>
<item name="NUM_LOGIC_O6ONLY" rev="7">
<item name="NUM_LOGIC_O6ONLY" rev="9">
<attrib name="value" value="85"/></item>
<item name="NUM_LUT_RT_DRIVES_CARRY4" rev="7">
<item name="NUM_LUT_RT_DRIVES_CARRY4" rev="9">
<attrib name="value" value="2"/></item>
<item name="NUM_LUT_RT_EXO6" rev="7">
<item name="NUM_LUT_RT_EXO6" rev="9">
<attrib name="value" value="2"/></item>
<item name="NUM_LUT_RT_O6" rev="7">
<item name="NUM_LUT_RT_O6" rev="9">
<attrib name="value" value="12"/></item>
<item name="NUM_SLICEL" rev="7">
<item name="NUM_SLICEL" rev="9">
<attrib name="value" value="11"/></item>
<item name="NUM_SLICEX" rev="7">
<attrib name="value" value="30"/></item>
<item name="NUM_SLICE_CARRY4" rev="7">
<item name="NUM_SLICEX" rev="9">
<attrib name="value" value="31"/></item>
<item name="NUM_SLICE_CARRY4" rev="9">
<attrib name="value" value="11"/></item>
<item name="NUM_SLICE_CONTROLSET" rev="7">
<item name="NUM_SLICE_CONTROLSET" rev="9">
<attrib name="value" value="8"/></item>
<item name="NUM_SLICE_CYINIT" rev="7">
<item name="NUM_SLICE_CYINIT" rev="9">
<attrib name="value" value="174"/></item>
<item name="NUM_SLICE_FF" rev="7">
<item name="NUM_SLICE_FF" rev="9">
<attrib name="value" value="81"/></item>
<item name="NUM_SLICE_UNUSEDCTRL" rev="7">
<attrib name="value" value="11"/></item>
<item name="NUM_UNUSABLE_FF_BELS" rev="7">
<item name="NUM_SLICE_UNUSEDCTRL" rev="9">
<attrib name="value" value="12"/></item>
<item name="NUM_UNUSABLE_FF_BELS" rev="9">
<attrib name="value" value="31"/></item>
</group>
</DesignStatistics>
<DeviceUsage TimeStamp="Wed Jun 08 12:43:41 2022"><group name="SiteSummary">
<item name="BUFG" rev="8">
<DeviceUsage TimeStamp="Wed Jun 08 12:53:24 2022"><group name="SiteSummary">
<item name="BUFG" rev="10">
<attrib name="total" value="1000000"/><attrib name="used" value="3"/></item>
<item name="BUFG_BUFG" rev="8">
<item name="BUFG_BUFG" rev="10">
<attrib name="total" value="1000000"/><attrib name="used" value="3"/></item>
<item name="CARRY4" rev="8">
<item name="CARRY4" rev="10">
<attrib name="total" value="1000000"/><attrib name="used" value="11"/></item>
<item name="FF_SR" rev="8">
<item name="FF_SR" rev="10">
<attrib name="total" value="1000000"/><attrib name="used" value="6"/></item>
<item name="HARD0" rev="8">
<item name="HARD0" rev="10">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="HARD1" rev="8">
<item name="HARD1" rev="10">
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="IOB" rev="8">
<item name="IOB" rev="10">
<attrib name="total" value="1000000"/><attrib name="used" value="21"/></item>
<item name="IOB_IMUX" rev="8">
<item name="IOB_IMUX" rev="10">
<attrib name="total" value="1000000"/><attrib name="used" value="14"/></item>
<item name="IOB_INBUF" rev="8">
<item name="IOB_INBUF" rev="10">
<attrib name="total" value="1000000"/><attrib name="used" value="14"/></item>
<item name="IOB_OUTBUF" rev="8">
<item name="IOB_OUTBUF" rev="10">
<attrib name="total" value="1000000"/><attrib name="used" value="7"/></item>
<item name="LUT5" rev="8">
<item name="LUT5" rev="10">
<attrib name="total" value="1000000"/><attrib name="used" value="42"/></item>
<item name="LUT6" rev="8">
<item name="LUT6" rev="10">
<attrib name="total" value="1000000"/><attrib name="used" value="129"/></item>
<item name="PAD" rev="8">
<item name="PAD" rev="10">
<attrib name="total" value="1000000"/><attrib name="used" value="21"/></item>
<item name="REG_SR" rev="8">
<item name="REG_SR" rev="10">
<attrib name="total" value="1000000"/><attrib name="used" value="75"/></item>
<item name="SLICEL" rev="8">
<item name="SLICEL" rev="10">
<attrib name="total" value="1000000"/><attrib name="used" value="11"/></item>
<item name="SLICEX" rev="8">
<attrib name="total" value="1000000"/><attrib name="used" value="30"/></item>
<item name="SLICEX" rev="10">
<attrib name="total" value="1000000"/><attrib name="used" value="31"/></item>
</group>
</DeviceUsage>
<ReportConfigData TimeStamp="Wed Jun 08 12:43:41 2022"><group name="REG_SR">
<item name="CK" rev="8">
<ReportConfigData TimeStamp="Wed Jun 08 12:53:24 2022"><group name="REG_SR">
<item name="CK" rev="10">
<attrib name="CK" value="52"/><attrib name="CK_INV" value="23"/></item>
<item name="LATCH_OR_FF" rev="8">
<item name="LATCH_OR_FF" rev="10">
<attrib name="FF" value="75"/></item>
<item name="SRINIT" rev="8">
<item name="SRINIT" rev="10">
<attrib name="SRINIT0" value="75"/></item>
<item name="SYNC_ATTR" rev="8">
<item name="SYNC_ATTR" rev="10">
<attrib name="ASYNC" value="64"/><attrib name="SYNC" value="11"/></item>
</group>
<group name="SLICEL">
<item name="CLK" rev="8">
<item name="CLK" rev="10">
<attrib name="CLK" value="2"/><attrib name="CLK_INV" value="3"/></item>
</group>
<group name="IOB_OUTBUF">
<item name="DRIVEATTRBOX" rev="8">
<item name="DRIVEATTRBOX" rev="10">
<attrib name="12" value="7"/></item>
<item name="SLEW" rev="8">
<item name="SLEW" rev="10">
<attrib name="SLOW" value="7"/></item>
<item name="SUSPEND" rev="8">
<item name="SUSPEND" rev="10">
<attrib name="3STATE" value="7"/></item>
</group>
<group name="SLICEX">
<item name="CLK" rev="8">
<item name="CLK" rev="10">
<attrib name="CLK" value="21"/><attrib name="CLK_INV" value="4"/></item>
</group>
<group name="FF_SR">
<item name="CK" rev="8">
<item name="CK" rev="10">
<attrib name="CK" value="3"/><attrib name="CK_INV" value="3"/></item>
<item name="SRINIT" rev="8">
<item name="SRINIT" rev="10">
<attrib name="SRINIT0" value="6"/></item>
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<item name="AX" rev="10">
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</ReportPinData>

2
textovhdl_xst.xrpt
View File

@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Wed Jun 08 12:42:31 2022">
<application stringID="Xst" timeStamp="Wed Jun 08 12:52:26 2022">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>

151
usage_statistics_webtalk.html
View File

@@ -17,7 +17,7 @@
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project ID (random number)</B></TD>
<TD><xtag-property name="RandomID">bd16c3ee05c44948bef10dae3c70184a</xtag-property>.<xtag-property name="ProjectID">047E6D81914F4B9E9C732FAABBF95C82</xtag-property>.<xtag-property name="ProjectIteration">4</xtag-property></TD>
<TD><xtag-property name="RandomID">bd16c3ee05c44948bef10dae3c70184a</xtag-property>.<xtag-property name="ProjectID">047E6D81914F4B9E9C732FAABBF95C82</xtag-property>.<xtag-property name="ProjectIteration">5</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Package:</B></TD>
<TD><xtag-property name="TargetPackage">csg324</xtag-property></TD>
</TR>
@@ -29,7 +29,7 @@
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Date Generated</B></TD>
<TD><xtag-property name="Date Generated">2022-06-08T12:43:42</xtag-property></TD>
<TD><xtag-property name="Date Generated">2022-06-08T12:53:25</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Tool Flow</B></TD>
<TD><xtag-property name="ToolFlow">ISE</xtag-property></TD>
</TR>
@@ -105,7 +105,7 @@
<LI><xtag-item1>AGG_BONDED_IO=21</xtag-item1></LI>
<LI><xtag-item1>AGG_IO=21</xtag-item1></LI>
<LI><xtag-item1>AGG_LOCED_IO=21</xtag-item1></LI>
<LI><xtag-item1>AGG_SLICE=41</xtag-item1></LI>
<LI><xtag-item1>AGG_SLICE=42</xtag-item1></LI>
<LI><xtag-item1>NUM_BONDED_IOB=21</xtag-item1></LI>
<LI><xtag-item1>NUM_BSFULL=73</xtag-item1></LI>
<LI><xtag-item1>NUM_BSLUTONLY=56</xtag-item1></LI>
@@ -120,12 +120,12 @@
<LI><xtag-item1>NUM_LUT_RT_EXO6=2</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_O6=12</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEL=11</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEX=30</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEX=31</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CARRY4=11</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CONTROLSET=8</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CYINIT=174</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_FF=81</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_UNUSEDCTRL=11</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_UNUSEDCTRL=12</xtag-item1></LI>
<LI><xtag-item1>NUM_UNUSABLE_FF_BELS=31</xtag-item1></LI>
</UL>
</xtag-group>
@@ -135,30 +135,30 @@
<UL>
<LI><xtag-item1>NumNets_Active=185</xtag-item1></LI>
<LI><xtag-item1>NumNets_Vcc=1</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEACROSS=6</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEIN=24</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEACROSS=4</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEIN=23</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BUFGOUT=3</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BUFHINP2OUT=4</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=30</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPINFEED=12</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CNTRLPIN=23</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=95</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=113</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GENERIC=10</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=26</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=27</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_INPUT=11</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBIN2OUT=8</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBOUTPUT=8</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_LUTINPUT=470</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTBOUND=145</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=157</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTBOUND=141</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=152</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PADINPUT=7</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PADOUTPUT=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINBOUNCE=75</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINBOUNCE=76</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINFEED=525</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_QUAD=42</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_QUAD=40</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_REGINPUT=3</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_SINGLE=237</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_HVCCOUT=13</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_SINGLE=224</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_HVCCOUT=14</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_LUTINPUT=42</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PINFEED=42</xtag-item1></LI>
</UL>
@@ -169,8 +169,8 @@
<LI><xtag-item1>IOB-IOBM=10</xtag-item1></LI>
<LI><xtag-item1>IOB-IOBS=11</xtag-item1></LI>
<LI><xtag-item1>SLICEL-SLICEM=11</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEL=10</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEM=6</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEL=11</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEM=3</xtag-item1></LI>
</UL>
</xtag-group>
</TD>
@@ -194,7 +194,7 @@
<LI><xtag-item2>PAD=21</xtag-item2></LI>
<LI><xtag-item2>REG_SR=75</xtag-item2></LI>
<LI><xtag-item2>SLICEL=11</xtag-item2></LI>
<LI><xtag-item2>SLICEX=30</xtag-item2></LI>
<LI><xtag-item2>SLICEX=31</xtag-item2></LI>
</UL>
</xtag-group>
</TD>
@@ -392,21 +392,21 @@
</xtag-group>
<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name>
<UL>
<LI><xtag-item1>A=6</xtag-item1></LI>
<LI><xtag-item1>A1=10</xtag-item1></LI>
<LI><xtag-item1>A2=19</xtag-item1></LI>
<LI><xtag-item1>A3=20</xtag-item1></LI>
<LI><xtag-item1>A4=23</xtag-item1></LI>
<LI><xtag-item1>A5=22</xtag-item1></LI>
<LI><xtag-item1>A6=23</xtag-item1></LI>
<LI><xtag-item1>A=5</xtag-item1></LI>
<LI><xtag-item1>A1=9</xtag-item1></LI>
<LI><xtag-item1>A2=17</xtag-item1></LI>
<LI><xtag-item1>A3=18</xtag-item1></LI>
<LI><xtag-item1>A4=22</xtag-item1></LI>
<LI><xtag-item1>A5=21</xtag-item1></LI>
<LI><xtag-item1>A6=22</xtag-item1></LI>
<LI><xtag-item1>AMUX=2</xtag-item1></LI>
<LI><xtag-item1>AQ=20</xtag-item1></LI>
<LI><xtag-item1>AX=1</xtag-item1></LI>
<LI><xtag-item1>AQ=22</xtag-item1></LI>
<LI><xtag-item1>AX=2</xtag-item1></LI>
<LI><xtag-item1>B=11</xtag-item1></LI>
<LI><xtag-item1>B1=7</xtag-item1></LI>
<LI><xtag-item1>B2=15</xtag-item1></LI>
<LI><xtag-item1>B3=16</xtag-item1></LI>
<LI><xtag-item1>B4=20</xtag-item1></LI>
<LI><xtag-item1>B2=16</xtag-item1></LI>
<LI><xtag-item1>B3=17</xtag-item1></LI>
<LI><xtag-item1>B4=21</xtag-item1></LI>
<LI><xtag-item1>B5=21</xtag-item1></LI>
<LI><xtag-item1>B6=22</xtag-item1></LI>
<LI><xtag-item1>BMUX=1</xtag-item1></LI>
@@ -423,15 +423,14 @@
<LI><xtag-item1>CLK=25</xtag-item1></LI>
<LI><xtag-item1>CMUX=3</xtag-item1></LI>
<LI><xtag-item1>CQ=16</xtag-item1></LI>
<LI><xtag-item1>D=11</xtag-item1></LI>
<LI><xtag-item1>D1=7</xtag-item1></LI>
<LI><xtag-item1>D2=17</xtag-item1></LI>
<LI><xtag-item1>D3=20</xtag-item1></LI>
<LI><xtag-item1>D=12</xtag-item1></LI>
<LI><xtag-item1>D1=8</xtag-item1></LI>
<LI><xtag-item1>D2=18</xtag-item1></LI>
<LI><xtag-item1>D3=21</xtag-item1></LI>
<LI><xtag-item1>D4=21</xtag-item1></LI>
<LI><xtag-item1>D5=20</xtag-item1></LI>
<LI><xtag-item1>D6=20</xtag-item1></LI>
<LI><xtag-item1>DQ=11</xtag-item1></LI>
<LI><xtag-item1>DX=1</xtag-item1></LI>
<LI><xtag-item1>D5=21</xtag-item1></LI>
<LI><xtag-item1>D6=21</xtag-item1></LI>
<LI><xtag-item1>DQ=9</xtag-item1></LI>
<LI><xtag-item1>SR=13</xtag-item1></LI>
</UL>
</TD>
@@ -471,6 +470,12 @@
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx16-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
</xtag-section></UL></TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'><xtag-section name="RunStatistics"><TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=8><B>Software Quality</B></TD></TR><TR ALIGN=LEFT><TD COLSPAN=8><B>Run Statistics</B></TD></TR><TR ALIGN=CENTER BGCOLOR='#FFFF99'><TD><B>Program Name</B></TD><TD><B>Runs Started</B></TD><TD><B>Runs Finished</B></TD><TD><B>Errors</B></TD><TD><B>Fatal Errors</B></TD><TD><B>Internal Errors</B></TD><TD><B>Exceptions</B></TD><TD><B>Core Dumps</B></TD></TR>
@@ -487,6 +492,36 @@
</tr>
<tr>
<td><xtag-program-name>bitgen</xtag-program-name></td>
<td><xtag-total-run-started>38</xtag-total-run-started></td>
<td><xtag-total-run-finished>38</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>map</xtag-program-name></td>
<td><xtag-total-run-started>42</xtag-total-run-started></td>
<td><xtag-total-run-finished>37</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>ngdbuild</xtag-program-name></td>
<td><xtag-total-run-started>42</xtag-total-run-started></td>
<td><xtag-total-run-finished>42</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>par</xtag-program-name></td>
<td><xtag-total-run-started>37</xtag-total-run-started></td>
<td><xtag-total-run-finished>37</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
@@ -495,40 +530,10 @@
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>map</xtag-program-name></td>
<td><xtag-total-run-started>41</xtag-total-run-started></td>
<td><xtag-total-run-finished>36</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>ngdbuild</xtag-program-name></td>
<td><xtag-total-run-started>41</xtag-total-run-started></td>
<td><xtag-total-run-finished>41</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>par</xtag-program-name></td>
<td><xtag-total-run-started>36</xtag-total-run-started></td>
<td><xtag-total-run-finished>36</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>trce</xtag-program-name></td>
<td><xtag-total-run-started>36</xtag-total-run-started></td>
<td><xtag-total-run-finished>36</xtag-total-run-finished></td>
<td><xtag-total-run-started>37</xtag-total-run-started></td>
<td><xtag-total-run-finished>37</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@@ -537,8 +542,8 @@
</tr>
<tr>
<td><xtag-program-name>xst</xtag-program-name></td>
<td><xtag-total-run-started>75</xtag-total-run-started></td>
<td><xtag-total-run-finished>75</xtag-total-run-finished></td>
<td><xtag-total-run-started>76</xtag-total-run-started></td>
<td><xtag-total-run-finished>76</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@@ -572,7 +577,7 @@
</TR><TR><TD><xtag-design-property-name>PROP_intProjectCreationTimestamp</xtag-design-property-name>=<xtag-design-property-value>2022-06-08T11:31:57</xtag-design-property-value></TD>
<TD><xtag-design-property-name>PROP_intWbtProjectID</xtag-design-property-name>=<xtag-design-property-value>047E6D81914F4B9E9C732FAABBF95C82</xtag-design-property-value></TD>
</TR><TR><TD><xtag-process-property-name>PROP_intWbtProjectIteration</xtag-process-property-name>=<xtag-process-property-value>4</xtag-process-property-value></TD>
</TR><TR><TD><xtag-process-property-name>PROP_intWbtProjectIteration</xtag-process-property-name>=<xtag-process-property-value>5</xtag-process-property-value></TD>
<TD><xtag-design-property-name>PROP_intWorkingDirLocWRTProjDir</xtag-design-property-name>=<xtag-design-property-value>Same</xtag-design-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_intWorkingDirUsed</xtag-design-property-name>=<xtag-design-property-value>No</xtag-design-property-value></TD>

2
webtalk.log
View File

@@ -4,7 +4,7 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Project Information
--------------------
ProjectID=047E6D81914F4B9E9C732FAABBF95C82
ProjectIteration=4
ProjectIteration=5
WebTalk Summary
----------------

6
webtalk_pn.xml
View File

@@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Wed Jun 08 12:43:04 2022">
<application name="pn" timeStamp="Wed Jun 08 12:52:54 2022">
<section name="Project Information" visible="false">
<property name="ProjectID" value="047E6D81914F4B9E9C732FAABBF95C82" type="project"/>
<property name="ProjectIteration" value="4" type="project"/>
<property name="ProjectIteration" value="5" type="project"/>
<property name="ProjectFile" value="C:/Users/Gabriel/Xilinx/Aula20220608/Aula20220608.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2022-06-08T11:31:57" type="project"/>
</section>
@@ -25,7 +25,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2022-06-08T11:31:57" type="design"/>
<property name="PROP_intWbtProjectID" value="047E6D81914F4B9E9C732FAABBF95C82" type="design"/>
<property name="PROP_intWbtProjectIteration" value="4" type="process"/>
<property name="PROP_intWbtProjectIteration" value="5" type="process"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_AutoTop" value="true" type="design"/>

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xst/work/work.vdbl
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xst/work/work.vdbx
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