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This commit is contained in:
Gabriel Lima
2022-06-08 12:44:36 -03:00
parent 4569cbc5a1
commit 9aa4fc0663
46 changed files with 1529 additions and 1120 deletions
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20
Aula20220608.gise
View File

@@ -52,6 +52,7 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="textovhdl.ut" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="textovhdl.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="textovhdl.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="textovhdl_envsettings.html"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="textovhdl_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="textovhdl_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="textovhdl_map.mrp" xil_pn:subbranch="Map"/>
@@ -101,7 +102,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1654698885" xil_pn:in_ck="-4144913829261074638" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-2610007826355223435" xil_pn:start_ts="1654698875">
<transform xil_pn:end_ts="1654702959" xil_pn:in_ck="-4144913829261074638" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-2610007826355223435" xil_pn:start_ts="1654702949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@@ -123,7 +124,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1654698935" xil_pn:in_ck="6717519187032307095" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7902521214899444903" xil_pn:start_ts="1654698928">
<transform xil_pn:end_ts="1654702973" xil_pn:in_ck="6717519187032307095" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7902521214899444903" xil_pn:start_ts="1654702967">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@@ -133,9 +134,8 @@
<outfile xil_pn:name="textovhdl.ngd"/>
<outfile xil_pn:name="textovhdl_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1654698944" xil_pn:in_ck="6717519187032307096" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-3180699873896808002" xil_pn:start_ts="1654698935">
<transform xil_pn:end_ts="1654702984" xil_pn:in_ck="6717519187032307096" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-3180699873896808002" xil_pn:start_ts="1654702973">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="textovhdl.pcf"/>
@@ -147,7 +147,7 @@
<outfile xil_pn:name="textovhdl_summary.xml"/>
<outfile xil_pn:name="textovhdl_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1654698960" xil_pn:in_ck="-717353726922960719" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1178055513630676559" xil_pn:start_ts="1654698944">
<transform xil_pn:end_ts="1654703000" xil_pn:in_ck="-717353726922960719" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1178055513630676559" xil_pn:start_ts="1654702984">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@@ -162,7 +162,7 @@
<outfile xil_pn:name="textovhdl_pad.txt"/>
<outfile xil_pn:name="textovhdl_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1654698976" xil_pn:in_ck="-4144913829261083515" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1654698964">
<transform xil_pn:end_ts="1654703024" xil_pn:in_ck="-4144913829261083515" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1654703011">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
@@ -174,7 +174,13 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1654698960" xil_pn:in_ck="6717519187032306964" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1654698954">
<transform xil_pn:end_ts="1654701236" xil_pn:in_ck="-4144913829261096369" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="8482462020707587906" xil_pn:start_ts="1654701232">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
</transform>
<transform xil_pn:end_ts="1654703000" xil_pn:in_ck="6717519187032306964" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1654702993">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>

2
_ngo/netlist.lst
View File

@@ -1,2 +1,2 @@
C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.ngc 1654698883
C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.ngc 1654702958
OK

28
_xmsgs/map.xmsgs
View File

@@ -5,10 +5,10 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">BUT&lt;3&gt;_IBUF</arg> has no load.
<msg type="info" file="LIT" num="243" delta="old" >Logical network <arg fmt="%s" index="1">BUT&lt;3&gt;_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="395" delta="new" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">12</arg> more times for the following (max. 5 shown):
<msg type="info" file="LIT" num="395" delta="old" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">11</arg> more times for the following (max. 5 shown):
<arg fmt="%s" index="3">BUT&lt;2&gt;_IBUF,
BUT&lt;1&gt;_IBUF,
BUT&lt;0&gt;_IBUF,
@@ -17,34 +17,22 @@ DIPSW&lt;2&gt;_IBUF</arg>
To see the details of these <arg fmt="%s" index="4">info</arg> messages, please use the -detail switch.
</msg>
<msg type="info" file="MapLib" num="562" delta="new" >No environment variables are currently set.
<msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set.
</msg>
<msg type="warning" file="MapLib" num="701" delta="new" >Signal <arg fmt="%s" index="1">LEDS&lt;3&gt;</arg> connected to top level port <arg fmt="%s" index="2">LEDS&lt;3&gt;</arg> has been removed.
<msg type="info" file="LIT" num="244" delta="old" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
</msg>
<msg type="warning" file="MapLib" num="701" delta="new" >Signal <arg fmt="%s" index="1">LEDS&lt;2&gt;</arg> connected to top level port <arg fmt="%s" index="2">LEDS&lt;2&gt;</arg> has been removed.
<msg type="info" file="Pack" num="1716" delta="old" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)
</msg>
<msg type="warning" file="MapLib" num="701" delta="new" >Signal <arg fmt="%s" index="1">LEDS&lt;1&gt;</arg> connected to top level port <arg fmt="%s" index="2">LEDS&lt;1&gt;</arg> has been removed.
<msg type="info" file="Pack" num="1720" delta="old" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts)
</msg>
<msg type="warning" file="MapLib" num="701" delta="new" >Signal <arg fmt="%s" index="1">LEDS&lt;0&gt;</arg> connected to top level port <arg fmt="%s" index="2">LEDS&lt;0&gt;</arg> has been removed.
<msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp).
</msg>
<msg type="info" file="LIT" num="244" delta="new" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
</msg>
<msg type="info" file="Pack" num="1716" delta="new" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)
</msg>
<msg type="info" file="Pack" num="1720" delta="new" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts)
</msg>
<msg type="info" file="Map" num="215" delta="new" >The Interim Design Summary has been generated in the MAP Report (.mrp).
</msg>
<msg type="info" file="Pack" num="1650" delta="new" >Map created a placed design.
<msg type="info" file="Pack" num="1650" delta="old" >Map created a placed design.
</msg>
</messages>

11
_xmsgs/ngdbuild.xmsgs
View File

@@ -5,19 +5,16 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="NgdBuild" num="470" delta="new" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">GPIO&lt;7&gt;</arg>&apos; has no legal driver
<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">GPIO&lt;7&gt;</arg>&apos; has no legal driver
</msg>
<msg type="warning" file="NgdBuild" num="470" delta="new" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">GPIO&lt;6&gt;</arg>&apos; has no legal driver
<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">GPIO&lt;5&gt;</arg>&apos; has no legal driver
</msg>
<msg type="warning" file="NgdBuild" num="470" delta="new" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">GPIO&lt;5&gt;</arg>&apos; has no legal driver
<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">GPIO&lt;4&gt;</arg>&apos; has no legal driver
</msg>
<msg type="warning" file="NgdBuild" num="470" delta="new" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">GPIO&lt;4&gt;</arg>&apos; has no legal driver
</msg>
<msg type="warning" file="NgdBuild" num="470" delta="new" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">GPIO&lt;3&gt;</arg>&apos; has no legal driver
<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">GPIO&lt;3&gt;</arg>&apos; has no legal driver
</msg>
</messages>

37
_xmsgs/par.xmsgs
View File

@@ -5,58 +5,55 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Par" num="282" delta="new" >No user timing constraints were detected or you have set the option to ignore timing constraints (&quot;par -x&quot;). Place and Route will run in &quot;Performance Evaluation Mode&quot; to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to &quot;std&quot;. For best performance, set the effort level to &quot;high&quot;.
<msg type="info" file="Par" num="282" delta="old" >No user timing constraints were detected or you have set the option to ignore timing constraints (&quot;par -x&quot;). Place and Route will run in &quot;Performance Evaluation Mode&quot; to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to &quot;std&quot;. For best performance, set the effort level to &quot;high&quot;.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">BUT&lt;2&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">GPIO&lt;5&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">BUT&lt;3&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">GPIO&lt;7&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">GPIO&lt;3&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">DIPSW&lt;0&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">GPIO&lt;4&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">DIPSW&lt;1&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">GPIO&lt;5&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">DIPSW&lt;2&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">GPIO&lt;6&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">DIPSW&lt;3&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">GPIO&lt;7&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">BUT&lt;0&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">DIPSW&lt;0&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">BUT&lt;1&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">DIPSW&lt;1&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">BUT&lt;2&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">DIPSW&lt;2&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">BUT&lt;3&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">DIPSW&lt;3&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">GPIO&lt;3&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">BUT&lt;0&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">GPIO&lt;4&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">BUT&lt;1&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
<msg type="info" file="Par" num="459" delta="old" >The Clock Report is not displayed in the non timing-driven mode.
</msg>
<msg type="info" file="Par" num="459" delta="new" >The Clock Report is not displayed in the non timing-driven mode.
</msg>
<msg type="info" file="Timing" num="2761" delta="old" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg>
<msg type="info" file="Timing" num="2761" delta="new" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg>
<msg type="warning" file="ParHelpers" num="361" delta="new" >There are <arg fmt="%d" index="1">13</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
<msg type="warning" file="ParHelpers" num="361" delta="old" >There are <arg fmt="%d" index="1">12</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
</msg>
<msg type="warning" file="Par" num="283" delta="new" >There are <arg fmt="%d" index="1">13</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
<msg type="warning" file="Par" num="283" delta="old" >There are <arg fmt="%d" index="1">12</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
</msg>

8
_xmsgs/trce.xmsgs
View File

@@ -5,13 +5,13 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Timing" num="2698" delta="new" >No timing constraints found, doing default enumeration.</msg>
<msg type="info" file="Timing" num="2698" delta="old" >No timing constraints found, doing default enumeration.</msg>
<msg type="info" file="Timing" num="3412" delta="new" >To improve timing, see the Timing Closure User Guide (UG612).</msg>
<msg type="info" file="Timing" num="3412" delta="old" >To improve timing, see the Timing Closure User Guide (UG612).</msg>
<msg type="info" file="Timing" num="2752" delta="new" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
<msg type="info" file="Timing" num="2752" delta="old" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
<msg type="info" file="Timing" num="3339" delta="new" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
<msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
</messages>

90
_xmsgs/xst.xmsgs
View File

@@ -5,103 +5,127 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 64: Assignment to <arg fmt="%s" index="1">clk100k</arg> ignored, since the identifier is never used
<msg type="warning" file="HDLCompiler" num="946" delta="old" >"C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 44: Actual for formal port <arg fmt="%s" index="1">en</arg> is neither a static name nor a globally static expression
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 65: Assignment to <arg fmt="%s" index="1">clk25k</arg> ignored, since the identifier is never used
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 86: Assignment to <arg fmt="%s" index="1">clk25k</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 66: Assignment to <arg fmt="%s" index="1">clk621ms</arg> ignored, since the identifier is never used
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 87: Assignment to <arg fmt="%s" index="1">clk621ms</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 20: Net &lt;<arg fmt="%s" index="1">num7[3]</arg>&gt; does not have a driver.
<msg type="warning" file="HDLCompiler" num="634" delta="old" >"C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 20: Net &lt;<arg fmt="%s" index="1">num7[3]</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">BUT</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">BUT</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">DIPSW</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DIPSW</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">num7</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd</arg>&quot; line <arg fmt="%s" index="2">48</arg>: Output port &lt;<arg fmt="%s" index="3">ENOUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">UC4</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">num6</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">num7</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">num5</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">num6</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">num4</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">num5</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">num3</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">num4</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">num2</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">num3</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">num1</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">num2</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">num0</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">num1</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="info" file="Xst" num="3218" delta="new" >HDL ADVISOR - The RAM &lt;<arg fmt="%s" index="1">Mram_proxdisplay</arg>&gt; will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">num0</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_6</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">bLeds_1</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_7</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">bLeds_2</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_8</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">bLeds_3</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_9</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="info" file="Xst" num="3218" delta="old" >HDL ADVISOR - The RAM &lt;<arg fmt="%s" index="1">Mram_proxdisplay</arg>&gt; will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_10</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">bLeds_1</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_11</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">bLeds_2</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_12</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">bLeds_3</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_13</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_6</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_14</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_7</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_15</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_8</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_16</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_9</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_17</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_10</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_18</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_11</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_19</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_12</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_20</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_13</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_21</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_14</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_22</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_15</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_23</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_16</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_17</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_18</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_19</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_20</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_21</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_22</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_23</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="info" file="Xst" num="2169" delta="old" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
</msg>
</messages>

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par_usage_statistics.html
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@@ -1,32 +1,32 @@
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>39</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>104</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>104</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>100</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>152</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>544</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>544</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>521</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>4.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>4.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>4.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>5.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>5.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>5.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>5.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>5.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>5.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>5.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>2.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>2.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>9.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>4.1</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>0.6</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>4.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>5.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>5.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>6.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>6.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>6.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>6.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>6.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>6.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>1.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>1.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>3.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>0.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>1.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>1.1</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0050</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0569</xtag-par-property-value></TD></TR>
</xtag-section>
</TABLE>

2
textovhdl.bgn
View File

@@ -5,7 +5,7 @@ C:\Xilinx\14.7\ISE_DS\ISE\.
"textovhdl" is an NCD, version 3.2, device xc6slx16, package csg324, speed -2
Opened constraints file textovhdl.pcf.
Wed Jun 08 11:36:09 2022
Wed Jun 08 12:43:37 2022
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 textovhdl.ncd

BIN
textovhdl.bit
View File

Binary file not shown.

7
textovhdl.bld
View File

@@ -16,7 +16,6 @@ Done...
Checking expanded design ...
WARNING:NgdBuild:470 - bidirect pad net 'GPIO<7>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'GPIO<6>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'GPIO<5>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'GPIO<4>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'GPIO<3>' has no legal driver
@@ -30,12 +29,12 @@ Partition Implementation Status
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 5
Number of warnings: 4
Total memory usage is 161712 kilobytes
Total memory usage is 161520 kilobytes
Writing NGD file "textovhdl.ngd" ...
Total REAL time to NGDBUILD completion: 3 sec
Total REAL time to NGDBUILD completion: 4 sec
Total CPU time to NGDBUILD completion: 3 sec
Writing NGDBUILD log file "textovhdl.bld"...

22
textovhdl.cmd_log
View File

@@ -4,3 +4,25 @@ map -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0 -re
par -w -intstyle ise -ol high -mt off textovhdl_map.ncd textovhdl.ncd textovhdl.pcf
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml textovhdl.twx textovhdl.ncd -o textovhdl.twr textovhdl.pcf -ucf restricoes.ucf
bitgen -intstyle ise -f textovhdl.ut textovhdl.ncd
xst -intstyle ise -ifn "C:/Users/Gabriel/Xilinx/Aula20220608/textovhdl.xst" -ofn "C:/Users/Gabriel/Xilinx/Aula20220608/textovhdl.syr"
xst -intstyle ise -ifn "C:/Users/Gabriel/Xilinx/Aula20220608/textovhdl.xst" -ofn "C:/Users/Gabriel/Xilinx/Aula20220608/textovhdl.syr"
xst -intstyle ise -ifn "C:/Users/Gabriel/Xilinx/Aula20220608/textovhdl.xst" -ofn "C:/Users/Gabriel/Xilinx/Aula20220608/textovhdl.syr"
xst -intstyle ise -ifn "C:/Users/Gabriel/Xilinx/Aula20220608/textovhdl.xst" -ofn "C:/Users/Gabriel/Xilinx/Aula20220608/textovhdl.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc restricoes.ucf -p xc6slx16-csg324-2 textovhdl.ngc textovhdl.ngd
map -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o textovhdl_map.ncd textovhdl.ngd textovhdl.pcf
par -w -intstyle ise -ol high -mt off textovhdl_map.ncd textovhdl.ncd textovhdl.pcf
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml textovhdl.twx textovhdl.ncd -o textovhdl.twr textovhdl.pcf -ucf restricoes.ucf
bitgen -intstyle ise -f textovhdl.ut textovhdl.ncd
xst -intstyle ise -ifn "C:/Users/Gabriel/Xilinx/Aula20220608/textovhdl.xst" -ofn "C:/Users/Gabriel/Xilinx/Aula20220608/textovhdl.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc restricoes.ucf -p xc6slx16-csg324-2 textovhdl.ngc textovhdl.ngd
map -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o textovhdl_map.ncd textovhdl.ngd textovhdl.pcf
par -w -intstyle ise -ol high -mt off textovhdl_map.ncd textovhdl.ncd textovhdl.pcf
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml textovhdl.twx textovhdl.ncd -o textovhdl.twr textovhdl.pcf -ucf restricoes.ucf
bitgen -intstyle ise -f textovhdl.ut textovhdl.ncd
xst -intstyle ise -ifn "C:/Users/Gabriel/Xilinx/Aula20220608/textovhdl.xst" -ofn "C:/Users/Gabriel/Xilinx/Aula20220608/textovhdl.syr"
xst -intstyle ise -ifn "C:/Users/Gabriel/Xilinx/Aula20220608/textovhdl.xst" -ofn "C:/Users/Gabriel/Xilinx/Aula20220608/textovhdl.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc restricoes.ucf -p xc6slx16-csg324-2 textovhdl.ngc textovhdl.ngd
map -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o textovhdl_map.ncd textovhdl.ngd textovhdl.pcf
par -w -intstyle ise -ol high -mt off textovhdl_map.ncd textovhdl.ncd textovhdl.pcf
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml textovhdl.twx textovhdl.ncd -o textovhdl.twr textovhdl.pcf -ucf restricoes.ucf
bitgen -intstyle ise -f textovhdl.ut textovhdl.ncd

2
textovhdl.drc
View File

@@ -1,7 +1,7 @@
Release 14.7 Drc P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Wed Jun 08 11:36:09 2022
Wed Jun 08 12:43:37 2022
drc -z textovhdl.ncd textovhdl.pcf

2
textovhdl.ncd
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File diff suppressed because one or more lines are too long

2
textovhdl.ngc
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File diff suppressed because one or more lines are too long

2
textovhdl.ngd
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File diff suppressed because one or more lines are too long

2
textovhdl.ngr
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File diff suppressed because one or more lines are too long

10
textovhdl.pad
View File

@@ -1,7 +1,7 @@
Release 14.7 - par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Wed Jun 08 11:35:52 2022
Wed Jun 08 12:43:12 2022
# NOTE: This file is designed to be imported into a spreadsheet program
@@ -22,7 +22,7 @@ Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|D
A1|||GND||||||||||||
A2||IOBS|IO_L2N_0|UNUSED||0|||||||||
A3|GPIO<2>|IOB|IO_L4N_0|OUTPUT|LVCMOS25*|0|12|SLOW||||LOCATED|NO|NONE|
A4||IOBS|IO_L5N_0|UNUSED||0|||||||||
A4|LEDS<3>|IOB|IO_L5N_0|OUTPUT|LVCMOS25*|0|12|SLOW||||LOCATED|NO|NONE|
A5||IOBS|IO_L6N_0|UNUSED||0|||||||||
A6||IOBS|IO_L8N_VREF_0|UNUSED||0|||||||||
A7||IOBS|IO_L10N_0|UNUSED||0|||||||||
@@ -58,7 +58,7 @@ B18|||TMS||||||||||||
C1||IOBS|IO_L83N_VREF_3|UNUSED||3|||||||||
C2||IOBM|IO_L83P_3|UNUSED||3|||||||||
C3|||GND||||||||||||
C4||IOBS|IO_L1N_VREF_0|UNUSED||0|||||||||
C4|LEDS<2>|IOB|IO_L1N_VREF_0|OUTPUT|LVCMOS25*|0|12|SLOW||||LOCATED|NO|NONE|
C5||IOBM|IO_L6P_0|UNUSED||0|||||||||
C6||IOBS|IO_L3N_0|UNUSED||0|||||||||
C7||IOBM|IO_L10P_0|UNUSED||0|||||||||
@@ -68,7 +68,7 @@ C10||IOBM|IO_L37P_GCLK13_0|UNUSED||0|||||||||
C11||IOBS|IO_L36N_GCLK14_0|UNUSED||0|||||||||
C12||IOBS|IO_L47N_0|UNUSED||0|||||||||
C13||IOBM|IO_L50P_0|UNUSED||0|||||||||
C14||IOBS|IO_L65N_SCP2_0|UNUSED||0|||||||||
C14|LEDS<1>|IOB|IO_L65N_SCP2_0|OUTPUT|LVCMOS25*|0|12|SLOW||||LOCATED|NO|NONE|
C15||IOBM|IO_L64P_SCP5_0|UNUSED||0|||||||||
C16|||GND||||||||||||
C17||IOBM|IO_L29P_A23_M1A13_1|UNUSED||1|||||||||
@@ -103,7 +103,7 @@ E9|||VCCAUX||||||||2.5||||
E10|||VCCO_0|||0|||||2.50||||
E11||IOBS|IO_L42N_0|UNUSED||0|||||||||
E12|DIPSW<1>|IOB|IO_L51N_0|INPUT|LVCMOS25*|0||||NONE||LOCATED|NO|NONE|
E13||IOBS|IO_L63N_SCP6_0|UNUSED||0|||||||||
E13|LEDS<0>|IOB|IO_L63N_SCP6_0|OUTPUT|LVCMOS25*|0|12|SLOW||||LOCATED|NO|NONE|
E14|||VCCAUX||||||||2.5||||
E15|||GND||||||||||||
E16||IOBM|IO_L33P_A15_M1A10_1|UNUSED||1|||||||||

87
textovhdl.par
View File

@@ -1,7 +1,7 @@
Release 14.7 par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
GABRIEL-E5400:: Wed Jun 08 11:35:46 2022
GABRIEL-E5400:: Wed Jun 08 12:43:05 2022
par -w -intstyle ise -ol high -mt off textovhdl_map.ncd textovhdl.ncd
textovhdl.pcf
@@ -27,16 +27,16 @@ Device speed data version: "PRODUCTION 1.23 2013-10-13".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 32 out of 18,224 1%
Number used as Flip Flops: 32
Number of Slice Registers: 81 out of 18,224 1%
Number used as Flip Flops: 81
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 31 out of 9,112 1%
Number used as logic: 29 out of 9,112 1%
Number using O6 output only: 14
Number using O5 output only: 11
Number using O5 and O6: 4
Number of Slice LUTs: 129 out of 9,112 1%
Number used as logic: 127 out of 9,112 1%
Number using O6 output only: 85
Number using O5 output only: 12
Number using O5 and O6: 30
Number used as ROM: 0
Number used as Memory: 0 out of 2,176 0%
Number used exclusively as route-thrus: 2
@@ -45,12 +45,12 @@ Slice Logic Utilization:
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 11 out of 2,278 1%
Number of MUXCYs used: 20 out of 4,556 1%
Number of LUT Flip Flop pairs used: 31
Number with an unused Flip Flop: 1 out of 31 3%
Number with an unused LUT: 0 out of 31 0%
Number of fully used LUT-FF pairs: 30 out of 31 96%
Number of occupied Slices: 41 out of 2,278 1%
Number of MUXCYs used: 44 out of 4,556 1%
Number of LUT Flip Flop pairs used: 132
Number with an unused Flip Flop: 56 out of 132 42%
Number with an unused LUT: 3 out of 132 2%
Number of fully used LUT-FF pairs: 73 out of 132 55%
Number of slice register sites lost
to control set restrictions: 0 out of 18,224 0%
@@ -61,16 +61,16 @@ Slice Logic Distribution:
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 17 out of 232 7%
Number of LOCed IOBs: 17 out of 17 100%
Number of bonded IOBs: 21 out of 232 9%
Number of LOCed IOBs: 21 out of 21 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 32 0%
Number of RAMB8BWERs: 0 out of 64 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 2 out of 16 12%
Number used as BUFGs: 2
Number of BUFG/BUFGMUXs: 3 out of 16 18%
Number used as BUFGs: 3
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 0 out of 248 0%
@@ -96,12 +96,7 @@ Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 4 secs
Finished initial Timing Analysis. REAL time: 4 secs
WARNING:Par:288 - The signal BUT<2>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal BUT<3>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO<3>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO<4>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO<5>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO<6>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO<7>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DIPSW<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DIPSW<1>_IBUF has no load. PAR will not attempt to route this signal.
@@ -109,32 +104,36 @@ WARNING:Par:288 - The signal DIPSW<2>_IBUF has no load. PAR will not attempt to
WARNING:Par:288 - The signal DIPSW<3>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal BUT<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal BUT<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal BUT<2>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal BUT<3>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO<3>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO<4>_IBUF has no load. PAR will not attempt to route this signal.
Starting Router
Phase 1 : 119 unrouted; REAL time: 4 secs
Phase 1 : 586 unrouted; REAL time: 4 secs
Phase 2 : 93 unrouted; REAL time: 4 secs
Phase 2 : 514 unrouted; REAL time: 4 secs
Phase 3 : 4 unrouted; REAL time: 4 secs
Phase 3 : 55 unrouted; REAL time: 5 secs
Phase 4 : 4 unrouted; (Par is working to improve performance) REAL time: 5 secs
Phase 4 : 55 unrouted; (Par is working to improve performance) REAL time: 5 secs
Updating file: textovhdl.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 5 secs
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 6 secs
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 5 secs
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 6 secs
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 5 secs
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 6 secs
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 5 secs
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 6 secs
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 5 secs
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 6 secs
Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 5 secs
Total REAL time to Router completion: 5 secs
Total CPU time to Router completion: 5 secs
Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 6 secs
Total REAL time to Router completion: 6 secs
Total CPU time to Router completion: 6 secs
Partition Implementation Status
-------------------------------
@@ -154,12 +153,18 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net con | SETUP | N/A| 1.993ns| N/A| 0
taux_5_BUFG | HOLD | 0.463ns| | 0| 0
Autotimespec constraint for clock net tog | SETUP | N/A| 1.051ns| N/A| 0
gleled | HOLD | 0.454ns| | 0| 0
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net CLK | SETUP | N/A| 1.805ns| N/A| 0
Autotimespec constraint for clock net CLK | SETUP | N/A| 3.484ns| N/A| 0
27MHz_BUFGP | HOLD | 0.530ns| | 0| 0
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net con | SETUP | N/A| 3.450ns| N/A| 0
t100k_8_BUFG | HOLD | 0.402ns| | 0| 0
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net con | SETUP | N/A| 2.554ns| N/A| 0
taux_5_BUFG | HOLD | 0.434ns| | 0| 0
----------------------------------------------------------------------------------------------------------
All constraints were met.
@@ -174,18 +179,18 @@ Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 13 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
WARNING:Par:283 - There are 12 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 6 secs
Total CPU time to PAR completion: 6 secs
Peak Memory Usage: 305 MB
Peak Memory Usage: 309 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 15
Number of warning messages: 14
Number of info messages: 2
Writing design to file textovhdl.ncd

30
textovhdl.pcf
View File

@@ -1,8 +1,24 @@
//! **************************************************************************
// Written by: Map P.20131013 on Wed Jun 08 11:35:43 2022
// Written by: Map P.20131013 on Wed Jun 08 12:43:02 2022
//! **************************************************************************
SCHEMATIC START;
COMP "GPIO<5>" LOCATE = SITE "B4" LEVEL 1;
COMP "GPIO<6>" LOCATE = SITE "F13" LEVEL 1;
PIN GPIO<6>_pin<0> = BEL "GPIO<6>" PINNAME PAD;
PIN "GPIO<6>_pin<0>" CLOCK_DEDICATED_ROUTE = FALSE;
COMP "GPIO<7>" LOCATE = SITE "P12" LEVEL 1;
COMP "LEDS<0>" LOCATE = SITE "E13" LEVEL 1;
COMP "LEDS<1>" LOCATE = SITE "C14" LEVEL 1;
COMP "LEDS<2>" LOCATE = SITE "C4" LEVEL 1;
COMP "LEDS<3>" LOCATE = SITE "A4" LEVEL 1;
COMP "DIPSW<0>" LOCATE = SITE "D14" LEVEL 1;
COMP "DIPSW<1>" LOCATE = SITE "E12" LEVEL 1;
COMP "CLK27MHz" LOCATE = SITE "V10" LEVEL 1;
COMP "DIPSW<2>" LOCATE = SITE "F12" LEVEL 1;
COMP "DIPSW<3>" LOCATE = SITE "V13" LEVEL 1;
COMP "BUT<0>" LOCATE = SITE "P4" LEVEL 1;
COMP "BUT<1>" LOCATE = SITE "F6" LEVEL 1;
COMP "BUT<2>" LOCATE = SITE "E4" LEVEL 1;
COMP "BUT<3>" LOCATE = SITE "F5" LEVEL 1;
COMP "GPIO<0>" LOCATE = SITE "N17" LEVEL 1;
@@ -12,17 +28,5 @@ COMP "GPIO<3>" LOCATE = SITE "L15" LEVEL 1;
COMP "GPIO<4>" LOCATE = SITE "F15" LEVEL 1;
PIN GPIO<4>_pin<0> = BEL "GPIO<4>" PINNAME PAD;
PIN "GPIO<4>_pin<0>" CLOCK_DEDICATED_ROUTE = FALSE;
COMP "GPIO<5>" LOCATE = SITE "B4" LEVEL 1;
COMP "GPIO<6>" LOCATE = SITE "F13" LEVEL 1;
PIN GPIO<6>_pin<0> = BEL "GPIO<6>" PINNAME PAD;
PIN "GPIO<6>_pin<0>" CLOCK_DEDICATED_ROUTE = FALSE;
COMP "GPIO<7>" LOCATE = SITE "P12" LEVEL 1;
COMP "DIPSW<0>" LOCATE = SITE "D14" LEVEL 1;
COMP "DIPSW<1>" LOCATE = SITE "E12" LEVEL 1;
COMP "CLK27MHz" LOCATE = SITE "V10" LEVEL 1;
COMP "DIPSW<2>" LOCATE = SITE "F12" LEVEL 1;
COMP "DIPSW<3>" LOCATE = SITE "V13" LEVEL 1;
COMP "BUT<0>" LOCATE = SITE "P4" LEVEL 1;
COMP "BUT<1>" LOCATE = SITE "F6" LEVEL 1;
SCHEMATIC END;

2
textovhdl.ptwx
View File

@@ -329,4 +329,4 @@
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net contaux_5_BUFG</twConstName><twConstData type="SETUP" best="1.993" units="ns" score="0"/><twConstData type="HOLD" slack="0.463" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net CLK27MHz_BUFGP</twConstName><twConstData type="SETUP" best="1.805" units="ns" score="0"/><twConstData type="HOLD" slack="0.530" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="6">0</twUnmetConstCnt><twInfo anchorID="7">INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</twInfo></twSumRpt></twBody></twReport>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net toggleled</twConstName><twConstData type="SETUP" best="1.051" units="ns" score="0"/><twConstData type="HOLD" slack="0.454" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net CLK27MHz_BUFGP</twConstName><twConstData type="SETUP" best="3.484" units="ns" score="0"/><twConstData type="HOLD" slack="0.530" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net cont100k_8_BUFG</twConstName><twConstData type="SETUP" best="3.450" units="ns" score="0"/><twConstData type="HOLD" slack="0.402" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net contaux_5_BUFG</twConstName><twConstData type="SETUP" best="2.554" units="ns" score="0"/><twConstData type="HOLD" slack="0.434" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="10">0</twUnmetConstCnt><twInfo anchorID="11">INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</twInfo></twSumRpt></twBody></twReport>

378
textovhdl.syr
View File

@@ -4,13 +4,13 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.13 secs
Total CPU time to Xst completion: 0.11 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.13 secs
Total CPU time to Xst completion: 0.11 secs
--> Reading design: textovhdl.prj
@@ -108,6 +108,7 @@ Slice Utilization Ratio Delta : 5
Parsing VHDL file "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" into library work
Parsing entity <textovhdl>.
Parsing architecture <comportamento> of entity <textovhdl>.
WARNING:HDLCompiler:946 - "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 44: Actual for formal port en is neither a static name nor a globally static expression
Parsing entity <CONTBCD_C>.
Parsing architecture <comportamento> of entity <contbcd_c>.
Parsing entity <display>.
@@ -119,10 +120,11 @@ Parsing architecture <comportamento> of entity <display>.
Elaborating entity <textovhdl> (architecture <comportamento>) from library <work>.
Elaborating entity <CONTBCD_C> (architecture <comportamento>) from library <work>.
Elaborating entity <display> (architecture <comportamento>) from library <work>.
WARNING:HDLCompiler:1127 - "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 64: Assignment to clk100k ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 65: Assignment to clk25k ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 66: Assignment to clk621ms ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 86: Assignment to clk25k ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 87: Assignment to clk621ms ignored, since the identifier is never used
WARNING:HDLCompiler:634 - "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 20: Net <num7[3]> does not have a driver.
=========================================================================
@@ -133,6 +135,7 @@ Synthesizing Unit <textovhdl>.
Related source file is "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd".
WARNING:Xst:647 - Input <BUT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DIPSW> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" line 48: Output port <ENOUT> of the instance <UC4> is unconnected or connected to loadless signal.
Always blocking tristate driving signal <GPIO<7>> is removed.
Always blocking tristate driving signal <GPIO<6>> is removed.
Always blocking tristate driving signal <GPIO<5>> is removed.
@@ -149,24 +152,34 @@ WARNING:Xst:653 - Signal <num3> is used but never assigned. This sourceless sign
WARNING:Xst:653 - Signal <num2> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <num1> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <num0> is used but never assigned. This sourceless signal will be automatically connected to value GND.
Found 1-bit register for signal <toggleled>.
Found 4-bit register for signal <bLeds>.
Found 24-bit register for signal <cont100k>.
Found 24-bit register for signal <contaux>.
Found 24-bit adder for signal <contaux[23]_GND_5_o_add_5_OUT> created at line 60.
Found 1-bit tristate buffer for signal <LEDS<3>> created at line 37
Found 1-bit tristate buffer for signal <LEDS<2>> created at line 37
Found 1-bit tristate buffer for signal <LEDS<1>> created at line 37
Found 1-bit tristate buffer for signal <LEDS<0>> created at line 37
Found 2-bit register for signal <ffmicro<19:18>>.
Found 24-bit adder for signal <contaux[23]_GND_5_o_add_9_OUT> created at line 81.
Found 24-bit subtractor for signal <GND_5_o_GND_5_o_sub_8_OUT<23:0>> created at line 79.
Summary:
inferred 2 Adder/Subtractor(s).
inferred 55 D-type flip-flop(s).
Unit <textovhdl> synthesized.
Synthesizing Unit <CONTBCD_C>.
Related source file is "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd".
Found 4-bit register for signal <cont>.
Found 4-bit adder for signal <cont[3]_UP_add_3_OUT> created at line 126.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 24 D-type flip-flop(s).
inferred 4 Tristate(s).
Unit <textovhdl> synthesized.
inferred 4 D-type flip-flop(s).
inferred 3 Multiplexer(s).
Unit <CONTBCD_C> synthesized.
Synthesizing Unit <display>.
Related source file is "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd".
Found 1-bit register for signal <configur>.
Found 16-bit register for signal <palavra>.
Found 9-bit register for signal <EN>.
Found 9-bit adder for signal <EN[8]_GND_18_o_add_37_OUT> created at line 179.
Found 9-bit adder for signal <EN[8]_GND_19_o_add_37_OUT> created at line 205.
Found 8x4-bit Read Only RAM for signal <proxdisplay>
Summary:
inferred 1 RAM(s).
@@ -181,18 +194,22 @@ HDL Synthesis Report
Macro Statistics
# RAMs : 1
8x4-bit single-port Read Only RAM : 1
# Adders/Subtractors : 2
# Adders/Subtractors : 8
24-bit adder : 1
24-bit subtractor : 1
4-bit adder : 5
9-bit adder : 1
# Registers : 4
1-bit register : 1
# Registers : 13
1-bit register : 2
16-bit register : 1
24-bit register : 1
2-bit register : 1
24-bit register : 2
4-bit register : 6
9-bit register : 1
# Multiplexers : 4
# Multiplexers : 19
1-bit 2-to-1 multiplexer : 5
16-bit 2-to-1 multiplexer : 4
# Tristates : 4
1-bit tristate buffer : 4
4-bit 2-to-1 multiplexer : 10
=========================================================================
@@ -200,6 +217,9 @@ Macro Statistics
* Advanced HDL Synthesis *
=========================================================================
WARNING:Xst:2677 - Node <bLeds_1> of sequential type is unconnected in block <textovhdl>.
WARNING:Xst:2677 - Node <bLeds_2> of sequential type is unconnected in block <textovhdl>.
WARNING:Xst:2677 - Node <bLeds_3> of sequential type is unconnected in block <textovhdl>.
Synthesizing (advanced) Unit <display>.
The following registers are absorbed into counter <EN>: 1 register on signal <EN>.
@@ -217,8 +237,12 @@ INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_proxdisplay> will be implemented on
Unit <display> synthesized (advanced).
Synthesizing (advanced) Unit <textovhdl>.
The following registers are absorbed into counter <cont100k>: 1 register on signal <cont100k>.
The following registers are absorbed into counter <contaux>: 1 register on signal <contaux>.
Unit <textovhdl> synthesized (advanced).
WARNING:Xst:2677 - Node <bLeds_1> of sequential type is unconnected in block <textovhdl>.
WARNING:Xst:2677 - Node <bLeds_2> of sequential type is unconnected in block <textovhdl>.
WARNING:Xst:2677 - Node <bLeds_3> of sequential type is unconnected in block <textovhdl>.
=========================================================================
Advanced HDL Synthesis Report
@@ -226,13 +250,18 @@ Advanced HDL Synthesis Report
Macro Statistics
# RAMs : 1
8x4-bit single-port distributed Read Only RAM : 1
# Counters : 2
# Adders/Subtractors : 5
4-bit adder : 5
# Counters : 3
24-bit down counter : 1
24-bit up counter : 1
9-bit up counter : 1
# Registers : 17
Flip-Flops : 17
# Multiplexers : 4
# Registers : 41
Flip-Flops : 41
# Multiplexers : 19
1-bit 2-to-1 multiplexer : 5
16-bit 2-to-1 multiplexer : 4
4-bit 2-to-1 multiplexer : 10
=========================================================================
@@ -260,11 +289,14 @@ WARNING:Xst:2677 - Node <contaux_23> of sequential type is unconnected in block
Optimizing unit <textovhdl> ...
Optimizing unit <CONTBCD_C> ...
Optimizing unit <display> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block textovhdl, actual ratio is 0.
Found area constraint ratio of 100 (+ 5) on block textovhdl, actual ratio is 1.
FlipFlop cont100k_8 has been replicated 1 time(s)
Final Macro Processing ...
@@ -272,8 +304,8 @@ Final Macro Processing ...
Final Register Report
Macro Statistics
# Registers : 32
Flip-Flops : 32
# Registers : 81
Flip-Flops : 81
=========================================================================
@@ -296,27 +328,29 @@ Top Level Output File Name : textovhdl.ngc
Primitive and Black Box Usage:
------------------------------
# BELS : 64
# BELS : 213
# GND : 1
# INV : 4
# LUT1 : 13
# LUT2 : 5
# LUT3 : 1
# LUT4 : 1
# LUT5 : 5
# LUT6 : 5
# MUXCY : 13
# INV : 31
# LUT1 : 14
# LUT2 : 7
# LUT3 : 9
# LUT4 : 4
# LUT5 : 43
# LUT6 : 28
# MUXCY : 36
# VCC : 1
# XORCY : 15
# FlipFlops/Latches : 32
# FD : 15
# FD_1 : 17
# Clock Buffers : 2
# BUFG : 1
# XORCY : 39
# FlipFlops/Latches : 81
# FD : 44
# FD_1 : 4
# FDCE : 20
# FDR_1 : 13
# Clock Buffers : 3
# BUFG : 2
# BUFGP : 1
# IO Buffers : 7
# OBUF : 3
# OBUFT : 4
# IO Buffers : 8
# IBUF : 1
# OBUF : 7
Device utilization summary:
---------------------------
@@ -325,23 +359,23 @@ Selected Device : 6slx16csg324-2
Slice Logic Utilization:
Number of Slice Registers: 32 out of 18224 0%
Number of Slice LUTs: 34 out of 9112 0%
Number used as Logic: 34 out of 9112 0%
Number of Slice Registers: 81 out of 18224 0%
Number of Slice LUTs: 136 out of 9112 1%
Number used as Logic: 136 out of 9112 1%
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 34
Number with an unused Flip Flop: 2 out of 34 5%
Number with an unused LUT: 0 out of 34 0%
Number of fully used LUT-FF pairs: 32 out of 34 94%
Number of unique control sets: 3
Number of LUT Flip Flop pairs used: 138
Number with an unused Flip Flop: 57 out of 138 41%
Number with an unused LUT: 2 out of 138 1%
Number of fully used LUT-FF pairs: 79 out of 138 57%
Number of unique control sets: 9
IO Utilization:
Number of IOs: 21
Number of bonded IOBs: 8 out of 232 3%
Number of bonded IOBs: 9 out of 232 3%
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: 2 out of 16 12%
Number of BUFG/BUFGCTRLs: 3 out of 16 18%
---------------------------
Partition Resource Summary:
@@ -364,9 +398,12 @@ Clock Information:
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
CLK27MHz | BUFGP | 6 |
cont100k_8 | BUFG | 23 |
toggleled | NONE(bLeds_0) | 1 |
CLK27MHz | BUFGP | 31 |
contaux_5 | BUFG | 26 |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
Asynchronous Control Signals Information:
----------------------------------------
@@ -376,75 +413,170 @@ Timing Summary:
---------------
Speed Grade: -2
Minimum period: 2.579ns (Maximum Frequency: 387.785MHz)
Minimum input arrival time before clock: No path found
Maximum output required time after clock: 5.607ns
Maximum combinational path delay: No path found
Minimum period: 4.284ns (Maximum Frequency: 233.427MHz)
Minimum input arrival time before clock: 3.096ns
Maximum output required time after clock: 7.122ns
Maximum combinational path delay: 5.549ns
Timing Details:
---------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'CLK27MHz'
Clock period: 2.049ns (frequency: 488.043MHz)
Total number of paths / destination ports: 21 / 6
Timing constraint: Default period analysis for Clock 'cont100k_8'
Clock period: 4.284ns (frequency: 233.427MHz)
Total number of paths / destination ports: 327 / 43
-------------------------------------------------------------------------
Delay: 2.049ns (Levels of Logic = 7)
Source: contaux_0 (FF)
Destination: contaux_5 (FF)
Delay: 4.284ns (Levels of Logic = 3)
Source: UC2/cont_0 (FF)
Destination: UC3/cont_3 (FF)
Source Clock: cont100k_8 rising
Destination Clock: cont100k_8 rising
Data Path: UC2/cont_0 to UC3/cont_3
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 9 0.525 1.252 UC2/cont_0 (UC2/cont_0)
LUT4:I0->O 5 0.254 0.841 UC1/Mmux_ENOUT11_SW0 (N10)
LUT5:I4->O 2 0.254 0.834 UC2/Mmux_ENOUT11_rstpot (UC2/Mmux_ENOUT11_rstpot)
LUT3:I1->O 1 0.250 0.000 UC3/cont_1_dpot (UC3/cont_1_dpot)
FDCE:D 0.074 UC3/cont_1
----------------------------------------
Total 4.284ns (1.357ns logic, 2.927ns route)
(31.7% logic, 68.3% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'toggleled'
Clock period: 2.260ns (frequency: 442.478MHz)
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay: 2.260ns (Levels of Logic = 1)
Source: bLeds_0 (FF)
Destination: bLeds_0 (FF)
Source Clock: toggleled rising
Destination Clock: toggleled rising
Data Path: bLeds_0 to bLeds_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 2 0.525 0.725 bLeds_0 (bLeds_0)
INV:I->O 1 0.255 0.681 bLeds[3]_inv_4_OUT<0>1_INV_0 (bLeds[3]_inv_4_OUT<0>)
FD:D 0.074 bLeds_0
----------------------------------------
Total 2.260ns (0.854ns logic, 1.406ns route)
(37.8% logic, 62.2% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'CLK27MHz'
Clock period: 3.944ns (frequency: 253.550MHz)
Total number of paths / destination ports: 930 / 31
-------------------------------------------------------------------------
Delay: 3.944ns (Levels of Logic = 2)
Source: cont100k_1 (FF)
Destination: cont100k_0 (FF)
Source Clock: CLK27MHz rising
Destination Clock: CLK27MHz rising
Data Path: contaux_0 to contaux_5
Data Path: cont100k_1 to cont100k_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 1 0.525 0.681 contaux_0 (contaux_0)
INV:I->O 1 0.255 0.000 Mcount_contaux_lut<0>_INV_0 (Mcount_contaux_lut<0>)
MUXCY:S->O 1 0.215 0.000 Mcount_contaux_cy<0> (Mcount_contaux_cy<0>)
MUXCY:CI->O 1 0.023 0.000 Mcount_contaux_cy<1> (Mcount_contaux_cy<1>)
MUXCY:CI->O 1 0.023 0.000 Mcount_contaux_cy<2> (Mcount_contaux_cy<2>)
MUXCY:CI->O 1 0.023 0.000 Mcount_contaux_cy<3> (Mcount_contaux_cy<3>)
MUXCY:CI->O 0 0.023 0.000 Mcount_contaux_cy<4> (Mcount_contaux_cy<4>)
XORCY:CI->O 1 0.206 0.000 Mcount_contaux_xor<5> (Result<5>)
FD:D 0.074 contaux_5
FD:C->Q 2 0.525 1.181 cont100k_1 (cont100k_1)
LUT6:I0->O 24 0.254 1.656 cont100k[23]_GND_5_o_equal_7_o<23>3 (cont100k[23]_GND_5_o_equal_7_o<23>2)
LUT5:I1->O 1 0.254 0.000 cont100k_0_rstpot (cont100k_0_rstpot)
FD:D 0.074 cont100k_0
----------------------------------------
Total 2.049ns (1.368ns logic, 0.681ns route)
(66.8% logic, 33.2% route)
Total 3.944ns (1.107ns logic, 2.837ns route)
(28.1% logic, 71.9% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'contaux_5'
Clock period: 2.579ns (frequency: 387.785MHz)
Total number of paths / destination ports: 117 / 26
Clock period: 3.741ns (frequency: 267.308MHz)
Total number of paths / destination ports: 183 / 39
-------------------------------------------------------------------------
Delay: 2.579ns (Levels of Logic = 6)
Source: UDISP/EN_4 (FF)
Destination: UDISP/EN_8 (FF)
Delay: 3.741ns (Levels of Logic = 1)
Source: UDISP/EN_6 (FF)
Destination: UDISP/palavra_15 (FF)
Source Clock: contaux_5 falling
Destination Clock: contaux_5 falling
Data Path: UDISP/EN_4 to UDISP/EN_8
Data Path: UDISP/EN_6 to UDISP/palavra_15
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 18 0.525 1.235 UDISP/EN_4 (UDISP/EN_4)
LUT1:I0->O 1 0.254 0.000 UDISP/Mcount_EN_cy<4>_rt (UDISP/Mcount_EN_cy<4>_rt)
MUXCY:S->O 1 0.215 0.000 UDISP/Mcount_EN_cy<4> (UDISP/Mcount_EN_cy<4>)
MUXCY:CI->O 1 0.023 0.000 UDISP/Mcount_EN_cy<5> (UDISP/Mcount_EN_cy<5>)
MUXCY:CI->O 1 0.023 0.000 UDISP/Mcount_EN_cy<6> (UDISP/Mcount_EN_cy<6>)
MUXCY:CI->O 0 0.023 0.000 UDISP/Mcount_EN_cy<7> (UDISP/Mcount_EN_cy<7>)
XORCY:CI->O 1 0.206 0.000 UDISP/Mcount_EN_xor<8> (UDISP/Result<8>)
FD:D 0.074 UDISP/EN_8
FD:C->Q 9 0.525 1.406 UDISP/EN_6 (UDISP/EN_6)
LUT5:I0->O 13 0.254 1.097 UDISP/_n01261 (UDISP/_n0126)
FDR_1:R 0.459 UDISP/palavra_1
----------------------------------------
Total 2.579ns (1.344ns logic, 1.235ns route)
(52.1% logic, 47.9% route)
Total 3.741ns (1.238ns logic, 2.503ns route)
(33.1% logic, 66.9% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'cont100k_8'
Total number of paths / destination ports: 20 / 20
-------------------------------------------------------------------------
Offset: 3.096ns (Levels of Logic = 1)
Source: GPIO<6> (PAD)
Destination: UC4/cont_3 (FF)
Destination Clock: cont100k_8 rising
Data Path: GPIO<6> to UC4/cont_3
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 21 1.328 1.309 GPIO_6_IBUF (LEDS_3_OBUF)
FDCE:CLR 0.459 UC4/cont_0
----------------------------------------
Total 3.096ns (1.787ns logic, 1.309ns route)
(57.7% logic, 42.3% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'cont100k_8'
Total number of paths / destination ports: 21 / 2
-------------------------------------------------------------------------
Offset: 7.122ns (Levels of Logic = 3)
Source: UC0/cont_2 (FF)
Destination: LEDS<1> (PAD)
Source Clock: cont100k_8 rising
Data Path: UC0/cont_2 to LEDS<1>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 7 0.525 1.340 UC0/cont_2 (UC0/cont_2)
LUT6:I1->O 2 0.254 1.156 andcontzero1 (andcontzero)
LUT5:I0->O 1 0.254 0.681 andcontzero4 (LEDS_1_OBUF)
OBUF:I->O 2.912 LEDS_1_OBUF (LEDS<1>)
----------------------------------------
Total 7.122ns (3.945ns logic, 3.177ns route)
(55.4% logic, 44.6% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'toggleled'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 4.162ns (Levels of Logic = 1)
Source: bLeds_0 (FF)
Destination: LEDS<0> (PAD)
Source Clock: toggleled rising
Data Path: bLeds_0 to LEDS<0>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 2 0.525 0.725 bLeds_0 (bLeds_0)
OBUF:I->O 2.912 LEDS_0_OBUF (LEDS<0>)
----------------------------------------
Total 4.162ns (3.437ns logic, 0.725ns route)
(82.6% logic, 17.4% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'contaux_5'
Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset: 5.607ns (Levels of Logic = 2)
Offset: 5.633ns (Levels of Logic = 2)
Source: UDISP/EN_4 (FF)
Destination: GPIO<1> (PAD)
Source Clock: contaux_5 falling
@@ -453,12 +585,12 @@ Offset: 5.607ns (Levels of Logic = 2)
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 18 0.525 1.234 UDISP/EN_4 (UDISP/EN_4)
FD:C->Q 19 0.525 1.260 UDISP/EN_4 (UDISP/EN_4)
INV:I->O 1 0.255 0.681 UDISP/CS1_INV_0 (GPIO_1_OBUF)
OBUF:I->O 2.912 GPIO_1_OBUF (GPIO<1>)
----------------------------------------
Total 5.607ns (3.692ns logic, 1.915ns route)
(65.8% logic, 34.2% route)
Total 5.633ns (3.692ns logic, 1.941ns route)
(65.5% logic, 34.5% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK27MHz'
@@ -479,6 +611,24 @@ Offset: 4.162ns (Levels of Logic = 1)
Total 4.162ns (3.437ns logic, 0.725ns route)
(82.6% logic, 17.4% route)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay: 5.549ns (Levels of Logic = 2)
Source: GPIO<6> (PAD)
Destination: LEDS<3> (PAD)
Data Path: GPIO<6> to LEDS<3>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 21 1.328 1.309 GPIO_6_IBUF (LEDS_3_OBUF)
OBUF:I->O 2.912 LEDS_3_OBUF (LEDS<3>)
----------------------------------------
Total 5.549ns (4.240ns logic, 1.309ns route)
(76.4% logic, 23.6% route)
=========================================================================
Cross Clock Domains Report:
@@ -489,7 +639,15 @@ Clock to Setup on destination clock CLK27MHz
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK27MHz | 2.049| | | |
CLK27MHz | 3.944| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock cont100k_8
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
cont100k_8 | 4.284| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock contaux_5
@@ -497,20 +655,28 @@ Clock to Setup on destination clock contaux_5
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
contaux_5 | | | 2.579| |
contaux_5 | | | 3.741| |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock toggleled
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
toggleled | 2.260| | | |
---------------+---------+---------+---------+---------+
=========================================================================
Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 6.79 secs
Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 7.06 secs
-->
Total memory usage is 258824 kilobytes
Total memory usage is 259080 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 32 ( 0 filtered)
Number of infos : 1 ( 0 filtered)
Number of warnings : 38 ( 0 filtered)
Number of infos : 3 ( 0 filtered)

15
textovhdl.twr
View File

@@ -37,7 +37,7 @@ Clock CLK27MHz to Pad
|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
------------+-----------------+------------+-----------------+------------+------------------+--------+
GPIO<0> | 9.967(R)| SLOW | 4.260(R)| FAST |CLK27MHz_BUFGP | 0.000|
GPIO<0> | 9.718(R)| SLOW | 4.138(R)| FAST |CLK27MHz_BUFGP | 0.000|
------------+-----------------+------------+-----------------+------------+------------------+--------+
Clock to Setup on destination clock CLK27MHz
@@ -45,18 +45,25 @@ Clock to Setup on destination clock CLK27MHz
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK27MHz | 1.805| | | |
CLK27MHz | 3.484| | | |
---------------+---------+---------+---------+---------+
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
GPIO<6> |LEDS<3> | 9.673|
---------------+---------------+---------+
Analysis completed Wed Jun 08 11:35:59 2022
Analysis completed Wed Jun 08 12:43:19 2022
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 218 MB
Peak Memory Usage: 219 MB

4
textovhdl.twx
View File

@@ -333,7 +333,7 @@
-n 3 -fastpaths -xml textovhdl.twx textovhdl.ncd -o textovhdl.twr textovhdl.pcf
-ucf restricoes.ucf
</twCmdLine><twDesign>textovhdl.ncd</twDesign><twDesignPath>textovhdl.ncd</twDesignPath><twPCF>textovhdl.pcf</twPCF><twPcfPath>textovhdl.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="csg324"><twDevName>xc6slx16</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-2</twSpeedGrade><twSpeedVer>PRODUCTION 1.23 2013-10-13</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:2698 - No timing constraints found, doing default enumeration.</twInfo><twInfo anchorID="3">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="4">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="5">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twDataSheet anchorID="6" twNameLen="15"><twClk2OutList anchorID="7" twDestWidth="7" twPhaseWidth="14"><twSrc>CLK27MHz</twSrc><twClk2Out twOutPad = "GPIO&lt;0&gt;" twMinTime = "4.260" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "9.967" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK27MHz_BUFGP" twClkPhase="0.000" ></twClk2Out></twClk2OutList><twClk2SUList anchorID="8" twDestWidth="8"><twDest>CLK27MHz</twDest><twClk2SU><twSrc>CLK27MHz</twSrc><twRiseRise>1.805</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twFoot><twTimestamp>Wed Jun 08 11:35:59 2022 </twTimestamp></twFoot><twClientInfo anchorID="9"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
</twCmdLine><twDesign>textovhdl.ncd</twDesign><twDesignPath>textovhdl.ncd</twDesignPath><twPCF>textovhdl.pcf</twPCF><twPcfPath>textovhdl.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="csg324"><twDevName>xc6slx16</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-2</twSpeedGrade><twSpeedVer>PRODUCTION 1.23 2013-10-13</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:2698 - No timing constraints found, doing default enumeration.</twInfo><twInfo anchorID="3">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="4">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="5">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twDataSheet anchorID="6" twNameLen="15"><twClk2OutList anchorID="7" twDestWidth="7" twPhaseWidth="14"><twSrc>CLK27MHz</twSrc><twClk2Out twOutPad = "GPIO&lt;0&gt;" twMinTime = "4.138" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "9.718" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK27MHz_BUFGP" twClkPhase="0.000" ></twClk2Out></twClk2OutList><twClk2SUList anchorID="8" twDestWidth="8"><twDest>CLK27MHz</twDest><twClk2SU><twSrc>CLK27MHz</twSrc><twRiseRise>3.484</twRiseRise></twClk2SU></twClk2SUList><twPad2PadList anchorID="9" twSrcWidth="7" twDestWidth="7"><twPad2Pad><twSrc>GPIO&lt;6&gt;</twSrc><twDest>LEDS&lt;3&gt;</twDest><twDel>9.673</twDel></twPad2Pad></twPad2PadList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twFoot><twTimestamp>Wed Jun 08 12:43:19 2022 </twTimestamp></twFoot><twClientInfo anchorID="10"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
Peak Memory Usage: 218 MB
Peak Memory Usage: 219 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>

5
textovhdl.unroutes
View File

@@ -1,11 +1,11 @@
Release 14.7 - par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Wed Jun 08 11:35:52 2022
Wed Jun 08 12:43:12 2022
All signals are completely routed.
WARNING:ParHelpers:361 - There are 13 loadless signals in this design. This design will cause Bitgen to issue DRC
WARNING:ParHelpers:361 - There are 12 loadless signals in this design. This design will cause Bitgen to issue DRC
warnings.
BUT<0>_IBUF
@@ -19,7 +19,6 @@ WARNING:ParHelpers:361 - There are 13 loadless signals in this design. This desi
GPIO<3>_IBUF
GPIO<4>_IBUF
GPIO<5>_IBUF
GPIO<6>_IBUF
GPIO<7>_IBUF

32
textovhdl.vhd
View File

@@ -19,6 +19,11 @@ signal CLK100k,clk621ms,clk25k: std_logic;
signal clkdisp,cs,din: std_logic;
signal num7,num6,num5,num4,num3,num2,num1,num0: std_logic_vector(3 downto 0);
signal microfone, toggleled, andcontzero: std_logic;
signal EOmicro: std_logic_vector(4 downto 0);
signal contmicro, ffmicro: std_logic_vector (19 downto 0);
signal bLeds: std_logic_vector (3 downto 0);
component display port( NUM7, NUM6, NUM5, NUM4, NUM3, NUM2, NUM1, NUM0: in std_logic_vector(3 downto 0);
CLK: in std_logic;
CS, Dout: out std_logic
@@ -36,12 +41,28 @@ begin
GPIO <= "ZZZZZZZZ";
LEDS <= "ZZZZ";
UC0: CONTBCD_C port map (CLK=>clk100k, CLR=>microfone, UP=>'1', EN=>(not contmicro(19)), ENout=>EOmicro(0), Q=>contmicro(3 downto 0));
UC1: CONTBCD_C port map (CLK=>clk100k, CLR=>microfone, UP=>'1', EN=>EOmicro(0), ENout=>EOmicro(1), Q=>contmicro(7 downto 4));
UC2: CONTBCD_C port map (CLK=>clk100k, CLR=>microfone, UP=>'1', EN=>EOmicro(1), ENout=>EOmicro(2), Q=>contmicro(11 downto 8));
UC3: CONTBCD_C port map (CLK=>clk100k, CLR=>microfone, UP=>'1', EN=>EOmicro(2), ENout=>EOmicro(3), Q=>contmicro(15 downto 12));
UC4: CONTBCD_C port map (CLK=>clk100k, CLR=>microfone, UP=>'1', EN=>EOmicro(3), ENout=>EOmicro(4), Q=>contmicro(19 downto 16));
andcontzero <= '1' when contmicro="00000000000000000000" else '0';
process (clk100k)
begin
if (clk100k'event and clk100k = '1') then
ffmicro <= contmicro;
toggleled <= andcontzero and (not ffmicro(19)) and ffmicro(18);
end if;
end process;
process (toggleled)
begin
if (toggleled'event and toggleled = '1') then
bLeds <= not bLeds;
end if;
end process;
@@ -68,6 +89,11 @@ clkdisp <= contaux(5); -- 421875 Hz
GPIO(0) <= clkdisp;
GPIO(1) <= cs;
GPIO(2) <= din;
microfone <= GPIO(6);
LEDS(3) <= microfone;
LEDS(0) <= bLeds(0);
LEDS(2) <= toggleled;
LEDS(1) <= andcontzero;
end comportamento;

2
textovhdl_guide.ncd
View File

File diff suppressed because one or more lines are too long

90
textovhdl_map.map
View File

@@ -10,17 +10,9 @@ Target Device : xc6slx16
Target Package : csg324
Target Speed : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Wed Jun 08 11:35:36 2022
Mapped Date : Wed Jun 08 12:42:55 2022
Mapping design into LUTs...
WARNING:MapLib:701 - Signal LEDS<3> connected to top level port LEDS<3> has been
removed.
WARNING:MapLib:701 - Signal LEDS<2> connected to top level port LEDS<2> has been
removed.
WARNING:MapLib:701 - Signal LEDS<1> connected to top level port LEDS<1> has been
removed.
WARNING:MapLib:701 - Signal LEDS<0> connected to top level port LEDS<0> has been
removed.
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
@@ -31,50 +23,50 @@ Total REAL time at the beginning of Placer: 5 secs
Total CPU time at the beginning of Placer: 5 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:3fba7d2c) REAL time: 5 secs
Phase 1.1 Initial Placement Analysis (Checksum:d8f2ed64) REAL time: 5 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:3fba7d2c) REAL time: 5 secs
Phase 2.7 Design Feasibility Check (Checksum:d8f2ed64) REAL time: 5 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:3fba7d2c) REAL time: 5 secs
Phase 3.31 Local Placement Optimization (Checksum:d8f2ed64) REAL time: 5 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:a88cf486) REAL time: 6 secs
(Checksum:7ce1aa2f) REAL time: 6 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:a88cf486) REAL time: 6 secs
Phase 5.36 Local Placement Optimization (Checksum:7ce1aa2f) REAL time: 6 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:a88cf486) REAL time: 6 secs
Phase 6.30 Global Clock Region Assignment (Checksum:7ce1aa2f) REAL time: 6 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:a88cf486) REAL time: 6 secs
Phase 7.3 Local Placement Optimization (Checksum:7ce1aa2f) REAL time: 6 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:a88cf486) REAL time: 6 secs
Phase 8.5 Local Placement Optimization (Checksum:7ce1aa2f) REAL time: 6 secs
Phase 9.8 Global Placement
....
....
Phase 9.8 Global Placement (Checksum:74c7df35) REAL time: 6 secs
..........
...
Phase 9.8 Global Placement (Checksum:dba6c2e8) REAL time: 6 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:74c7df35) REAL time: 6 secs
Phase 10.5 Local Placement Optimization (Checksum:dba6c2e8) REAL time: 6 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:b8849b8d) REAL time: 6 secs
Phase 11.18 Placement Optimization (Checksum:941e67b8) REAL time: 7 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:b8849b8d) REAL time: 6 secs
Phase 12.5 Local Placement Optimization (Checksum:941e67b8) REAL time: 7 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:b8849b8d) REAL time: 6 secs
Phase 13.34 Placement Validation (Checksum:93cf0c93) REAL time: 7 secs
Total REAL time to Placer completion: 6 secs
Total CPU time to Placer completion: 6 secs
Total REAL time to Placer completion: 7 secs
Total CPU time to Placer completion: 7 secs
Running post-placement packing...
Writing output files...
@@ -83,18 +75,18 @@ Design Summary
Design Summary:
Number of errors: 0
Number of warnings: 4
Number of warnings: 0
Slice Logic Utilization:
Number of Slice Registers: 32 out of 18,224 1%
Number used as Flip Flops: 32
Number of Slice Registers: 81 out of 18,224 1%
Number used as Flip Flops: 81
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 31 out of 9,112 1%
Number used as logic: 29 out of 9,112 1%
Number using O6 output only: 14
Number using O5 output only: 11
Number using O5 and O6: 4
Number of Slice LUTs: 129 out of 9,112 1%
Number used as logic: 127 out of 9,112 1%
Number using O6 output only: 85
Number using O5 output only: 12
Number using O5 and O6: 30
Number used as ROM: 0
Number used as Memory: 0 out of 2,176 0%
Number used exclusively as route-thrus: 2
@@ -103,15 +95,15 @@ Slice Logic Utilization:
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 11 out of 2,278 1%
Number of MUXCYs used: 20 out of 4,556 1%
Number of LUT Flip Flop pairs used: 31
Number with an unused Flip Flop: 1 out of 31 3%
Number with an unused LUT: 0 out of 31 0%
Number of fully used LUT-FF pairs: 30 out of 31 96%
Number of unique control sets: 2
Number of occupied Slices: 41 out of 2,278 1%
Number of MUXCYs used: 44 out of 4,556 1%
Number of LUT Flip Flop pairs used: 132
Number with an unused Flip Flop: 56 out of 132 42%
Number with an unused LUT: 3 out of 132 2%
Number of fully used LUT-FF pairs: 73 out of 132 55%
Number of unique control sets: 8
Number of slice register sites lost
to control set restrictions: 8 out of 18,224 1%
to control set restrictions: 31 out of 18,224 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
@@ -120,16 +112,16 @@ Slice Logic Distribution:
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 17 out of 232 7%
Number of LOCed IOBs: 17 out of 17 100%
Number of bonded IOBs: 21 out of 232 9%
Number of LOCed IOBs: 21 out of 21 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 32 0%
Number of RAMB8BWERs: 0 out of 64 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 2 out of 16 12%
Number used as BUFGs: 2
Number of BUFG/BUFGMUXs: 3 out of 16 18%
Number used as BUFGs: 3
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 0 out of 248 0%
@@ -148,11 +140,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 1.88
Average Fanout of Non-Clock Nets: 3.39
Peak Memory Usage: 346 MB
Peak Memory Usage: 349 MB
Total REAL time to MAP completion: 7 secs
Total CPU time to MAP completion: 6 secs
Total CPU time to MAP completion: 7 secs
Mapping completed.
See MAP report file "textovhdl_map.mrp" for details.

82
textovhdl_map.mrp
View File

@@ -10,23 +10,23 @@ Target Device : xc6slx16
Target Package : csg324
Target Speed : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Wed Jun 08 11:35:36 2022
Mapped Date : Wed Jun 08 12:42:55 2022
Design Summary
--------------
Number of errors: 0
Number of warnings: 4
Number of warnings: 0
Slice Logic Utilization:
Number of Slice Registers: 32 out of 18,224 1%
Number used as Flip Flops: 32
Number of Slice Registers: 81 out of 18,224 1%
Number used as Flip Flops: 81
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 31 out of 9,112 1%
Number used as logic: 29 out of 9,112 1%
Number using O6 output only: 14
Number using O5 output only: 11
Number using O5 and O6: 4
Number of Slice LUTs: 129 out of 9,112 1%
Number used as logic: 127 out of 9,112 1%
Number using O6 output only: 85
Number using O5 output only: 12
Number using O5 and O6: 30
Number used as ROM: 0
Number used as Memory: 0 out of 2,176 0%
Number used exclusively as route-thrus: 2
@@ -35,15 +35,15 @@ Slice Logic Utilization:
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 11 out of 2,278 1%
Number of MUXCYs used: 20 out of 4,556 1%
Number of LUT Flip Flop pairs used: 31
Number with an unused Flip Flop: 1 out of 31 3%
Number with an unused LUT: 0 out of 31 0%
Number of fully used LUT-FF pairs: 30 out of 31 96%
Number of unique control sets: 2
Number of occupied Slices: 41 out of 2,278 1%
Number of MUXCYs used: 44 out of 4,556 1%
Number of LUT Flip Flop pairs used: 132
Number with an unused Flip Flop: 56 out of 132 42%
Number with an unused LUT: 3 out of 132 2%
Number of fully used LUT-FF pairs: 73 out of 132 55%
Number of unique control sets: 8
Number of slice register sites lost
to control set restrictions: 8 out of 18,224 1%
to control set restrictions: 31 out of 18,224 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
@@ -52,16 +52,16 @@ Slice Logic Distribution:
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 17 out of 232 7%
Number of LOCed IOBs: 17 out of 17 100%
Number of bonded IOBs: 21 out of 232 9%
Number of LOCed IOBs: 21 out of 21 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 32 0%
Number of RAMB8BWERs: 0 out of 64 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 2 out of 16 12%
Number used as BUFGs: 2
Number of BUFG/BUFGMUXs: 3 out of 16 18%
Number used as BUFGs: 3
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 0 out of 248 0%
@@ -80,11 +80,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 1.88
Average Fanout of Non-Clock Nets: 3.39
Peak Memory Usage: 346 MB
Peak Memory Usage: 349 MB
Total REAL time to MAP completion: 7 secs
Total CPU time to MAP completion: 6 secs
Total CPU time to MAP completion: 7 secs
Table of Contents
-----------------
@@ -107,19 +107,11 @@ Section 1 - Errors
Section 2 - Warnings
--------------------
WARNING:MapLib:701 - Signal LEDS<3> connected to top level port LEDS<3> has been
removed.
WARNING:MapLib:701 - Signal LEDS<2> connected to top level port LEDS<2> has been
removed.
WARNING:MapLib:701 - Signal LEDS<1> connected to top level port LEDS<1> has been
removed.
WARNING:MapLib:701 - Signal LEDS<0> connected to top level port LEDS<0> has been
removed.
Section 3 - Informational
-------------------------
INFO:LIT:243 - Logical network BUT<3>_IBUF has no load.
INFO:LIT:395 - The above info message is repeated 12 more times for the
INFO:LIT:395 - The above info message is repeated 11 more times for the
following (max. 5 shown):
BUT<2>_IBUF,
BUT<1>_IBUF,
@@ -141,31 +133,11 @@ INFO:Pack:1650 - Map created a placed design.
Section 4 - Removed Logic Summary
---------------------------------
8 block(s) removed
2 block(s) optimized away
4 signal(s) removed
Section 5 - Removed Logic
-------------------------
The trimmed logic reported below is either:
1. part of a cycle
2. part of disabled logic
3. a side-effect of other trimmed logic
The signal "LEDS<3>" is unused and has been removed.
Unused block "LEDS_3_OBUFT" (TRI) removed.
The signal "LEDS<2>" is unused and has been removed.
Unused block "LEDS_2_OBUFT" (TRI) removed.
The signal "LEDS<1>" is unused and has been removed.
Unused block "LEDS_1_OBUFT" (TRI) removed.
The signal "LEDS<0>" is unused and has been removed.
Unused block "LEDS_0_OBUFT" (TRI) removed.
Unused block "LEDS<0>" (PAD) removed.
Unused block "LEDS<1>" (PAD) removed.
Unused block "LEDS<2>" (PAD) removed.
Unused block "LEDS<3>" (PAD) removed.
Optimized Block(s):
TYPE BLOCK
GND XST_GND
@@ -198,6 +170,10 @@ Section 6 - IOB Properties
| GPIO<5> | IOB | INPUT | LVCMOS25 | | | | | | |
| GPIO<6> | IOB | INPUT | LVCMOS25 | | | | | | |
| GPIO<7> | IOB | INPUT | LVCMOS25 | | | | | | |
| LEDS<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| LEDS<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| LEDS<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| LEDS<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs

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90
textovhdl_map.xrpt
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@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Map" timeStamp="Wed Jun 08 11:35:43 2022">
<application stringID="Map" timeStamp="Wed Jun 08 12:43:02 2022">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@@ -65,16 +65,16 @@
<item DEFAULT="None" label="-p" stringID="MAP_PARTNAME" value="xc6slx16-csg324-2"/>
</section>
<task stringID="MAP_PACK_REPORT">
<item AVAILABLE="18224" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="32">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="32"/>
<item AVAILABLE="18224" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="81">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="81"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
</item>
<item AVAILABLE="9112" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="31">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="11"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="14"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="4"/>
<item AVAILABLE="9112" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="129">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="12"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="85"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="30"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
@@ -94,7 +94,7 @@
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="2"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item>
<item AVAILABLE="232" dataType="int" stringID="MAP_AGG_BONDED_IO" value="17"/>
<item AVAILABLE="232" dataType="int" stringID="MAP_AGG_BONDED_IO" value="21"/>
<item AVAILABLE="12" dataType="int" stringID="MAP_AGG_UNBONDED_IO" value="0"/>
<item AVAILABLE="0" dataType="int" label="IOB Flip Flops" stringID="MAP_NUM_IOB_FF" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IOB_LATCH" value="0"/>
@@ -116,22 +116,22 @@
<section stringID="MAP_DESIGN_SUMMARY">
<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="4"/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="353868"/>
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="0"/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="356940"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="7 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="6 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="7 secs "/>
</section>
<section stringID="MAP_SLICE_REPORTING">
<item AVAILABLE="18224" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="32">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="32"/>
<item AVAILABLE="18224" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="81">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="81"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
</item>
<item AVAILABLE="9112" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="31">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="11"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="14"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="4"/>
<item AVAILABLE="9112" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="129">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="12"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="85"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="30"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
@@ -151,19 +151,19 @@
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="2"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item>
<item AVAILABLE="2278" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="11">
<item AVAILABLE="595" dataType="int" stringID="MAP_NUM_SLICEL" value="5"/>
<item AVAILABLE="2278" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="41">
<item AVAILABLE="595" dataType="int" stringID="MAP_NUM_SLICEL" value="11"/>
<item AVAILABLE="544" dataType="int" stringID="MAP_NUM_SLICEM" value="0"/>
<item AVAILABLE="1139" dataType="int" stringID="MAP_NUM_SLICEX" value="6"/>
<item AVAILABLE="1139" dataType="int" stringID="MAP_NUM_SLICEX" value="30"/>
</item>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="31">
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="1"/>
<item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="0"/>
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="30"/>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="132">
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="56"/>
<item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="3"/>
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="73"/>
</item>
</section>
<section stringID="MAP_IOB_REPORTING">
<item AVAILABLE="232" dataType="int" stringID="MAP_AGG_BONDED_IO" value="17"/>
<item AVAILABLE="232" dataType="int" stringID="MAP_AGG_BONDED_IO" value="21"/>
<item AVAILABLE="12" dataType="int" stringID="MAP_AGG_UNBONDED_IO" value="0"/>
<item AVAILABLE="0" dataType="int" label="IOB Flip Flops" stringID="MAP_NUM_IOB_FF" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IOB_LATCH" value="0"/>
@@ -198,7 +198,7 @@
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_SUSPEND_SYNC" value="0"/>
</section>
<section stringID="MAP_BUFG_DATA">
<item dataType="int" label="Number used as BUFGs" stringID="MAP_NUM_BUFG" value="2"/>
<item dataType="int" label="Number used as BUFGs" stringID="MAP_NUM_BUFG" value="3"/>
<item dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="0"/>
<item dataType="int" stringID="MAP_AVAILABLE" value="16"/>
</section>
@@ -326,11 +326,43 @@
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="18">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="LEDS&lt;0>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="19">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="LEDS&lt;1>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="20">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="LEDS&lt;2>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="21">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="LEDS&lt;3>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
</table>
</section>
<section stringID="MAP_RPM_MACROS">
<section stringID="MAP_SHAPE_SECTION">
<item dataType="int" stringID="MAP_NUM_SHAPE" value="2"/>
<item dataType="int" stringID="MAP_NUM_SHAPE" value="3"/>
</section>
</section>
<section stringID="MAP_GUIDE_REPORT"/>
@@ -339,7 +371,7 @@
<section stringID="MAP_CONFIGURATION_STRING_DETAILS"/>
<section stringID="MAP_GENERAL_CONFIG_DATA"/>
<section stringID="MAP_CONTROL_SET_INFORMATION">
<item dataType="int" label="Number of unique control sets" stringID="MAP_NUM_CONTROL_SETS" value="2"/>
<item dataType="int" label="Number of unique control sets" stringID="MAP_NUM_CONTROL_SETS" value="8"/>
<tree stringID="MAP_CONTROL_SET_HIERARCHY">
<property stringID="MAP_CLOCK_SIGNAL"/>
<property stringID="MAP_RESET_SIGNAL"/>
@@ -371,7 +403,7 @@
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_SUSPEND_SYNC" value="0"/>
</section>
<section stringID="MAP_BUFG_DATA">
<item dataType="int" label="Number used as BUFGs" stringID="MAP_NUM_BUFG" value="2"/>
<item dataType="int" label="Number used as BUFGs" stringID="MAP_NUM_BUFG" value="3"/>
<item dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="0"/>
<item dataType="int" stringID="MAP_AVAILABLE" value="16"/>
<item dataType="int" stringID="MAP_HARD_MACROS" value="0"/>

63
textovhdl_ngdbuild.xrpt
View File

@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Wed Jun 08 11:35:33 2022">
<application stringID="NgdBuild" timeStamp="Wed Jun 08 12:42:52 2022">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@@ -61,48 +61,51 @@
<section stringID="NGDBUILD_DESIGN_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="NGDBUILD_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="5"/>
<item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="4"/>
<item dataType="int" stringID="NGDBUILD_FILTERED_INFOS" value="0"/>
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
</section>
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_BUFGP" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="15"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD_1" value="17"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="44"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDCE" value="20"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR_1" value="13"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD_1" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="13"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="5"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="5"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="5"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="13"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="31"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="14"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="7"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="9"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="43"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="28"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="36"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="7"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="15"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="39"/>
</section>
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="15"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD_1" value="17"/>
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="44"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDCE" value="20"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR_1" value="13"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD_1" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="13"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="13"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="5"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="5"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="5"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="13"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="31"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="14"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="7"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="9"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="43"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="28"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="36"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="7"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="15"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="39"/>
</section>
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
<section stringID="NGDBUILD_CORE_INSTANCES"/>

10
textovhdl_pad.csv
View File

@@ -1,7 +1,7 @@
#Release 14.7 - par P.20131013 (nt64)
#Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
#Wed Jun 08 11:35:52 2022
#Wed Jun 08 12:43:12 2022
#
## NOTE: This file is designed to be imported into a spreadsheet program
@@ -22,7 +22,7 @@ Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,D
A1,,,GND,,,,,,,,,,,,
A2,,IOBS,IO_L2N_0,UNUSED,,0,,,,,,,,,
A3,GPIO<2>,IOB,IO_L4N_0,OUTPUT,LVCMOS25*,0,12,SLOW,,,,LOCATED,NO,NONE,
A4,,IOBS,IO_L5N_0,UNUSED,,0,,,,,,,,,
A4,LEDS<3>,IOB,IO_L5N_0,OUTPUT,LVCMOS25*,0,12,SLOW,,,,LOCATED,NO,NONE,
A5,,IOBS,IO_L6N_0,UNUSED,,0,,,,,,,,,
A6,,IOBS,IO_L8N_VREF_0,UNUSED,,0,,,,,,,,,
A7,,IOBS,IO_L10N_0,UNUSED,,0,,,,,,,,,
@@ -58,7 +58,7 @@ B18,,,TMS,,,,,,,,,,,,
C1,,IOBS,IO_L83N_VREF_3,UNUSED,,3,,,,,,,,,
C2,,IOBM,IO_L83P_3,UNUSED,,3,,,,,,,,,
C3,,,GND,,,,,,,,,,,,
C4,,IOBS,IO_L1N_VREF_0,UNUSED,,0,,,,,,,,,
C4,LEDS<2>,IOB,IO_L1N_VREF_0,OUTPUT,LVCMOS25*,0,12,SLOW,,,,LOCATED,NO,NONE,
C5,,IOBM,IO_L6P_0,UNUSED,,0,,,,,,,,,
C6,,IOBS,IO_L3N_0,UNUSED,,0,,,,,,,,,
C7,,IOBM,IO_L10P_0,UNUSED,,0,,,,,,,,,
@@ -68,7 +68,7 @@ C10,,IOBM,IO_L37P_GCLK13_0,UNUSED,,0,,,,,,,,,
C11,,IOBS,IO_L36N_GCLK14_0,UNUSED,,0,,,,,,,,,
C12,,IOBS,IO_L47N_0,UNUSED,,0,,,,,,,,,
C13,,IOBM,IO_L50P_0,UNUSED,,0,,,,,,,,,
C14,,IOBS,IO_L65N_SCP2_0,UNUSED,,0,,,,,,,,,
C14,LEDS<1>,IOB,IO_L65N_SCP2_0,OUTPUT,LVCMOS25*,0,12,SLOW,,,,LOCATED,NO,NONE,
C15,,IOBM,IO_L64P_SCP5_0,UNUSED,,0,,,,,,,,,
C16,,,GND,,,,,,,,,,,,
C17,,IOBM,IO_L29P_A23_M1A13_1,UNUSED,,1,,,,,,,,,
@@ -103,7 +103,7 @@ E9,,,VCCAUX,,,,,,,,2.5,,,,
E10,,,VCCO_0,,,0,,,,,2.50,,,,
E11,,IOBS,IO_L42N_0,UNUSED,,0,,,,,,,,,
E12,DIPSW<1>,IOB,IO_L51N_0,INPUT,LVCMOS25*,0,,,,NONE,,LOCATED,NO,NONE,
E13,,IOBS,IO_L63N_SCP6_0,UNUSED,,0,,,,,,,,,
E13,LEDS<0>,IOB,IO_L63N_SCP6_0,OUTPUT,LVCMOS25*,0,12,SLOW,,,,LOCATED,NO,NONE,
E14,,,VCCAUX,,,,,,,,2.5,,,,
E15,,,GND,,,,,,,,,,,,
E16,,IOBM,IO_L33P_A15_M1A10_1,UNUSED,,1,,,,,,,,,
1 #Release 14.7 - par P.20131013 (nt64)
2 #Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
3 #Wed Jun 08 11:35:52 2022 #Wed Jun 08 12:43:12 2022
4 #
5 ## NOTE: This file is designed to be imported into a spreadsheet program
6 # such as Microsoft Excel for viewing, printing and sorting. The |
7 # character is used as the data field separator. This file is also designed
22 A3,GPIO<2>,IOB,IO_L4N_0,OUTPUT,LVCMOS25*,0,12,SLOW,,,,LOCATED,NO,NONE,
23 A4,,IOBS,IO_L5N_0,UNUSED,,0,,,,,,,,, A4,LEDS<3>,IOB,IO_L5N_0,OUTPUT,LVCMOS25*,0,12,SLOW,,,,LOCATED,NO,NONE,
24 A5,,IOBS,IO_L6N_0,UNUSED,,0,,,,,,,,,
25 A6,,IOBS,IO_L8N_VREF_0,UNUSED,,0,,,,,,,,,
26 A7,,IOBS,IO_L10N_0,UNUSED,,0,,,,,,,,,
27 A8,,IOBS,IO_L33N_0,UNUSED,,0,,,,,,,,,
28 A9,,IOBS,IO_L35N_GCLK16_0,UNUSED,,0,,,,,,,,,
58 C3,,,GND,,,,,,,,,,,,
59 C4,,IOBS,IO_L1N_VREF_0,UNUSED,,0,,,,,,,,, C4,LEDS<2>,IOB,IO_L1N_VREF_0,OUTPUT,LVCMOS25*,0,12,SLOW,,,,LOCATED,NO,NONE,
60 C5,,IOBM,IO_L6P_0,UNUSED,,0,,,,,,,,,
61 C6,,IOBS,IO_L3N_0,UNUSED,,0,,,,,,,,,
62 C7,,IOBM,IO_L10P_0,UNUSED,,0,,,,,,,,,
63 C8,,IOBS,IO_L11N_0,UNUSED,,0,,,,,,,,,
64 C9,,IOBS,IO_L34N_GCLK18_0,UNUSED,,0,,,,,,,,,
68 C13,,IOBM,IO_L50P_0,UNUSED,,0,,,,,,,,,
69 C14,,IOBS,IO_L65N_SCP2_0,UNUSED,,0,,,,,,,,, C14,LEDS<1>,IOB,IO_L65N_SCP2_0,OUTPUT,LVCMOS25*,0,12,SLOW,,,,LOCATED,NO,NONE,
70 C15,,IOBM,IO_L64P_SCP5_0,UNUSED,,0,,,,,,,,,
71 C16,,,GND,,,,,,,,,,,,
72 C17,,IOBM,IO_L29P_A23_M1A13_1,UNUSED,,1,,,,,,,,,
73 C18,,IOBS,IO_L29N_A22_M1A14_1,UNUSED,,1,,,,,,,,,
74 D1,,IOBS,IO_L52N_M3A9_3,UNUSED,,3,,,,,,,,,
103 E12,DIPSW<1>,IOB,IO_L51N_0,INPUT,LVCMOS25*,0,,,,NONE,,LOCATED,NO,NONE,
104 E13,,IOBS,IO_L63N_SCP6_0,UNUSED,,0,,,,,,,,, E13,LEDS<0>,IOB,IO_L63N_SCP6_0,OUTPUT,LVCMOS25*,0,12,SLOW,,,,LOCATED,NO,NONE,
105 E14,,,VCCAUX,,,,,,,,2.5,,,,
106 E15,,,GND,,,,,,,,,,,,
107 E16,,IOBM,IO_L33P_A15_M1A10_1,UNUSED,,1,,,,,,,,,
108 E17,,,VCCO_1,,,1,,,,,2.50,,,,
109 E18,,IOBS,IO_L33N_A14_M1A4_1,UNUSED,,1,,,,,,,,,

10
textovhdl_pad.txt
View File

@@ -1,7 +1,7 @@
Release 14.7 - par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Wed Jun 08 11:35:52 2022
Wed Jun 08 12:43:12 2022
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
@@ -23,7 +23,7 @@ Pinout by Pin Number:
|A1 | | |GND | | | | | | | | | | | |
|A2 | |IOBS |IO_L2N_0 |UNUSED | |0 | | | | | | | | |
|A3 |GPIO<2> |IOB |IO_L4N_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW | | | |LOCATED |NO |NONE |
|A4 | |IOBS |IO_L5N_0 |UNUSED | |0 | | | | | | | | |
|A4 |LEDS<3> |IOB |IO_L5N_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW | | | |LOCATED |NO |NONE |
|A5 | |IOBS |IO_L6N_0 |UNUSED | |0 | | | | | | | | |
|A6 | |IOBS |IO_L8N_VREF_0 |UNUSED | |0 | | | | | | | | |
|A7 | |IOBS |IO_L10N_0 |UNUSED | |0 | | | | | | | | |
@@ -59,7 +59,7 @@ Pinout by Pin Number:
|C1 | |IOBS |IO_L83N_VREF_3 |UNUSED | |3 | | | | | | | | |
|C2 | |IOBM |IO_L83P_3 |UNUSED | |3 | | | | | | | | |
|C3 | | |GND | | | | | | | | | | | |
|C4 | |IOBS |IO_L1N_VREF_0 |UNUSED | |0 | | | | | | | | |
|C4 |LEDS<2> |IOB |IO_L1N_VREF_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW | | | |LOCATED |NO |NONE |
|C5 | |IOBM |IO_L6P_0 |UNUSED | |0 | | | | | | | | |
|C6 | |IOBS |IO_L3N_0 |UNUSED | |0 | | | | | | | | |
|C7 | |IOBM |IO_L10P_0 |UNUSED | |0 | | | | | | | | |
@@ -69,7 +69,7 @@ Pinout by Pin Number:
|C11 | |IOBS |IO_L36N_GCLK14_0 |UNUSED | |0 | | | | | | | | |
|C12 | |IOBS |IO_L47N_0 |UNUSED | |0 | | | | | | | | |
|C13 | |IOBM |IO_L50P_0 |UNUSED | |0 | | | | | | | | |
|C14 | |IOBS |IO_L65N_SCP2_0 |UNUSED | |0 | | | | | | | | |
|C14 |LEDS<1> |IOB |IO_L65N_SCP2_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW | | | |LOCATED |NO |NONE |
|C15 | |IOBM |IO_L64P_SCP5_0 |UNUSED | |0 | | | | | | | | |
|C16 | | |GND | | | | | | | | | | | |
|C17 | |IOBM |IO_L29P_A23_M1A13_1 |UNUSED | |1 | | | | | | | | |
@@ -104,7 +104,7 @@ Pinout by Pin Number:
|E10 | | |VCCO_0 | | |0 | | | | |2.50 | | | |
|E11 | |IOBS |IO_L42N_0 |UNUSED | |0 | | | | | | | | |
|E12 |DIPSW<1> |IOB |IO_L51N_0 |INPUT |LVCMOS25* |0 | | | |NONE | |LOCATED |NO |NONE |
|E13 | |IOBS |IO_L63N_SCP6_0 |UNUSED | |0 | | | | | | | | |
|E13 |LEDS<0> |IOB |IO_L63N_SCP6_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW | | | |LOCATED |NO |NONE |
|E14 | | |VCCAUX | | | | | | | |2.5 | | | |
|E15 | | |GND | | | | | | | | | | | |
|E16 | |IOBM |IO_L33P_A15_M1A10_1 |UNUSED | |1 | | | | | | | | |

84
textovhdl_par.xrpt
View File

@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="par" timeStamp="Wed Jun 08 11:35:50 2022">
<application stringID="par" timeStamp="Wed Jun 08 12:43:09 2022">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@@ -59,8 +59,8 @@
</task>
<task stringID="PAR_PAR">
<section stringID="PAR_DESIGN_SUMMARY">
<item stringID="PAR_REAL_TIME_COMPLETION_ROUTER" value="5 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="5 secs "/>
<item stringID="PAR_REAL_TIME_COMPLETION_ROUTER" value="6 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="6 secs "/>
<item dataType="int" stringID="PAR_UNROUTES" value="0"/>
<item dataType="float" stringID="PAR_TIMING_SCORE" value="0.000000"/>
<item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="6 secs "/>
@@ -112,10 +112,17 @@
</row>
<row stringID="row" value="4">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="A4"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="LEDS&lt;3>"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L5N_0"/>
<item stringID="Direction" value="UNUSED"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
<item label="Slew&#xA;Rate" stringID="Slew_Rate" value="SLOW"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="5">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="A5"/>
@@ -345,10 +352,17 @@
</row>
<row stringID="row" value="40">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="C4"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="LEDS&lt;2>"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L1N_VREF_0"/>
<item stringID="Direction" value="UNUSED"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
<item label="Slew&#xA;Rate" stringID="Slew_Rate" value="SLOW"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="41">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="C5"/>
@@ -415,10 +429,17 @@
</row>
<row stringID="row" value="50">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="C14"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="LEDS&lt;1>"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L65N_SCP2_0"/>
<item stringID="Direction" value="UNUSED"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
<item label="Slew&#xA;Rate" stringID="Slew_Rate" value="SLOW"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="51">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="C15"/>
@@ -655,10 +676,17 @@
</row>
<row stringID="row" value="85">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="E13"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="LEDS&lt;0>"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L63N_SCP6_0"/>
<item stringID="Direction" value="UNUSED"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
<item label="Slew&#xA;Rate" stringID="Slew_Rate" value="SLOW"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="86">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="E14"/>
@@ -2263,12 +2291,12 @@
<section stringID="PAR_UNROUTES_REPORT">
<item dataType="int" stringID="PAR_UNROUTED_NETS" value="0"/>
<item dataType="int" stringID="PAR_TOTAL_SOURCELESS_NETS" value="0"/>
<item dataType="int" stringID="PAR_TOTAL_LOADLESS_NETS" value="13"/>
<item dataType="int" stringID="PAR_TOTAL_LOADLESS_NETS" value="12"/>
</section>
</task>
</application>
<application stringID="Par" timeStamp="Wed Jun 08 11:35:50 2022">
<application stringID="Par" timeStamp="Wed Jun 08 12:43:09 2022">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@@ -2314,16 +2342,16 @@
</section>
<task label="Device Utilization Summary" stringID="PAR_DEVICE_UTLIZATION">
<section stringID="PAR_SLICE_REPORTING">
<item AVAILABLE="18224" dataType="int" label="Number of Slice Registers" stringID="PAR_SLICE_REGISTERS" value="32">
<item dataType="int" stringID="PAR_NUM_SLICE_FF" value="32"/>
<item AVAILABLE="18224" dataType="int" label="Number of Slice Registers" stringID="PAR_SLICE_REGISTERS" value="81">
<item dataType="int" stringID="PAR_NUM_SLICE_FF" value="81"/>
<item dataType="int" stringID="PAR_NUM_SLICE_LATCH" value="0"/>
<item dataType="int" stringID="PAR_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="PAR_NUM_SLICE_LATCHLOGIC" value="0"/>
</item>
<item AVAILABLE="9112" dataType="int" label="Number of Slice LUTS" stringID="PAR_SLICE_LUTS" value="31">
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ONLY" value="11"/>
<item dataType="int" stringID="PAR_NUM_LOGIC_O6ONLY" value="14"/>
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ANDO6" value="4"/>
<item AVAILABLE="9112" dataType="int" label="Number of Slice LUTS" stringID="PAR_SLICE_LUTS" value="129">
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ONLY" value="12"/>
<item dataType="int" stringID="PAR_NUM_LOGIC_O6ONLY" value="85"/>
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ANDO6" value="30"/>
<item dataType="int" stringID="PAR_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="PAR_NUM_ROM_O6ONLY" value="0"/>
<item dataType="int" stringID="PAR_NUM_ROM_O5ANDO6" value="0"/>
@@ -2343,19 +2371,19 @@
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_CARRY4" value="2"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item>
<item AVAILABLE="2278" dataType="int" stringID="PAR_OCCUPIED_SLICES" value="11">
<item AVAILABLE="595" dataType="int" stringID="PAR_NUM_SLICEL" value="5"/>
<item AVAILABLE="2278" dataType="int" stringID="PAR_OCCUPIED_SLICES" value="41">
<item AVAILABLE="595" dataType="int" stringID="PAR_NUM_SLICEL" value="11"/>
<item AVAILABLE="544" dataType="int" stringID="PAR_NUM_SLICEM" value="0"/>
<item AVAILABLE="1139" dataType="int" stringID="PAR_NUM_SLICEX" value="6"/>
<item AVAILABLE="1139" dataType="int" stringID="PAR_NUM_SLICEX" value="30"/>
</item>
<item dataType="int" stringID="PAR_OCCUPIED_LUT_AND_FF" value="31">
<item dataType="int" stringID="PAR_OCCUPIED_LUT_ONLY" value="1"/>
<item dataType="int" stringID="PAR_OCCUPIED_FF_ONLY" value="0"/>
<item dataType="int" stringID="PAR_OCCUPIED_FF_AND_LUT" value="30"/>
<item dataType="int" stringID="PAR_OCCUPIED_LUT_AND_FF" value="132">
<item dataType="int" stringID="PAR_OCCUPIED_LUT_ONLY" value="56"/>
<item dataType="int" stringID="PAR_OCCUPIED_FF_ONLY" value="3"/>
<item dataType="int" stringID="PAR_OCCUPIED_FF_AND_LUT" value="73"/>
</item>
</section>
<section stringID="PAR_IOB_REPORTING">
<item AVAILABLE="232" dataType="int" stringID="PAR_AGG_BONDED_IO" value="17"/>
<item AVAILABLE="232" dataType="int" stringID="PAR_AGG_BONDED_IO" value="21"/>
<item AVAILABLE="12" dataType="int" stringID="PAR_AGG_UNBONDED_IO" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="PAR_NUM_IOB_FF" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="PAR_NUM_IOB_LATCH" value="0"/>
@@ -2390,7 +2418,7 @@
<item AVAILABLE="1" dataType="int" stringID="PAR_NUM_SUSPEND_SYNC" value="0"/>
</section>
<section stringID="PAR_BUFG_DATA">
<item dataType="int" stringID="PAR_NUM_BUFG" value="2"/>
<item dataType="int" stringID="PAR_NUM_BUFG" value="3"/>
<item dataType="int" stringID="PAR_NUM_BUFGMUX" value="0"/>
<item dataType="int" stringID="PAR_AVAILABLE" value="16"/>
</section>

83
textovhdl_summary.html
View File

@@ -2,7 +2,7 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>textovhdl Project Status (06/08/2022 - 11:36:16)</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>textovhdl Project Status (06/08/2022 - 12:43:44)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>Aula20220608.xise</TD>
@@ -19,13 +19,12 @@
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc6slx16-2csg324</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>
No Errors</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/*.xmsgs?&DataKey=Warning'>56 Warnings (56 new)</A></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
@@ -60,13 +59,13 @@ System Settings</A>
<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
<TD ALIGN=RIGHT>32</TD>
<TD ALIGN=RIGHT>81</TD>
<TD ALIGN=RIGHT>18,224</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Flip Flops</TD>
<TD ALIGN=RIGHT>32</TD>
<TD ALIGN=RIGHT>81</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
@@ -90,31 +89,31 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
<TD ALIGN=RIGHT>31</TD>
<TD ALIGN=RIGHT>129</TD>
<TD ALIGN=RIGHT>9,112</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
<TD ALIGN=RIGHT>29</TD>
<TD ALIGN=RIGHT>127</TD>
<TD ALIGN=RIGHT>9,112</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
<TD ALIGN=RIGHT>14</TD>
<TD ALIGN=RIGHT>85</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
<TD ALIGN=RIGHT>11</TD>
<TD ALIGN=RIGHT>12</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>30</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
@@ -156,62 +155,62 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
<TD ALIGN=RIGHT>11</TD>
<TD ALIGN=RIGHT>41</TD>
<TD ALIGN=RIGHT>2,278</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MUXCYs used</TD>
<TD ALIGN=RIGHT>20</TD>
<TD ALIGN=RIGHT>44</TD>
<TD ALIGN=RIGHT>4,556</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
<TD ALIGN=RIGHT>31</TD>
<TD ALIGN=RIGHT>132</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused Flip Flop</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>31</TD>
<TD ALIGN=RIGHT>3%</TD>
<TD ALIGN=RIGHT>56</TD>
<TD ALIGN=RIGHT>132</TD>
<TD ALIGN=RIGHT>42%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused LUT</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>31</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD ALIGN=RIGHT>3</TD>
<TD ALIGN=RIGHT>132</TD>
<TD ALIGN=RIGHT>2%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of fully used LUT-FF pairs</TD>
<TD ALIGN=RIGHT>30</TD>
<TD ALIGN=RIGHT>31</TD>
<TD ALIGN=RIGHT>96%</TD>
<TD ALIGN=RIGHT>73</TD>
<TD ALIGN=RIGHT>132</TD>
<TD ALIGN=RIGHT>55%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of unique control sets</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>8</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of slice register sites lost<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;to control set restrictions</TD>
<TD ALIGN=RIGHT>8</TD>
<TD ALIGN=RIGHT>31</TD>
<TD ALIGN=RIGHT>18,224</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
<TD ALIGN=RIGHT>17</TD>
<TD ALIGN=RIGHT>21</TD>
<TD ALIGN=RIGHT>232</TD>
<TD ALIGN=RIGHT>7%</TD>
<TD ALIGN=RIGHT>9%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of LOCed IOBs</TD>
<TD ALIGN=RIGHT>17</TD>
<TD ALIGN=RIGHT>17</TD>
<TD ALIGN=RIGHT>21</TD>
<TD ALIGN=RIGHT>21</TD>
<TD ALIGN=RIGHT>100%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
@@ -240,13 +239,13 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>3</TD>
<TD ALIGN=RIGHT>16</TD>
<TD ALIGN=RIGHT>12%</TD>
<TD ALIGN=RIGHT>18%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGs</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>3</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
@@ -354,7 +353,7 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
<TD ALIGN=RIGHT>1.88</TD>
<TD ALIGN=RIGHT>3.39</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
@@ -391,21 +390,21 @@ System Settings</A>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Jun 8 11:34:43 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/xst.xmsgs?&DataKey=Warning'>32 Warnings (32 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/xst.xmsgs?&DataKey=Info'>1 Info (1 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl.bld'>Translation Report</A></TD><TD>Current</TD><TD>Wed Jun 8 11:35:33 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>5 Warnings (5 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Wed Jun 8 11:35:43 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/map.xmsgs?&DataKey=Warning'>4 Warnings (4 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/map.xmsgs?&DataKey=Info'>8 Infos (8 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Wed Jun 8 11:35:52 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/par.xmsgs?&DataKey=Warning'>15 Warnings (15 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/par.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Jun 8 12:42:38 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/xst.xmsgs?&DataKey=Warning'>38 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/xst.xmsgs?&DataKey=Info'>3 Infos (1 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl.bld'>Translation Report</A></TD><TD>Current</TD><TD>Wed Jun 8 12:42:52 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>4 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Wed Jun 8 12:43:03 2022</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Wed Jun 8 12:43:12 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/par.xmsgs?&DataKey=Warning'>14 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/par.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Wed Jun 8 11:35:59 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/trce.xmsgs?&DataKey=Info'>4 Infos (4 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Wed Jun 8 11:36:14 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Wed Jun 8 12:43:19 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/trce.xmsgs?&DataKey=Info'>4 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Wed Jun 8 12:43:41 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Jun 8 11:36:14 2022</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Jun 8 11:36:16 2022</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Jun 8 12:43:42 2022</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Jun 8 12:43:43 2022</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 06/08/2022 - 11:36:16</center>
<br><center><b>Date Generated:</b> 06/08/2022 - 12:43:44</center>
</BODY></HTML>

2
textovhdl_summary.xml
View File

@@ -4,7 +4,7 @@
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DesignSummary rev="2">
<DesignSummary rev="8">
<CmdHistory>
</CmdHistory>
</DesignSummary>

704
textovhdl_usage.xml
View File

@@ -4,407 +4,469 @@
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DeviceUsageSummary rev="2">
<DesignStatistics TimeStamp="Wed Jun 08 11:36:13 2022"><group name="NetStatistics">
<item name="NumNets_Active" rev="2">
<attrib name="value" value="69"/></item>
<item name="NumNets_Vcc" rev="2">
<DeviceUsageSummary rev="8">
<DesignStatistics TimeStamp="Wed Jun 08 12:43:41 2022"><group name="NetStatistics">
<item name="NumNets_Active" rev="8">
<attrib name="value" value="185"/></item>
<item name="NumNets_Vcc" rev="8">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Active_BOUNCEACROSS" rev="2">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Active_BOUNCEIN" rev="2">
<item name="NumNodesOfType_Active_BOUNCEACROSS" rev="8">
<attrib name="value" value="6"/></item>
<item name="NumNodesOfType_Active_BUFGOUT" rev="2">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Active_BUFHINP2OUT" rev="2">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Active_CLKPIN" rev="2">
<attrib name="value" value="10"/></item>
<item name="NumNodesOfType_Active_CLKPINFEED" rev="2">
<attrib name="value" value="6"/></item>
<item name="NumNodesOfType_Active_DOUBLE" rev="2">
<attrib name="value" value="8"/></item>
<item name="NumNodesOfType_Active_GENERIC" rev="2">
<item name="NumNodesOfType_Active_BOUNCEIN" rev="8">
<attrib name="value" value="24"/></item>
<item name="NumNodesOfType_Active_BUFGOUT" rev="8">
<attrib name="value" value="3"/></item>
<item name="NumNodesOfType_Active_BUFHINP2OUT" rev="8">
<attrib name="value" value="4"/></item>
<item name="NumNodesOfType_Active_GLOBAL" rev="2">
<attrib name="value" value="14"/></item>
<item name="NumNodesOfType_Active_INPUT" rev="2">
<attrib name="value" value="5"/></item>
<item name="NumNodesOfType_Active_IOBIN2OUT" rev="2">
<item name="NumNodesOfType_Active_CLKPIN" rev="8">
<attrib name="value" value="30"/></item>
<item name="NumNodesOfType_Active_CLKPINFEED" rev="8">
<attrib name="value" value="12"/></item>
<item name="NumNodesOfType_Active_CNTRLPIN" rev="8">
<attrib name="value" value="23"/></item>
<item name="NumNodesOfType_Active_DOUBLE" rev="8">
<attrib name="value" value="95"/></item>
<item name="NumNodesOfType_Active_GENERIC" rev="8">
<attrib name="value" value="10"/></item>
<item name="NumNodesOfType_Active_GLOBAL" rev="8">
<attrib name="value" value="26"/></item>
<item name="NumNodesOfType_Active_INPUT" rev="8">
<attrib name="value" value="11"/></item>
<item name="NumNodesOfType_Active_IOBIN2OUT" rev="8">
<attrib name="value" value="8"/></item>
<item name="NumNodesOfType_Active_IOBOUTPUT" rev="8">
<attrib name="value" value="8"/></item>
<item name="NumNodesOfType_Active_LUTINPUT" rev="8">
<attrib name="value" value="470"/></item>
<item name="NumNodesOfType_Active_OUTBOUND" rev="8">
<attrib name="value" value="145"/></item>
<item name="NumNodesOfType_Active_OUTPUT" rev="8">
<attrib name="value" value="157"/></item>
<item name="NumNodesOfType_Active_PADINPUT" rev="8">
<attrib name="value" value="7"/></item>
<item name="NumNodesOfType_Active_PADOUTPUT" rev="8">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Active_PINBOUNCE" rev="8">
<attrib name="value" value="75"/></item>
<item name="NumNodesOfType_Active_PINFEED" rev="8">
<attrib name="value" value="525"/></item>
<item name="NumNodesOfType_Active_QUAD" rev="8">
<attrib name="value" value="42"/></item>
<item name="NumNodesOfType_Active_REGINPUT" rev="8">
<attrib name="value" value="3"/></item>
<item name="NumNodesOfType_Active_IOBOUTPUT" rev="2">
<attrib name="value" value="3"/></item>
<item name="NumNodesOfType_Active_LUTINPUT" rev="2">
<attrib name="value" value="86"/></item>
<item name="NumNodesOfType_Active_OUTBOUND" rev="2">
<attrib name="value" value="33"/></item>
<item name="NumNodesOfType_Active_OUTPUT" rev="2">
<attrib name="value" value="39"/></item>
<item name="NumNodesOfType_Active_PADINPUT" rev="2">
<attrib name="value" value="3"/></item>
<item name="NumNodesOfType_Active_PADOUTPUT" rev="2">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Active_PINBOUNCE" rev="2">
<attrib name="value" value="19"/></item>
<item name="NumNodesOfType_Active_PINFEED" rev="2">
<attrib name="value" value="102"/></item>
<item name="NumNodesOfType_Active_QUAD" rev="2">
<attrib name="value" value="22"/></item>
<item name="NumNodesOfType_Active_SINGLE" rev="2">
<attrib name="value" value="20"/></item>
<item name="NumNodesOfType_Vcc_HVCCOUT" rev="2">
<attrib name="value" value="5"/></item>
<item name="NumNodesOfType_Vcc_LUTINPUT" rev="2">
<attrib name="value" value="15"/></item>
<item name="NumNodesOfType_Vcc_PINFEED" rev="2">
<attrib name="value" value="15"/></item>
<item name="NumNodesOfType_Active_SINGLE" rev="8">
<attrib name="value" value="237"/></item>
<item name="NumNodesOfType_Vcc_HVCCOUT" rev="8">
<attrib name="value" value="13"/></item>
<item name="NumNodesOfType_Vcc_LUTINPUT" rev="8">
<attrib name="value" value="42"/></item>
<item name="NumNodesOfType_Vcc_PINFEED" rev="8">
<attrib name="value" value="42"/></item>
</group>
<group name="SiteStatistics">
<item name="BUFG-BUFGMUX" rev="2">
<attrib name="value" value="2"/></item>
<item name="IOB-IOBM" rev="2">
<item name="BUFG-BUFGMUX" rev="8">
<attrib name="value" value="3"/></item>
<item name="IOB-IOBM" rev="8">
<attrib name="value" value="10"/></item>
<item name="IOB-IOBS" rev="2">
<attrib name="value" value="7"/></item>
<item name="SLICEL-SLICEM" rev="2">
<attrib name="value" value="2"/></item>
<item name="SLICEX-SLICEL" rev="2">
<attrib name="value" value="1"/></item>
<item name="SLICEX-SLICEM" rev="2">
<attrib name="value" value="2"/></item>
<item name="IOB-IOBS" rev="8">
<attrib name="value" value="11"/></item>
<item name="SLICEL-SLICEM" rev="8">
<attrib name="value" value="11"/></item>
<item name="SLICEX-SLICEL" rev="8">
<attrib name="value" value="10"/></item>
<item name="SLICEX-SLICEM" rev="8">
<attrib name="value" value="6"/></item>
</group>
<group name="MiscellaneousStatistics">
<item name="AGG_BONDED_IO" rev="1">
<attrib name="value" value="17"/></item>
<item name="AGG_IO" rev="1">
<attrib name="value" value="17"/></item>
<item name="AGG_LOCED_IO" rev="1">
<attrib name="value" value="17"/></item>
<item name="AGG_SLICE" rev="1">
<attrib name="value" value="11"/></item>
<item name="NUM_BONDED_IOB" rev="1">
<attrib name="value" value="17"/></item>
<item name="NUM_BSFULL" rev="1">
<item name="AGG_BONDED_IO" rev="7">
<attrib name="value" value="21"/></item>
<item name="AGG_IO" rev="7">
<attrib name="value" value="21"/></item>
<item name="AGG_LOCED_IO" rev="7">
<attrib name="value" value="21"/></item>
<item name="AGG_SLICE" rev="7">
<attrib name="value" value="41"/></item>
<item name="NUM_BONDED_IOB" rev="7">
<attrib name="value" value="21"/></item>
<item name="NUM_BSFULL" rev="7">
<attrib name="value" value="73"/></item>
<item name="NUM_BSLUTONLY" rev="7">
<attrib name="value" value="56"/></item>
<item name="NUM_BSREGONLY" rev="7">
<attrib name="value" value="3"/></item>
<item name="NUM_BSUSED" rev="7">
<attrib name="value" value="132"/></item>
<item name="NUM_BUFG" rev="7">
<attrib name="value" value="3"/></item>
<item name="NUM_LOCED_IOB" rev="7">
<attrib name="value" value="21"/></item>
<item name="NUM_LOGIC_O5ANDO6" rev="7">
<attrib name="value" value="30"/></item>
<item name="NUM_BSLUTONLY" rev="1">
<attrib name="value" value="1"/></item>
<item name="NUM_BSUSED" rev="1">
<attrib name="value" value="31"/></item>
<item name="NUM_BUFG" rev="1">
<item name="NUM_LOGIC_O5ONLY" rev="7">
<attrib name="value" value="12"/></item>
<item name="NUM_LOGIC_O6ONLY" rev="7">
<attrib name="value" value="85"/></item>
<item name="NUM_LUT_RT_DRIVES_CARRY4" rev="7">
<attrib name="value" value="2"/></item>
<item name="NUM_LOCED_IOB" rev="1">
<attrib name="value" value="17"/></item>
<item name="NUM_LOGIC_O5ANDO6" rev="1">
<attrib name="value" value="4"/></item>
<item name="NUM_LOGIC_O5ONLY" rev="1">
<item name="NUM_LUT_RT_EXO6" rev="7">
<attrib name="value" value="2"/></item>
<item name="NUM_LUT_RT_O6" rev="7">
<attrib name="value" value="12"/></item>
<item name="NUM_SLICEL" rev="7">
<attrib name="value" value="11"/></item>
<item name="NUM_LOGIC_O6ONLY" rev="1">
<attrib name="value" value="14"/></item>
<item name="NUM_LUT_RT_DRIVES_CARRY4" rev="1">
<attrib name="value" value="2"/></item>
<item name="NUM_LUT_RT_EXO6" rev="1">
<attrib name="value" value="2"/></item>
<item name="NUM_LUT_RT_O6" rev="1">
<item name="NUM_SLICEX" rev="7">
<attrib name="value" value="30"/></item>
<item name="NUM_SLICE_CARRY4" rev="7">
<attrib name="value" value="11"/></item>
<item name="NUM_SLICEL" rev="1">
<attrib name="value" value="5"/></item>
<item name="NUM_SLICEX" rev="1">
<attrib name="value" value="6"/></item>
<item name="NUM_SLICE_CARRY4" rev="1">
<attrib name="value" value="5"/></item>
<item name="NUM_SLICE_CONTROLSET" rev="1">
<attrib name="value" value="2"/></item>
<item name="NUM_SLICE_CYINIT" rev="1">
<attrib name="value" value="48"/></item>
<item name="NUM_SLICE_FF" rev="1">
<attrib name="value" value="32"/></item>
<item name="NUM_SLICE_UNUSEDCTRL" rev="1">
<attrib name="value" value="1"/></item>
<item name="NUM_UNUSABLE_FF_BELS" rev="1">
<item name="NUM_SLICE_CONTROLSET" rev="7">
<attrib name="value" value="8"/></item>
<item name="NUM_SLICE_CYINIT" rev="7">
<attrib name="value" value="174"/></item>
<item name="NUM_SLICE_FF" rev="7">
<attrib name="value" value="81"/></item>
<item name="NUM_SLICE_UNUSEDCTRL" rev="7">
<attrib name="value" value="11"/></item>
<item name="NUM_UNUSABLE_FF_BELS" rev="7">
<attrib name="value" value="31"/></item>
</group>
</DesignStatistics>
<DeviceUsage TimeStamp="Wed Jun 08 11:36:13 2022"><group name="SiteSummary">
<item name="BUFG" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="BUFG_BUFG" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="CARRY4" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="5"/></item>
<item name="FF_SR" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="HARD0" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="IOB" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="17"/></item>
<item name="IOB_IMUX" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="14"/></item>
<item name="IOB_INBUF" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="14"/></item>
<item name="IOB_OUTBUF" rev="2">
<DeviceUsage TimeStamp="Wed Jun 08 12:43:41 2022"><group name="SiteSummary">
<item name="BUFG" rev="8">
<attrib name="total" value="1000000"/><attrib name="used" value="3"/></item>
<item name="LUT5" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="15"/></item>
<item name="LUT6" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="31"/></item>
<item name="PAD" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="17"/></item>
<item name="REG_SR" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="30"/></item>
<item name="SLICEL" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="5"/></item>
<item name="SLICEX" rev="2">
<item name="BUFG_BUFG" rev="8">
<attrib name="total" value="1000000"/><attrib name="used" value="3"/></item>
<item name="CARRY4" rev="8">
<attrib name="total" value="1000000"/><attrib name="used" value="11"/></item>
<item name="FF_SR" rev="8">
<attrib name="total" value="1000000"/><attrib name="used" value="6"/></item>
<item name="HARD0" rev="8">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="HARD1" rev="8">
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="IOB" rev="8">
<attrib name="total" value="1000000"/><attrib name="used" value="21"/></item>
<item name="IOB_IMUX" rev="8">
<attrib name="total" value="1000000"/><attrib name="used" value="14"/></item>
<item name="IOB_INBUF" rev="8">
<attrib name="total" value="1000000"/><attrib name="used" value="14"/></item>
<item name="IOB_OUTBUF" rev="8">
<attrib name="total" value="1000000"/><attrib name="used" value="7"/></item>
<item name="LUT5" rev="8">
<attrib name="total" value="1000000"/><attrib name="used" value="42"/></item>
<item name="LUT6" rev="8">
<attrib name="total" value="1000000"/><attrib name="used" value="129"/></item>
<item name="PAD" rev="8">
<attrib name="total" value="1000000"/><attrib name="used" value="21"/></item>
<item name="REG_SR" rev="8">
<attrib name="total" value="1000000"/><attrib name="used" value="75"/></item>
<item name="SLICEL" rev="8">
<attrib name="total" value="1000000"/><attrib name="used" value="11"/></item>
<item name="SLICEX" rev="8">
<attrib name="total" value="1000000"/><attrib name="used" value="30"/></item>
</group>
</DeviceUsage>
<ReportConfigData TimeStamp="Wed Jun 08 11:36:13 2022"><group name="REG_SR">
<item name="CK" rev="2">
<attrib name="CK" value="6"/><attrib name="CK_INV" value="24"/></item>
<item name="LATCH_OR_FF" rev="2">
<attrib name="FF" value="30"/></item>
<item name="SRINIT" rev="2">
<attrib name="SRINIT0" value="30"/></item>
<item name="SYNC_ATTR" rev="2">
<attrib name="ASYNC" value="30"/></item>
<ReportConfigData TimeStamp="Wed Jun 08 12:43:41 2022"><group name="REG_SR">
<item name="CK" rev="8">
<attrib name="CK" value="52"/><attrib name="CK_INV" value="23"/></item>
<item name="LATCH_OR_FF" rev="8">
<attrib name="FF" value="75"/></item>
<item name="SRINIT" rev="8">
<attrib name="SRINIT0" value="75"/></item>
<item name="SYNC_ATTR" rev="8">
<attrib name="ASYNC" value="64"/><attrib name="SYNC" value="11"/></item>
</group>
<group name="SLICEL">
<item name="CLK" rev="2">
<item name="CLK" rev="8">
<attrib name="CLK" value="2"/><attrib name="CLK_INV" value="3"/></item>
</group>
<group name="IOB_OUTBUF">
<item name="DRIVEATTRBOX" rev="2">
<attrib name="12" value="3"/></item>
<item name="SLEW" rev="2">
<attrib name="SLOW" value="3"/></item>
<item name="SUSPEND" rev="2">
<attrib name="3STATE" value="3"/></item>
<item name="DRIVEATTRBOX" rev="8">
<attrib name="12" value="7"/></item>
<item name="SLEW" rev="8">
<attrib name="SLOW" value="7"/></item>
<item name="SUSPEND" rev="8">
<attrib name="3STATE" value="7"/></item>
</group>
<group name="SLICEX">
<item name="CLK" rev="2">
<attrib name="CLK" value="0"/><attrib name="CLK_INV" value="5"/></item>
<item name="CLK" rev="8">
<attrib name="CLK" value="21"/><attrib name="CLK_INV" value="4"/></item>
</group>
<group name="FF_SR">
<item name="CK" rev="2">
<attrib name="CK" value="0"/><attrib name="CK_INV" value="2"/></item>
<item name="SRINIT" rev="2">
<attrib name="SRINIT0" value="2"/></item>
<item name="SYNC_ATTR" rev="2">
<attrib name="ASYNC" value="2"/></item>
<item name="CK" rev="8">
<attrib name="CK" value="3"/><attrib name="CK_INV" value="3"/></item>
<item name="SRINIT" rev="8">
<attrib name="SRINIT0" value="6"/></item>
<item name="SYNC_ATTR" rev="8">
<attrib name="ASYNC" value="4"/><attrib name="SYNC" value="2"/></item>
</group>
</ReportConfigData>
<ReportPinData TimeStamp="Wed Jun 08 11:36:13 2022"><group name="REG_SR">
<item name="CK" rev="2">
<attrib name="value" value="30"/></item>
<item name="D" rev="2">
<attrib name="value" value="30"/></item>
<item name="Q" rev="2">
<attrib name="value" value="30"/></item>
<ReportPinData TimeStamp="Wed Jun 08 12:43:41 2022"><group name="REG_SR">
<item name="CE" rev="8">
<attrib name="value" value="17"/></item>
<item name="CK" rev="8">
<attrib name="value" value="75"/></item>
<item name="D" rev="8">
<attrib name="value" value="75"/></item>
<item name="Q" rev="8">
<attrib name="value" value="75"/></item>
<item name="SR" rev="8">
<attrib name="value" value="28"/></item>
</group>
<group name="SLICEL">
<item name="A4" rev="2">
<item name="A4" rev="8">
<attrib name="value" value="5"/></item>
<item name="A6" rev="2">
<attrib name="value" value="4"/></item>
<item name="AQ" rev="2">
<item name="A5" rev="8">
<attrib name="value" value="6"/></item>
<item name="A6" rev="8">
<attrib name="value" value="10"/></item>
<item name="AMUX" rev="8">
<attrib name="value" value="6"/></item>
<item name="AQ" rev="8">
<attrib name="value" value="5"/></item>
<item name="B4" rev="2">
<item name="B4" rev="8">
<attrib name="value" value="4"/></item>
<item name="B6" rev="2">
<attrib name="value" value="3"/></item>
<item name="BQ" rev="2">
<item name="B5" rev="8">
<attrib name="value" value="6"/></item>
<item name="B6" rev="8">
<attrib name="value" value="9"/></item>
<item name="BMUX" rev="8">
<attrib name="value" value="6"/></item>
<item name="BQ" rev="8">
<attrib name="value" value="4"/></item>
<item name="C4" rev="2">
<item name="C4" rev="8">
<attrib name="value" value="3"/></item>
<item name="C6" rev="2">
<attrib name="value" value="3"/></item>
<item name="CIN" rev="2">
<attrib name="value" value="3"/></item>
<item name="CLK" rev="2">
<item name="C5" rev="8">
<attrib name="value" value="6"/></item>
<item name="C6" rev="8">
<attrib name="value" value="9"/></item>
<item name="CIN" rev="8">
<attrib name="value" value="8"/></item>
<item name="CLK" rev="8">
<attrib name="value" value="5"/></item>
<item name="COUT" rev="2">
<item name="CMUX" rev="8">
<attrib name="value" value="6"/></item>
<item name="COUT" rev="8">
<attrib name="value" value="8"/></item>
<item name="CQ" rev="8">
<attrib name="value" value="3"/></item>
<item name="CQ" rev="2">
<item name="D4" rev="8">
<attrib name="value" value="3"/></item>
<item name="D4" rev="2">
<attrib name="value" value="3"/></item>
<item name="D6" rev="2">
<attrib name="value" value="3"/></item>
<item name="DQ" rev="2">
<item name="D5" rev="8">
<attrib name="value" value="5"/></item>
<item name="D6" rev="8">
<attrib name="value" value="9"/></item>
<item name="DMUX" rev="8">
<attrib name="value" value="6"/></item>
<item name="DQ" rev="8">
<attrib name="value" value="3"/></item>
</group>
<group name="IOB_OUTBUF">
<item name="IN" rev="2">
<attrib name="value" value="3"/></item>
<item name="OUT" rev="2">
<attrib name="value" value="3"/></item>
<item name="IN" rev="8">
<attrib name="value" value="7"/></item>
<item name="OUT" rev="8">
<attrib name="value" value="7"/></item>
</group>
<group name="SLICEX">
<item name="A" rev="2">
<attrib name="value" value="1"/></item>
<item name="A2" rev="2">
<attrib name="value" value="2"/></item>
<item name="A3" rev="2">
<attrib name="value" value="3"/></item>
<item name="A4" rev="2">
<attrib name="value" value="5"/></item>
<item name="A5" rev="2">
<attrib name="value" value="4"/></item>
<item name="A6" rev="2">
<item name="A" rev="8">
<attrib name="value" value="6"/></item>
<item name="AMUX" rev="2">
<attrib name="value" value="1"/></item>
<item name="AQ" rev="2">
<attrib name="value" value="5"/></item>
<item name="B1" rev="2">
<attrib name="value" value="1"/></item>
<item name="B2" rev="2">
<item name="A1" rev="8">
<attrib name="value" value="10"/></item>
<item name="A2" rev="8">
<attrib name="value" value="19"/></item>
<item name="A3" rev="8">
<attrib name="value" value="20"/></item>
<item name="A4" rev="8">
<attrib name="value" value="23"/></item>
<item name="A5" rev="8">
<attrib name="value" value="22"/></item>
<item name="A6" rev="8">
<attrib name="value" value="23"/></item>
<item name="AMUX" rev="8">
<attrib name="value" value="2"/></item>
<item name="B3" rev="2">
<attrib name="value" value="4"/></item>
<item name="B4" rev="2">
<attrib name="value" value="4"/></item>
<item name="B5" rev="2">
<attrib name="value" value="4"/></item>
<item name="B6" rev="2">
<attrib name="value" value="4"/></item>
<item name="BMUX" rev="2">
<item name="AQ" rev="8">
<attrib name="value" value="20"/></item>
<item name="AX" rev="8">
<attrib name="value" value="1"/></item>
<item name="BQ" rev="2">
<attrib name="value" value="4"/></item>
<item name="C1" rev="2">
<attrib name="value" value="2"/></item>
<item name="C2" rev="2">
<attrib name="value" value="3"/></item>
<item name="C3" rev="2">
<attrib name="value" value="3"/></item>
<item name="C4" rev="2">
<attrib name="value" value="3"/></item>
<item name="C5" rev="2">
<attrib name="value" value="3"/></item>
<item name="C6" rev="2">
<attrib name="value" value="3"/></item>
<item name="CLK" rev="2">
<attrib name="value" value="5"/></item>
<item name="CQ" rev="2">
<attrib name="value" value="3"/></item>
<item name="D1" rev="2">
<attrib name="value" value="2"/></item>
<item name="D2" rev="2">
<attrib name="value" value="3"/></item>
<item name="D3" rev="2">
<attrib name="value" value="3"/></item>
<item name="D4" rev="2">
<attrib name="value" value="3"/></item>
<item name="D5" rev="2">
<attrib name="value" value="3"/></item>
<item name="D6" rev="2">
<attrib name="value" value="3"/></item>
<item name="DQ" rev="2">
<item name="B" rev="8">
<attrib name="value" value="11"/></item>
<item name="B1" rev="8">
<attrib name="value" value="7"/></item>
<item name="B2" rev="8">
<attrib name="value" value="15"/></item>
<item name="B3" rev="8">
<attrib name="value" value="16"/></item>
<item name="B4" rev="8">
<attrib name="value" value="20"/></item>
<item name="B5" rev="8">
<attrib name="value" value="21"/></item>
<item name="B6" rev="8">
<attrib name="value" value="22"/></item>
<item name="BMUX" rev="8">
<attrib name="value" value="1"/></item>
<item name="BQ" rev="8">
<attrib name="value" value="13"/></item>
<item name="BX" rev="8">
<attrib name="value" value="1"/></item>
<item name="C" rev="8">
<attrib name="value" value="6"/></item>
<item name="C1" rev="8">
<attrib name="value" value="7"/></item>
<item name="C2" rev="8">
<attrib name="value" value="20"/></item>
<item name="C3" rev="8">
<attrib name="value" value="21"/></item>
<item name="C4" rev="8">
<attrib name="value" value="22"/></item>
<item name="C5" rev="8">
<attrib name="value" value="22"/></item>
<item name="C6" rev="8">
<attrib name="value" value="22"/></item>
<item name="CE" rev="8">
<attrib name="value" value="10"/></item>
<item name="CLK" rev="8">
<attrib name="value" value="25"/></item>
<item name="CMUX" rev="8">
<attrib name="value" value="3"/></item>
<item name="CQ" rev="8">
<attrib name="value" value="16"/></item>
<item name="D" rev="8">
<attrib name="value" value="11"/></item>
<item name="D1" rev="8">
<attrib name="value" value="7"/></item>
<item name="D2" rev="8">
<attrib name="value" value="17"/></item>
<item name="D3" rev="8">
<attrib name="value" value="20"/></item>
<item name="D4" rev="8">
<attrib name="value" value="21"/></item>
<item name="D5" rev="8">
<attrib name="value" value="20"/></item>
<item name="D6" rev="8">
<attrib name="value" value="20"/></item>
<item name="DQ" rev="8">
<attrib name="value" value="11"/></item>
<item name="DX" rev="8">
<attrib name="value" value="1"/></item>
<item name="SR" rev="8">
<attrib name="value" value="13"/></item>
</group>
<group name="BUFG_BUFG">
<item name="I0" rev="2">
<attrib name="value" value="2"/></item>
<item name="O" rev="2">
<attrib name="value" value="2"/></item>
<item name="I0" rev="8">
<attrib name="value" value="3"/></item>
<item name="O" rev="8">
<attrib name="value" value="3"/></item>
</group>
<group name="PAD">
<item name="PAD" rev="2">
<attrib name="value" value="17"/></item>
<item name="PAD" rev="8">
<attrib name="value" value="21"/></item>
</group>
<group name="IOB_INBUF">
<item name="OUT" rev="2">
<item name="OUT" rev="8">
<attrib name="value" value="14"/></item>
<item name="PAD" rev="2">
<item name="PAD" rev="8">
<attrib name="value" value="14"/></item>
</group>
<group name="CARRY4">
<item name="CIN" rev="2">
<attrib name="value" value="3"/></item>
<item name="CO3" rev="2">
<attrib name="value" value="3"/></item>
<item name="CYINIT" rev="2">
<attrib name="value" value="2"/></item>
<item name="DI0" rev="2">
<attrib name="value" value="4"/></item>
<item name="DI1" rev="2">
<attrib name="value" value="3"/></item>
<item name="DI2" rev="2">
<attrib name="value" value="3"/></item>
<item name="DI3" rev="2">
<attrib name="value" value="3"/></item>
<item name="O0" rev="2">
<attrib name="value" value="5"/></item>
<item name="O1" rev="2">
<attrib name="value" value="4"/></item>
<item name="O2" rev="2">
<attrib name="value" value="3"/></item>
<item name="O3" rev="2">
<attrib name="value" value="3"/></item>
<item name="S0" rev="2">
<attrib name="value" value="5"/></item>
<item name="S1" rev="2">
<attrib name="value" value="4"/></item>
<item name="S2" rev="2">
<attrib name="value" value="3"/></item>
<item name="S3" rev="2">
<item name="CIN" rev="8">
<attrib name="value" value="8"/></item>
<item name="CO3" rev="8">
<attrib name="value" value="8"/></item>
<item name="CYINIT" rev="8">
<attrib name="value" value="3"/></item>
<item name="DI0" rev="8">
<attrib name="value" value="10"/></item>
<item name="DI1" rev="8">
<attrib name="value" value="9"/></item>
<item name="DI2" rev="8">
<attrib name="value" value="9"/></item>
<item name="DI3" rev="8">
<attrib name="value" value="8"/></item>
<item name="O0" rev="8">
<attrib name="value" value="11"/></item>
<item name="O1" rev="8">
<attrib name="value" value="10"/></item>
<item name="O2" rev="8">
<attrib name="value" value="9"/></item>
<item name="O3" rev="8">
<attrib name="value" value="9"/></item>
<item name="S0" rev="8">
<attrib name="value" value="11"/></item>
<item name="S1" rev="8">
<attrib name="value" value="10"/></item>
<item name="S2" rev="8">
<attrib name="value" value="9"/></item>
<item name="S3" rev="8">
<attrib name="value" value="9"/></item>
</group>
<group name="LUT5">
<item name="A3" rev="2">
<attrib name="value" value="2"/></item>
<item name="A5" rev="2">
<attrib name="value" value="2"/></item>
<item name="O5" rev="2">
<attrib name="value" value="15"/></item>
<item name="A1" rev="8">
<attrib name="value" value="3"/></item>
<item name="A2" rev="8">
<attrib name="value" value="4"/></item>
<item name="A3" rev="8">
<attrib name="value" value="6"/></item>
<item name="A4" rev="8">
<attrib name="value" value="6"/></item>
<item name="A5" rev="8">
<attrib name="value" value="3"/></item>
<item name="O5" rev="8">
<attrib name="value" value="42"/></item>
</group>
<group name="LUT6">
<item name="A1" rev="2">
<attrib name="value" value="5"/></item>
<item name="A2" rev="2">
<attrib name="value" value="10"/></item>
<item name="A3" rev="2">
<attrib name="value" value="11"/></item>
<item name="A4" rev="2">
<attrib name="value" value="30"/></item>
<item name="A5" rev="2">
<attrib name="value" value="14"/></item>
<item name="A6" rev="2">
<item name="A1" rev="8">
<attrib name="value" value="29"/></item>
<item name="O6" rev="2">
<attrib name="value" value="31"/></item>
<item name="A2" rev="8">
<attrib name="value" value="68"/></item>
<item name="A3" rev="8">
<attrib name="value" value="76"/></item>
<item name="A4" rev="8">
<attrib name="value" value="99"/></item>
<item name="A5" rev="8">
<attrib name="value" value="108"/></item>
<item name="A6" rev="8">
<attrib name="value" value="124"/></item>
<item name="O6" rev="8">
<attrib name="value" value="129"/></item>
</group>
<group name="IOB_IMUX">
<item name="I" rev="2">
<item name="I" rev="8">
<attrib name="value" value="14"/></item>
<item name="OUT" rev="2">
<item name="OUT" rev="8">
<attrib name="value" value="14"/></item>
</group>
<group name="IOB">
<item name="I" rev="2">
<item name="I" rev="8">
<attrib name="value" value="14"/></item>
<item name="O" rev="2">
<attrib name="value" value="3"/></item>
<item name="PAD" rev="2">
<attrib name="value" value="17"/></item>
<item name="O" rev="8">
<attrib name="value" value="7"/></item>
<item name="PAD" rev="8">
<attrib name="value" value="21"/></item>
</group>
<group name="HARD0">
<item name="0" rev="2">
<item name="0" rev="8">
<attrib name="value" value="2"/></item>
</group>
<group name="HARD1">
<item name="1" rev="8">
<attrib name="value" value="1"/></item>
</group>
<group name="FF_SR">
<item name="CK" rev="2">
<attrib name="value" value="2"/></item>
<item name="D" rev="2">
<attrib name="value" value="2"/></item>
<item name="Q" rev="2">
<attrib name="value" value="2"/></item>
<item name="CE" rev="8">
<attrib name="value" value="3"/></item>
<item name="CK" rev="8">
<attrib name="value" value="6"/></item>
<item name="D" rev="8">
<attrib name="value" value="6"/></item>
<item name="Q" rev="8">
<attrib name="value" value="6"/></item>
<item name="SR" rev="8">
<attrib name="value" value="5"/></item>
</group>
<group name="BUFG">
<item name="I0" rev="2">
<attrib name="value" value="2"/></item>
<item name="O" rev="2">
<attrib name="value" value="2"/></item>
<item name="I0" rev="8">
<attrib name="value" value="3"/></item>
<item name="O" rev="8">
<attrib name="value" value="3"/></item>
</group>
</ReportPinData>
<CmdHistory>

98
textovhdl_xst.xrpt
View File

@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Wed Jun 08 11:34:37 2022">
<application stringID="Xst" timeStamp="Wed Jun 08 12:42:31 2022">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@@ -103,34 +103,42 @@
</section>
<section stringID="XST_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_RAMS" value="1"></item>
<item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="2"></item>
<item dataType="int" stringID="XST_REGISTERS" value="4">
<item dataType="int" stringID="XST_1BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="8">
<item dataType="int" stringID="XST_4BIT_ADDER" value="5"/>
</item>
<item dataType="int" stringID="XST_REGISTERS" value="13">
<item dataType="int" stringID="XST_1BIT_REGISTER" value="2"/>
<item dataType="int" stringID="XST_16BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_2BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_4BIT_REGISTER" value="6"/>
<item dataType="int" stringID="XST_9BIT_REGISTER" value="1"/>
</item>
<item dataType="int" stringID="XST_MULTIPLEXERS" value="4">
<item dataType="int" stringID="XST_MULTIPLEXERS" value="19">
<item dataType="int" stringID="XST_1BIT_2TO1_MULTIPLEXER" value="5"/>
<item dataType="int" stringID="XST_16BIT_2TO1_MULTIPLEXER" value="4"/>
</item>
<item dataType="int" stringID="XST_TRISTATES" value="4">
<item dataType="int" stringID="XST_1BIT_TRISTATE_BUFFER" value="4"/>
<item dataType="int" stringID="XST_4BIT_2TO1_MULTIPLEXER" value="10"/>
</item>
</section>
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_RAMS" value="1"></item>
<item dataType="int" stringID="XST_COUNTERS" value="2">
<item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="5">
<item dataType="int" stringID="XST_4BIT_ADDER" value="5"/>
</item>
<item dataType="int" stringID="XST_COUNTERS" value="3">
<item dataType="int" stringID="XST_9BIT_UP_COUNTER" value="1"/>
</item>
<item dataType="int" stringID="XST_REGISTERS" value="17">
<item dataType="int" stringID="XST_FLIPFLOPS" value="17"/>
<item dataType="int" stringID="XST_REGISTERS" value="41">
<item dataType="int" stringID="XST_FLIPFLOPS" value="41"/>
</item>
<item dataType="int" stringID="XST_MULTIPLEXERS" value="4">
<item dataType="int" stringID="XST_MULTIPLEXERS" value="19">
<item dataType="int" stringID="XST_1BIT_2TO1_MULTIPLEXER" value="5"/>
<item dataType="int" stringID="XST_16BIT_2TO1_MULTIPLEXER" value="4"/>
<item dataType="int" stringID="XST_4BIT_2TO1_MULTIPLEXER" value="10"/>
</item>
</section>
<section stringID="XST_FINAL_REGISTER_REPORT">
<item dataType="int" stringID="XST_REGISTERS" value="32">
<item dataType="int" stringID="XST_FLIPFLOPS" value="32"/>
<item dataType="int" stringID="XST_REGISTERS" value="81">
<item dataType="int" stringID="XST_FLIPFLOPS" value="81"/>
</item>
</section>
<section stringID="XST_PARTITION_REPORT">
@@ -143,54 +151,56 @@
<item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="textovhdl.ngc"/>
</section>
<section stringID="XST_PRIMITIVE_AND_BLACK_BOX_USAGE">
<item dataType="int" stringID="XST_BELS" value="64">
<item dataType="int" stringID="XST_BELS" value="213">
<item dataType="int" stringID="XST_GND" value="1"/>
<item dataType="int" stringID="XST_INV" value="4"/>
<item dataType="int" stringID="XST_LUT1" value="13"/>
<item dataType="int" stringID="XST_LUT2" value="5"/>
<item dataType="int" stringID="XST_LUT3" value="1"/>
<item dataType="int" stringID="XST_LUT4" value="1"/>
<item dataType="int" stringID="XST_LUT5" value="5"/>
<item dataType="int" stringID="XST_LUT6" value="5"/>
<item dataType="int" stringID="XST_MUXCY" value="13"/>
<item dataType="int" stringID="XST_INV" value="31"/>
<item dataType="int" stringID="XST_LUT1" value="14"/>
<item dataType="int" stringID="XST_LUT2" value="7"/>
<item dataType="int" stringID="XST_LUT3" value="9"/>
<item dataType="int" stringID="XST_LUT4" value="4"/>
<item dataType="int" stringID="XST_LUT5" value="43"/>
<item dataType="int" stringID="XST_LUT6" value="28"/>
<item dataType="int" stringID="XST_MUXCY" value="36"/>
<item dataType="int" stringID="XST_VCC" value="1"/>
<item dataType="int" stringID="XST_XORCY" value="15"/>
<item dataType="int" stringID="XST_XORCY" value="39"/>
</item>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="32">
<item dataType="int" stringID="XST_FD" value="15"/>
<item dataType="int" stringID="XST_FD1" value="17"/>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="81">
<item dataType="int" stringID="XST_FD" value="44"/>
<item dataType="int" stringID="XST_FD1" value="4"/>
<item dataType="int" stringID="XST_FDCE" value="20"/>
<item dataType="int" stringID="XST_FDR1" value="13"/>
</item>
<item dataType="int" stringID="XST_CLOCK_BUFFERS" value="2">
<item dataType="int" label="-bufg" stringID="XST_BUFG" value="1"/>
<item dataType="int" stringID="XST_CLOCK_BUFFERS" value="3">
<item dataType="int" label="-bufg" stringID="XST_BUFG" value="2"/>
<item dataType="int" stringID="XST_BUFGP" value="1"/>
</item>
<item dataType="int" stringID="XST_IO_BUFFERS" value="7">
<item dataType="int" stringID="XST_OBUF" value="3"/>
<item dataType="int" stringID="XST_OBUFT" value="4"/>
<item dataType="int" stringID="XST_IO_BUFFERS" value="8">
<item dataType="int" stringID="XST_IBUF" value="1"/>
<item dataType="int" stringID="XST_OBUF" value="7"/>
</item>
</section>
</section>
<section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
<item stringID="XST_SELECTED_DEVICE" value="6slx16csg324-2"/>
<item AVAILABLE="18224" dataType="int" label="Number of Slice Registers" stringID="XST_NUMBER_OF_SLICE_REGISTERS" value="32"/>
<item AVAILABLE="9112" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="34"/>
<item AVAILABLE="9112" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="34"/>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="34"/>
<item AVAILABLE="34" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="2"/>
<item AVAILABLE="34" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="0"/>
<item AVAILABLE="34" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="32"/>
<item dataType="int" label="Number of unique control sets" stringID="XST_NUMBER_OF_UNIQUE_CONTROL_SETS" value="3"/>
<item AVAILABLE="18224" dataType="int" label="Number of Slice Registers" stringID="XST_NUMBER_OF_SLICE_REGISTERS" value="81"/>
<item AVAILABLE="9112" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="136"/>
<item AVAILABLE="9112" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="136"/>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="138"/>
<item AVAILABLE="138" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="57"/>
<item AVAILABLE="138" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="2"/>
<item AVAILABLE="138" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="79"/>
<item dataType="int" label="Number of unique control sets" stringID="XST_NUMBER_OF_UNIQUE_CONTROL_SETS" value="9"/>
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="21"/>
<item AVAILABLE="232" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="8"/>
<item AVAILABLE="16" dataType="int" label="Number of BUFG/BUFGCTRLs" stringID="XST_NUMBER_OF_BUFGBUFGCTRLS" value="2"/>
<item AVAILABLE="232" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="9"/>
<item AVAILABLE="16" dataType="int" label="Number of BUFG/BUFGCTRLs" stringID="XST_NUMBER_OF_BUFGBUFGCTRLS" value="3"/>
</section>
<section stringID="XST_PARTITION_RESOURCE_SUMMARY">
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
</section>
<section stringID="XST_ERRORS_STATISTICS">
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="32"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="1"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="38"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="3"/>
</section>
</application>

479
usage_statistics_webtalk.html
View File

@@ -17,7 +17,7 @@
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project ID (random number)</B></TD>
<TD><xtag-property name="RandomID">bd16c3ee05c44948bef10dae3c70184a</xtag-property>.<xtag-property name="ProjectID">047E6D81914F4B9E9C732FAABBF95C82</xtag-property>.<xtag-property name="ProjectIteration">1</xtag-property></TD>
<TD><xtag-property name="RandomID">bd16c3ee05c44948bef10dae3c70184a</xtag-property>.<xtag-property name="ProjectID">047E6D81914F4B9E9C732FAABBF95C82</xtag-property>.<xtag-property name="ProjectIteration">4</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Package:</B></TD>
<TD><xtag-property name="TargetPackage">csg324</xtag-property></TD>
</TR>
@@ -29,7 +29,7 @@
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Date Generated</B></TD>
<TD><xtag-property name="Date Generated">2022-06-08T11:36:14</xtag-property></TD>
<TD><xtag-property name="Date Generated">2022-06-08T12:43:42</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Tool Flow</B></TD>
<TD><xtag-property name="ToolFlow">ISE</xtag-property></TD>
</TR>
@@ -67,15 +67,23 @@
<TR ALIGN=CENTER BGCOLOR='#FFFF99'><TD><B>Macro Statistics</B></TD><TD><B>Miscellaneous Statistics</B></TD><TD><B>Net Statistics</B></TD><TD><B>Site Usage</B></TD></TR><TR VALIGN=TOP>
<xtag-section name="MacroStatistics">
<TD>
<xtag-group><xtag-group-name name="Counters=2">Counters=2</xtag-group-name>
<xtag-group><xtag-group-name name="Adders/Subtractors=5">Adders/Subtractors=5</xtag-group-name>
<UL>
<LI><xtag-item1>4-bit adder=5</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="Counters=3">Counters=3</xtag-group-name>
<UL>
<LI><xtag-item1>24-bit down counter=1</xtag-item1></LI>
<LI><xtag-item1>24-bit up counter=1</xtag-item1></LI>
<LI><xtag-item1>9-bit up counter=1</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="Multiplexers=4">Multiplexers=4</xtag-group-name>
<xtag-group><xtag-group-name name="Multiplexers=19">Multiplexers=19</xtag-group-name>
<UL>
<LI><xtag-item1>1-bit 2-to-1 multiplexer=5</xtag-item1></LI>
<LI><xtag-item1>16-bit 2-to-1 multiplexer=4</xtag-item1></LI>
<LI><xtag-item1>4-bit 2-to-1 multiplexer=10</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="RAMs=1">RAMs=1</xtag-group-name>
@@ -83,9 +91,9 @@
<LI><xtag-item1>8x4-bit single-port distributed Read Only RAM=1</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="Registers=17">Registers=17</xtag-group-name>
<xtag-group><xtag-group-name name="Registers=41">Registers=41</xtag-group-name>
<UL>
<LI><xtag-item1>Flip-Flops=17</xtag-item1></LI>
<LI><xtag-item1>Flip-Flops=41</xtag-item1></LI>
</UL>
</xtag-group>
</TD>
@@ -94,72 +102,75 @@
<TD>
<xtag-group><xtag-group-name name="MiscellaneousStatistics">MiscellaneousStatistics</xtag-group-name>
<UL>
<LI><xtag-item1>AGG_BONDED_IO=17</xtag-item1></LI>
<LI><xtag-item1>AGG_IO=17</xtag-item1></LI>
<LI><xtag-item1>AGG_LOCED_IO=17</xtag-item1></LI>
<LI><xtag-item1>AGG_SLICE=11</xtag-item1></LI>
<LI><xtag-item1>NUM_BONDED_IOB=17</xtag-item1></LI>
<LI><xtag-item1>NUM_BSFULL=30</xtag-item1></LI>
<LI><xtag-item1>NUM_BSLUTONLY=1</xtag-item1></LI>
<LI><xtag-item1>NUM_BSUSED=31</xtag-item1></LI>
<LI><xtag-item1>NUM_BUFG=2</xtag-item1></LI>
<LI><xtag-item1>NUM_LOCED_IOB=17</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O5ANDO6=4</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O5ONLY=11</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O6ONLY=14</xtag-item1></LI>
<LI><xtag-item1>AGG_BONDED_IO=21</xtag-item1></LI>
<LI><xtag-item1>AGG_IO=21</xtag-item1></LI>
<LI><xtag-item1>AGG_LOCED_IO=21</xtag-item1></LI>
<LI><xtag-item1>AGG_SLICE=41</xtag-item1></LI>
<LI><xtag-item1>NUM_BONDED_IOB=21</xtag-item1></LI>
<LI><xtag-item1>NUM_BSFULL=73</xtag-item1></LI>
<LI><xtag-item1>NUM_BSLUTONLY=56</xtag-item1></LI>
<LI><xtag-item1>NUM_BSREGONLY=3</xtag-item1></LI>
<LI><xtag-item1>NUM_BSUSED=132</xtag-item1></LI>
<LI><xtag-item1>NUM_BUFG=3</xtag-item1></LI>
<LI><xtag-item1>NUM_LOCED_IOB=21</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O5ANDO6=30</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O5ONLY=12</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O6ONLY=85</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_DRIVES_CARRY4=2</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_EXO6=2</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_O6=11</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEL=5</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEX=6</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CARRY4=5</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CONTROLSET=2</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CYINIT=48</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_FF=32</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_UNUSEDCTRL=1</xtag-item1></LI>
<LI><xtag-item1>NUM_UNUSABLE_FF_BELS=8</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_O6=12</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEL=11</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEX=30</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CARRY4=11</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CONTROLSET=8</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CYINIT=174</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_FF=81</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_UNUSEDCTRL=11</xtag-item1></LI>
<LI><xtag-item1>NUM_UNUSABLE_FF_BELS=31</xtag-item1></LI>
</UL>
</xtag-group>
</TD>
<TD>
<xtag-group><xtag-group-name name="NetStatistics">NetStatistics</xtag-group-name>
<UL>
<LI><xtag-item1>NumNets_Active=69</xtag-item1></LI>
<LI><xtag-item1>NumNets_Active=185</xtag-item1></LI>
<LI><xtag-item1>NumNets_Vcc=1</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEACROSS=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEIN=6</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BUFGOUT=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BUFHINP2OUT=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=10</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPINFEED=6</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=8</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GENERIC=4</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=14</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_INPUT=5</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBIN2OUT=3</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBOUTPUT=3</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_LUTINPUT=86</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTBOUND=33</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=39</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PADINPUT=3</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PADOUTPUT=1</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINBOUNCE=19</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINFEED=102</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_QUAD=22</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_SINGLE=20</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_HVCCOUT=5</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_LUTINPUT=15</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PINFEED=15</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEACROSS=6</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEIN=24</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BUFGOUT=3</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BUFHINP2OUT=4</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=30</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPINFEED=12</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CNTRLPIN=23</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=95</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GENERIC=10</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=26</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_INPUT=11</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBIN2OUT=8</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBOUTPUT=8</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_LUTINPUT=470</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTBOUND=145</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=157</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PADINPUT=7</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PADOUTPUT=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINBOUNCE=75</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINFEED=525</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_QUAD=42</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_REGINPUT=3</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_SINGLE=237</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_HVCCOUT=13</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_LUTINPUT=42</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PINFEED=42</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SiteStatistics">SiteStatistics</xtag-group-name>
<UL>
<LI><xtag-item1>BUFG-BUFGMUX=2</xtag-item1></LI>
<LI><xtag-item1>BUFG-BUFGMUX=3</xtag-item1></LI>
<LI><xtag-item1>IOB-IOBM=10</xtag-item1></LI>
<LI><xtag-item1>IOB-IOBS=7</xtag-item1></LI>
<LI><xtag-item1>SLICEL-SLICEM=2</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEL=1</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEM=2</xtag-item1></LI>
<LI><xtag-item1>IOB-IOBS=11</xtag-item1></LI>
<LI><xtag-item1>SLICEL-SLICEM=11</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEL=10</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEM=6</xtag-item1></LI>
</UL>
</xtag-group>
</TD>
@@ -168,21 +179,22 @@
<TD>
<xtag-group><xtag-group-name name="SiteSummary">SiteSummary</xtag-group-name>
<UL>
<LI><xtag-item2>BUFG=2</xtag-item2></LI>
<LI><xtag-item2>BUFG_BUFG=2</xtag-item2></LI>
<LI><xtag-item2>CARRY4=5</xtag-item2></LI>
<LI><xtag-item2>FF_SR=2</xtag-item2></LI>
<LI><xtag-item2>BUFG=3</xtag-item2></LI>
<LI><xtag-item2>BUFG_BUFG=3</xtag-item2></LI>
<LI><xtag-item2>CARRY4=11</xtag-item2></LI>
<LI><xtag-item2>FF_SR=6</xtag-item2></LI>
<LI><xtag-item2>HARD0=2</xtag-item2></LI>
<LI><xtag-item2>IOB=17</xtag-item2></LI>
<LI><xtag-item2>HARD1=1</xtag-item2></LI>
<LI><xtag-item2>IOB=21</xtag-item2></LI>
<LI><xtag-item2>IOB_IMUX=14</xtag-item2></LI>
<LI><xtag-item2>IOB_INBUF=14</xtag-item2></LI>
<LI><xtag-item2>IOB_OUTBUF=3</xtag-item2></LI>
<LI><xtag-item2>LUT5=15</xtag-item2></LI>
<LI><xtag-item2>LUT6=31</xtag-item2></LI>
<LI><xtag-item2>PAD=17</xtag-item2></LI>
<LI><xtag-item2>REG_SR=30</xtag-item2></LI>
<LI><xtag-item2>SLICEL=5</xtag-item2></LI>
<LI><xtag-item2>SLICEX=6</xtag-item2></LI>
<LI><xtag-item2>IOB_OUTBUF=7</xtag-item2></LI>
<LI><xtag-item2>LUT5=42</xtag-item2></LI>
<LI><xtag-item2>LUT6=129</xtag-item2></LI>
<LI><xtag-item2>PAD=21</xtag-item2></LI>
<LI><xtag-item2>REG_SR=75</xtag-item2></LI>
<LI><xtag-item2>SLICEL=11</xtag-item2></LI>
<LI><xtag-item2>SLICEX=30</xtag-item2></LI>
</UL>
</xtag-group>
</TD>
@@ -194,28 +206,28 @@
<TD>
<xtag-group><xtag-group-name name="FF_SR">FF_SR</xtag-group-name>
<UL>
<LI><xtag-item3>CK=[CK:0] [CK_INV:2]</xtag-item3></LI>
<LI><xtag-item3>SRINIT=[SRINIT0:2]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:2]</xtag-item3></LI>
<LI><xtag-item3>CK=[CK:3] [CK_INV:3]</xtag-item3></LI>
<LI><xtag-item3>SRINIT=[SRINIT0:6]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:4] [SYNC:2]</xtag-item3></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="IOB_OUTBUF">IOB_OUTBUF</xtag-group-name>
<UL>
<LI><xtag-item3>DRIVEATTRBOX=[12:3]</xtag-item3></LI>
<LI><xtag-item3>SLEW=[SLOW:3]</xtag-item3></LI>
<LI><xtag-item3>SUSPEND=[3STATE:3]</xtag-item3></LI>
<LI><xtag-item3>DRIVEATTRBOX=[12:7]</xtag-item3></LI>
<LI><xtag-item3>SLEW=[SLOW:7]</xtag-item3></LI>
<LI><xtag-item3>SUSPEND=[3STATE:7]</xtag-item3></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name>
<UL>
<LI><xtag-item3>CK=[CK:6] [CK_INV:24]</xtag-item3></LI>
<LI><xtag-item3>LATCH_OR_FF=[FF:30]</xtag-item3></LI>
<LI><xtag-item3>SRINIT=[SRINIT0:30]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:30]</xtag-item3></LI>
<LI><xtag-item3>CK=[CK:52] [CK_INV:23]</xtag-item3></LI>
<LI><xtag-item3>LATCH_OR_FF=[FF:75]</xtag-item3></LI>
<LI><xtag-item3>SRINIT=[SRINIT0:75]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:64] [SYNC:11]</xtag-item3></LI>
</UL>
</TD>
<TD>
@@ -227,7 +239,7 @@
</xtag-group>
<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name>
<UL>
<LI><xtag-item3>CLK=[CLK:0] [CLK_INV:5]</xtag-item3></LI>
<LI><xtag-item3>CLK=[CLK:21] [CLK_INV:4]</xtag-item3></LI>
</UL>
</xtag-group>
</TD>
@@ -239,55 +251,62 @@
<TD>
<xtag-group><xtag-group-name name="BUFG">BUFG</xtag-group-name>
<UL>
<LI><xtag-item1>I0=2</xtag-item1></LI>
<LI><xtag-item1>O=2</xtag-item1></LI>
<LI><xtag-item1>I0=3</xtag-item1></LI>
<LI><xtag-item1>O=3</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="BUFG_BUFG">BUFG_BUFG</xtag-group-name>
<UL>
<LI><xtag-item1>I0=2</xtag-item1></LI>
<LI><xtag-item1>O=2</xtag-item1></LI>
<LI><xtag-item1>I0=3</xtag-item1></LI>
<LI><xtag-item1>O=3</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="CARRY4">CARRY4</xtag-group-name>
<UL>
<LI><xtag-item1>CIN=3</xtag-item1></LI>
<LI><xtag-item1>CO3=3</xtag-item1></LI>
<LI><xtag-item1>CYINIT=2</xtag-item1></LI>
<LI><xtag-item1>DI0=4</xtag-item1></LI>
<LI><xtag-item1>DI1=3</xtag-item1></LI>
<LI><xtag-item1>DI2=3</xtag-item1></LI>
<LI><xtag-item1>DI3=3</xtag-item1></LI>
<LI><xtag-item1>O0=5</xtag-item1></LI>
<LI><xtag-item1>O1=4</xtag-item1></LI>
<LI><xtag-item1>O2=3</xtag-item1></LI>
<LI><xtag-item1>O3=3</xtag-item1></LI>
<LI><xtag-item1>S0=5</xtag-item1></LI>
<LI><xtag-item1>S1=4</xtag-item1></LI>
<LI><xtag-item1>S2=3</xtag-item1></LI>
<LI><xtag-item1>S3=3</xtag-item1></LI>
<LI><xtag-item1>CIN=8</xtag-item1></LI>
<LI><xtag-item1>CO3=8</xtag-item1></LI>
<LI><xtag-item1>CYINIT=3</xtag-item1></LI>
<LI><xtag-item1>DI0=10</xtag-item1></LI>
<LI><xtag-item1>DI1=9</xtag-item1></LI>
<LI><xtag-item1>DI2=9</xtag-item1></LI>
<LI><xtag-item1>DI3=8</xtag-item1></LI>
<LI><xtag-item1>O0=11</xtag-item1></LI>
<LI><xtag-item1>O1=10</xtag-item1></LI>
<LI><xtag-item1>O2=9</xtag-item1></LI>
<LI><xtag-item1>O3=9</xtag-item1></LI>
<LI><xtag-item1>S0=11</xtag-item1></LI>
<LI><xtag-item1>S1=10</xtag-item1></LI>
<LI><xtag-item1>S2=9</xtag-item1></LI>
<LI><xtag-item1>S3=9</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="FF_SR">FF_SR</xtag-group-name>
<UL>
<LI><xtag-item1>CK=2</xtag-item1></LI>
<LI><xtag-item1>D=2</xtag-item1></LI>
<LI><xtag-item1>Q=2</xtag-item1></LI>
<LI><xtag-item1>CE=3</xtag-item1></LI>
<LI><xtag-item1>CK=6</xtag-item1></LI>
<LI><xtag-item1>D=6</xtag-item1></LI>
<LI><xtag-item1>Q=6</xtag-item1></LI>
<LI><xtag-item1>SR=5</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="HARD0">HARD0</xtag-group-name>
<UL>
<LI><xtag-item1>0=2</xtag-item1></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="HARD1">HARD1</xtag-group-name>
<UL>
<LI><xtag-item1>1=1</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOB">IOB</xtag-group-name>
<UL>
<LI><xtag-item1>I=14</xtag-item1></LI>
<LI><xtag-item1>O=3</xtag-item1></LI>
<LI><xtag-item1>PAD=17</xtag-item1></LI>
<LI><xtag-item1>O=7</xtag-item1></LI>
<LI><xtag-item1>PAD=21</xtag-item1></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="IOB_IMUX">IOB_IMUX</xtag-group-name>
<UL>
@@ -303,94 +322,117 @@
</xtag-group>
<xtag-group><xtag-group-name name="IOB_OUTBUF">IOB_OUTBUF</xtag-group-name>
<UL>
<LI><xtag-item1>IN=3</xtag-item1></LI>
<LI><xtag-item1>OUT=3</xtag-item1></LI>
<LI><xtag-item1>IN=7</xtag-item1></LI>
<LI><xtag-item1>OUT=7</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="LUT5">LUT5</xtag-group-name>
<UL>
<LI><xtag-item1>A3=2</xtag-item1></LI>
<LI><xtag-item1>A5=2</xtag-item1></LI>
<LI><xtag-item1>O5=15</xtag-item1></LI>
<LI><xtag-item1>A1=3</xtag-item1></LI>
<LI><xtag-item1>A2=4</xtag-item1></LI>
<LI><xtag-item1>A3=6</xtag-item1></LI>
<LI><xtag-item1>A4=6</xtag-item1></LI>
<LI><xtag-item1>A5=3</xtag-item1></LI>
<LI><xtag-item1>O5=42</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="LUT6">LUT6</xtag-group-name>
<UL>
<LI><xtag-item1>A1=5</xtag-item1></LI>
<LI><xtag-item1>A2=10</xtag-item1></LI>
<LI><xtag-item1>A3=11</xtag-item1></LI>
<LI><xtag-item1>A4=30</xtag-item1></LI>
<LI><xtag-item1>A5=14</xtag-item1></LI>
<LI><xtag-item1>A6=29</xtag-item1></LI>
<LI><xtag-item1>O6=31</xtag-item1></LI>
<LI><xtag-item1>A1=29</xtag-item1></LI>
<LI><xtag-item1>A2=68</xtag-item1></LI>
<LI><xtag-item1>A3=76</xtag-item1></LI>
<LI><xtag-item1>A4=99</xtag-item1></LI>
<LI><xtag-item1>A5=108</xtag-item1></LI>
<LI><xtag-item1>A6=124</xtag-item1></LI>
<LI><xtag-item1>O6=129</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="PAD">PAD</xtag-group-name>
<UL>
<LI><xtag-item1>PAD=17</xtag-item1></LI>
<LI><xtag-item1>PAD=21</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name>
<UL>
<LI><xtag-item1>CK=30</xtag-item1></LI>
<LI><xtag-item1>D=30</xtag-item1></LI>
<LI><xtag-item1>Q=30</xtag-item1></LI>
<LI><xtag-item1>CE=17</xtag-item1></LI>
<LI><xtag-item1>CK=75</xtag-item1></LI>
<LI><xtag-item1>D=75</xtag-item1></LI>
<LI><xtag-item1>Q=75</xtag-item1></LI>
<LI><xtag-item1>SR=28</xtag-item1></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name>
<UL>
<LI><xtag-item1>A4=5</xtag-item1></LI>
<LI><xtag-item1>A6=4</xtag-item1></LI>
<LI><xtag-item1>A5=6</xtag-item1></LI>
<LI><xtag-item1>A6=10</xtag-item1></LI>
<LI><xtag-item1>AMUX=6</xtag-item1></LI>
<LI><xtag-item1>AQ=5</xtag-item1></LI>
<LI><xtag-item1>B4=4</xtag-item1></LI>
<LI><xtag-item1>B6=3</xtag-item1></LI>
<LI><xtag-item1>B5=6</xtag-item1></LI>
<LI><xtag-item1>B6=9</xtag-item1></LI>
<LI><xtag-item1>BMUX=6</xtag-item1></LI>
<LI><xtag-item1>BQ=4</xtag-item1></LI>
<LI><xtag-item1>C4=3</xtag-item1></LI>
<LI><xtag-item1>C6=3</xtag-item1></LI>
<LI><xtag-item1>CIN=3</xtag-item1></LI>
<LI><xtag-item1>C5=6</xtag-item1></LI>
<LI><xtag-item1>C6=9</xtag-item1></LI>
<LI><xtag-item1>CIN=8</xtag-item1></LI>
<LI><xtag-item1>CLK=5</xtag-item1></LI>
<LI><xtag-item1>COUT=3</xtag-item1></LI>
<LI><xtag-item1>CMUX=6</xtag-item1></LI>
<LI><xtag-item1>COUT=8</xtag-item1></LI>
<LI><xtag-item1>CQ=3</xtag-item1></LI>
<LI><xtag-item1>D4=3</xtag-item1></LI>
<LI><xtag-item1>D6=3</xtag-item1></LI>
<LI><xtag-item1>D5=5</xtag-item1></LI>
<LI><xtag-item1>D6=9</xtag-item1></LI>
<LI><xtag-item1>DMUX=6</xtag-item1></LI>
<LI><xtag-item1>DQ=3</xtag-item1></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name>
<UL>
<LI><xtag-item1>A=1</xtag-item1></LI>
<LI><xtag-item1>A2=2</xtag-item1></LI>
<LI><xtag-item1>A3=3</xtag-item1></LI>
<LI><xtag-item1>A4=5</xtag-item1></LI>
<LI><xtag-item1>A5=4</xtag-item1></LI>
<LI><xtag-item1>A6=6</xtag-item1></LI>
<LI><xtag-item1>AMUX=1</xtag-item1></LI>
<LI><xtag-item1>AQ=5</xtag-item1></LI>
<LI><xtag-item1>B1=1</xtag-item1></LI>
<LI><xtag-item1>B2=2</xtag-item1></LI>
<LI><xtag-item1>B3=4</xtag-item1></LI>
<LI><xtag-item1>B4=4</xtag-item1></LI>
<LI><xtag-item1>B5=4</xtag-item1></LI>
<LI><xtag-item1>B6=4</xtag-item1></LI>
<LI><xtag-item1>A=6</xtag-item1></LI>
<LI><xtag-item1>A1=10</xtag-item1></LI>
<LI><xtag-item1>A2=19</xtag-item1></LI>
<LI><xtag-item1>A3=20</xtag-item1></LI>
<LI><xtag-item1>A4=23</xtag-item1></LI>
<LI><xtag-item1>A5=22</xtag-item1></LI>
<LI><xtag-item1>A6=23</xtag-item1></LI>
<LI><xtag-item1>AMUX=2</xtag-item1></LI>
<LI><xtag-item1>AQ=20</xtag-item1></LI>
<LI><xtag-item1>AX=1</xtag-item1></LI>
<LI><xtag-item1>B=11</xtag-item1></LI>
<LI><xtag-item1>B1=7</xtag-item1></LI>
<LI><xtag-item1>B2=15</xtag-item1></LI>
<LI><xtag-item1>B3=16</xtag-item1></LI>
<LI><xtag-item1>B4=20</xtag-item1></LI>
<LI><xtag-item1>B5=21</xtag-item1></LI>
<LI><xtag-item1>B6=22</xtag-item1></LI>
<LI><xtag-item1>BMUX=1</xtag-item1></LI>
<LI><xtag-item1>BQ=4</xtag-item1></LI>
<LI><xtag-item1>C1=2</xtag-item1></LI>
<LI><xtag-item1>C2=3</xtag-item1></LI>
<LI><xtag-item1>C3=3</xtag-item1></LI>
<LI><xtag-item1>C4=3</xtag-item1></LI>
<LI><xtag-item1>C5=3</xtag-item1></LI>
<LI><xtag-item1>C6=3</xtag-item1></LI>
<LI><xtag-item1>CLK=5</xtag-item1></LI>
<LI><xtag-item1>CQ=3</xtag-item1></LI>
<LI><xtag-item1>D1=2</xtag-item1></LI>
<LI><xtag-item1>D2=3</xtag-item1></LI>
<LI><xtag-item1>D3=3</xtag-item1></LI>
<LI><xtag-item1>D4=3</xtag-item1></LI>
<LI><xtag-item1>D5=3</xtag-item1></LI>
<LI><xtag-item1>D6=3</xtag-item1></LI>
<LI><xtag-item1>DQ=3</xtag-item1></LI>
<LI><xtag-item1>BQ=13</xtag-item1></LI>
<LI><xtag-item1>BX=1</xtag-item1></LI>
<LI><xtag-item1>C=6</xtag-item1></LI>
<LI><xtag-item1>C1=7</xtag-item1></LI>
<LI><xtag-item1>C2=20</xtag-item1></LI>
<LI><xtag-item1>C3=21</xtag-item1></LI>
<LI><xtag-item1>C4=22</xtag-item1></LI>
<LI><xtag-item1>C5=22</xtag-item1></LI>
<LI><xtag-item1>C6=22</xtag-item1></LI>
<LI><xtag-item1>CE=10</xtag-item1></LI>
<LI><xtag-item1>CLK=25</xtag-item1></LI>
<LI><xtag-item1>CMUX=3</xtag-item1></LI>
<LI><xtag-item1>CQ=16</xtag-item1></LI>
<LI><xtag-item1>D=11</xtag-item1></LI>
<LI><xtag-item1>D1=7</xtag-item1></LI>
<LI><xtag-item1>D2=17</xtag-item1></LI>
<LI><xtag-item1>D3=20</xtag-item1></LI>
<LI><xtag-item1>D4=21</xtag-item1></LI>
<LI><xtag-item1>D5=20</xtag-item1></LI>
<LI><xtag-item1>D6=20</xtag-item1></LI>
<LI><xtag-item1>DQ=11</xtag-item1></LI>
<LI><xtag-item1>DX=1</xtag-item1></LI>
<LI><xtag-item1>SR=13</xtag-item1></LI>
</UL>
</TD>
<TD>
@@ -407,13 +449,35 @@
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx16-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx16-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx16-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
</xtag-section></UL></TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'><xtag-section name="RunStatistics"><TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=8><B>Software Quality</B></TD></TR><TR ALIGN=LEFT><TD COLSPAN=8><B>Run Statistics</B></TD></TR><TR ALIGN=CENTER BGCOLOR='#FFFF99'><TD><B>Program Name</B></TD><TD><B>Runs Started</B></TD><TD><B>Runs Finished</B></TD><TD><B>Errors</B></TD><TD><B>Fatal Errors</B></TD><TD><B>Internal Errors</B></TD><TD><B>Exceptions</B></TD><TD><B>Core Dumps</B></TD></TR>
<tr>
<td><xtag-program-name>_impact</xtag-program-name></td>
<td><xtag-total-run-started>23</xtag-total-run-started></td>
<td><xtag-total-run-started>24</xtag-total-run-started></td>
<td><xtag-total-run-finished>21</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
@@ -423,8 +487,8 @@
</tr>
<tr>
<td><xtag-program-name>bitgen</xtag-program-name></td>
<td><xtag-total-run-started>34</xtag-total-run-started></td>
<td><xtag-total-run-finished>34</xtag-total-run-finished></td>
<td><xtag-total-run-started>37</xtag-total-run-started></td>
<td><xtag-total-run-finished>37</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@@ -433,8 +497,8 @@
</tr>
<tr>
<td><xtag-program-name>map</xtag-program-name></td>
<td><xtag-total-run-started>38</xtag-total-run-started></td>
<td><xtag-total-run-finished>33</xtag-total-run-finished></td>
<td><xtag-total-run-started>41</xtag-total-run-started></td>
<td><xtag-total-run-finished>36</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@@ -443,8 +507,8 @@
</tr>
<tr>
<td><xtag-program-name>ngdbuild</xtag-program-name></td>
<td><xtag-total-run-started>38</xtag-total-run-started></td>
<td><xtag-total-run-finished>38</xtag-total-run-finished></td>
<td><xtag-total-run-started>41</xtag-total-run-started></td>
<td><xtag-total-run-finished>41</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@@ -453,8 +517,8 @@
</tr>
<tr>
<td><xtag-program-name>par</xtag-program-name></td>
<td><xtag-total-run-started>33</xtag-total-run-started></td>
<td><xtag-total-run-finished>33</xtag-total-run-finished></td>
<td><xtag-total-run-started>36</xtag-total-run-started></td>
<td><xtag-total-run-finished>36</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@@ -463,8 +527,8 @@
</tr>
<tr>
<td><xtag-program-name>trce</xtag-program-name></td>
<td><xtag-total-run-started>33</xtag-total-run-started></td>
<td><xtag-total-run-finished>33</xtag-total-run-finished></td>
<td><xtag-total-run-started>36</xtag-total-run-started></td>
<td><xtag-total-run-finished>36</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@@ -473,8 +537,8 @@
</tr>
<tr>
<td><xtag-program-name>xst</xtag-program-name></td>
<td><xtag-total-run-started>68</xtag-total-run-started></td>
<td><xtag-total-run-finished>68</xtag-total-run-finished></td>
<td><xtag-total-run-started>75</xtag-total-run-started></td>
<td><xtag-total-run-finished>75</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@@ -508,7 +572,7 @@
</TR><TR><TD><xtag-design-property-name>PROP_intProjectCreationTimestamp</xtag-design-property-name>=<xtag-design-property-value>2022-06-08T11:31:57</xtag-design-property-value></TD>
<TD><xtag-design-property-name>PROP_intWbtProjectID</xtag-design-property-name>=<xtag-design-property-value>047E6D81914F4B9E9C732FAABBF95C82</xtag-design-property-value></TD>
</TR><TR><TD><xtag-process-property-name>PROP_intWbtProjectIteration</xtag-process-property-name>=<xtag-process-property-value>1</xtag-process-property-value></TD>
</TR><TR><TD><xtag-process-property-name>PROP_intWbtProjectIteration</xtag-process-property-name>=<xtag-process-property-value>4</xtag-process-property-value></TD>
<TD><xtag-design-property-name>PROP_intWorkingDirLocWRTProjDir</xtag-design-property-name>=<xtag-design-property-value>Same</xtag-design-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_intWorkingDirUsed</xtag-design-property-name>=<xtag-design-property-value>No</xtag-design-property-value></TD>
@@ -532,58 +596,61 @@
<xtag-section name="UnisimStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Unisim Statistics</B></TD></TR>
<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_PRE_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFG</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFG</xtag-preunisim-param-name>=<xtag-preunisim-param-value>2</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFGP</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FD</xtag-preunisim-param-name>=<xtag-preunisim-param-value>15</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FD_1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>17</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FD</xtag-preunisim-param-name>=<xtag-preunisim-param-value>44</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDCE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>20</xtag-preunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDR_1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>13</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FD_1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>4</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_GND</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_INV</xtag-preunisim-param-name>=<xtag-preunisim-param-value>4</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>13</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT2</xtag-preunisim-param-name>=<xtag-preunisim-param-value>5</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_IBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT3</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT4</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT5</xtag-preunisim-param-name>=<xtag-preunisim-param-value>5</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT6</xtag-preunisim-param-name>=<xtag-preunisim-param-value>5</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_INV</xtag-preunisim-param-name>=<xtag-preunisim-param-value>31</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>14</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT2</xtag-preunisim-param-name>=<xtag-preunisim-param-value>7</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT3</xtag-preunisim-param-name>=<xtag-preunisim-param-value>9</xtag-preunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>13</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>3</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUFT</xtag-preunisim-param-name>=<xtag-preunisim-param-value>4</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT4</xtag-preunisim-param-name>=<xtag-preunisim-param-value>4</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT5</xtag-preunisim-param-name>=<xtag-preunisim-param-value>43</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT6</xtag-preunisim-param-name>=<xtag-preunisim-param-value>28</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>36</xtag-preunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>7</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_VCC</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_XORCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>15</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_XORCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>39</xtag-preunisim-param-value></TD>
<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_POST_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_BUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>2</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FD</xtag-postunisim-param-name>=<xtag-postunisim-param-value>15</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FD_1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>17</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_GND</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_BUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>3</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FD</xtag-postunisim-param-name>=<xtag-postunisim-param-value>44</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDCE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>20</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDR_1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>13</xtag-postunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FD_1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>4</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_GND</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>13</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_INV</xtag-postunisim-param-name>=<xtag-postunisim-param-value>4</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>13</xtag-postunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT2</xtag-postunisim-param-name>=<xtag-postunisim-param-value>5</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT3</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT4</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT5</xtag-postunisim-param-name>=<xtag-postunisim-param-value>5</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_INV</xtag-postunisim-param-name>=<xtag-postunisim-param-value>31</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>14</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT2</xtag-postunisim-param-name>=<xtag-postunisim-param-value>7</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT3</xtag-postunisim-param-name>=<xtag-postunisim-param-value>9</xtag-postunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT6</xtag-postunisim-param-name>=<xtag-postunisim-param-value>5</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>13</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>3</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUFT</xtag-postunisim-param-name>=<xtag-postunisim-param-value>4</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT4</xtag-postunisim-param-name>=<xtag-postunisim-param-value>4</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT5</xtag-postunisim-param-name>=<xtag-postunisim-param-value>43</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT6</xtag-postunisim-param-name>=<xtag-postunisim-param-value>28</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>36</xtag-postunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>7</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_VCC</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_XORCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>15</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_XORCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>39</xtag-postunisim-param-value></TD>
</xtag-section></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="XstCommandLineOptions">

2
webtalk.log
View File

@@ -4,7 +4,7 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Project Information
--------------------
ProjectID=047E6D81914F4B9E9C732FAABBF95C82
ProjectIteration=1
ProjectIteration=4
WebTalk Summary
----------------

6
webtalk_pn.xml
View File

@@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Wed Jun 08 11:35:45 2022">
<application name="pn" timeStamp="Wed Jun 08 12:43:04 2022">
<section name="Project Information" visible="false">
<property name="ProjectID" value="047E6D81914F4B9E9C732FAABBF95C82" type="project"/>
<property name="ProjectIteration" value="1" type="project"/>
<property name="ProjectIteration" value="4" type="project"/>
<property name="ProjectFile" value="C:/Users/Gabriel/Xilinx/Aula20220608/Aula20220608.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2022-06-08T11:31:57" type="project"/>
</section>
@@ -25,7 +25,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2022-06-08T11:31:57" type="design"/>
<property name="PROP_intWbtProjectID" value="047E6D81914F4B9E9C732FAABBF95C82" type="design"/>
<property name="PROP_intWbtProjectIteration" value="1" type="process"/>
<property name="PROP_intWbtProjectIteration" value="4" type="process"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_AutoTop" value="true" type="design"/>

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xlnx_auto_0_xdb/cst.xbcd
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xst/work/work.vdbl
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xst/work/work.vdbx
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