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Cleanup e synthesis

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Gabriel Lima
2022-06-08 11:36:34 -03:00
parent 1bdd7c5ffd
commit 4569cbc5a1
58 changed files with 9541 additions and 137 deletions
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@@ -0,0 +1,186 @@
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387
Aula20220608.xise
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<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="Spartan-6 SP601 Evaluation Platform" xil_pn:valueState="non-default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
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<property xil_pn:name="Implementation Top File" xil_pn:value="textovhdl.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/textovhdl" xil_pn:valueState="non-default"/>
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<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
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<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
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<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
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<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="textovhdl" xil_pn:valueState="default"/>
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<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="default"/>
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<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
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<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
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<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="textovhdl_synthesis.vhd" xil_pn:valueState="default"/>
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<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
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<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
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<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
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<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
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<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="textovhdl" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
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<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="Aula20220608" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2022-06-08T11:31:57" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="047E6D81914F4B9E9C732FAABBF95C82" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

2
_ngo/netlist.lst Normal file
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C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.ngc 1654698883
OK

9
_xmsgs/bitgen.xmsgs Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>

51
_xmsgs/map.xmsgs Normal file
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@@ -0,0 +1,51 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">BUT&lt;3&gt;_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="395" delta="new" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">12</arg> more times for the following (max. 5 shown):
<arg fmt="%s" index="3">BUT&lt;2&gt;_IBUF,
BUT&lt;1&gt;_IBUF,
BUT&lt;0&gt;_IBUF,
DIPSW&lt;3&gt;_IBUF,
DIPSW&lt;2&gt;_IBUF</arg>
To see the details of these <arg fmt="%s" index="4">info</arg> messages, please use the -detail switch.
</msg>
<msg type="info" file="MapLib" num="562" delta="new" >No environment variables are currently set.
</msg>
<msg type="warning" file="MapLib" num="701" delta="new" >Signal <arg fmt="%s" index="1">LEDS&lt;3&gt;</arg> connected to top level port <arg fmt="%s" index="2">LEDS&lt;3&gt;</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="new" >Signal <arg fmt="%s" index="1">LEDS&lt;2&gt;</arg> connected to top level port <arg fmt="%s" index="2">LEDS&lt;2&gt;</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="new" >Signal <arg fmt="%s" index="1">LEDS&lt;1&gt;</arg> connected to top level port <arg fmt="%s" index="2">LEDS&lt;1&gt;</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="new" >Signal <arg fmt="%s" index="1">LEDS&lt;0&gt;</arg> connected to top level port <arg fmt="%s" index="2">LEDS&lt;0&gt;</arg> has been removed.
</msg>
<msg type="info" file="LIT" num="244" delta="new" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
</msg>
<msg type="info" file="Pack" num="1716" delta="new" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)
</msg>
<msg type="info" file="Pack" num="1720" delta="new" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts)
</msg>
<msg type="info" file="Map" num="215" delta="new" >The Interim Design Summary has been generated in the MAP Report (.mrp).
</msg>
<msg type="info" file="Pack" num="1650" delta="new" >Map created a placed design.
</msg>
</messages>

24
_xmsgs/ngdbuild.xmsgs Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="NgdBuild" num="470" delta="new" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">GPIO&lt;7&gt;</arg>&apos; has no legal driver
</msg>
<msg type="warning" file="NgdBuild" num="470" delta="new" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">GPIO&lt;6&gt;</arg>&apos; has no legal driver
</msg>
<msg type="warning" file="NgdBuild" num="470" delta="new" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">GPIO&lt;5&gt;</arg>&apos; has no legal driver
</msg>
<msg type="warning" file="NgdBuild" num="470" delta="new" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">GPIO&lt;4&gt;</arg>&apos; has no legal driver
</msg>
<msg type="warning" file="NgdBuild" num="470" delta="new" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">GPIO&lt;3&gt;</arg>&apos; has no legal driver
</msg>
</messages>

64
_xmsgs/par.xmsgs Normal file
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@@ -0,0 +1,64 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Par" num="282" delta="new" >No user timing constraints were detected or you have set the option to ignore timing constraints (&quot;par -x&quot;). Place and Route will run in &quot;Performance Evaluation Mode&quot; to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to &quot;std&quot;. For best performance, set the effort level to &quot;high&quot;.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">BUT&lt;2&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">BUT&lt;3&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">GPIO&lt;3&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">GPIO&lt;4&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">GPIO&lt;5&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">GPIO&lt;6&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">GPIO&lt;7&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">DIPSW&lt;0&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">DIPSW&lt;1&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">DIPSW&lt;2&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">DIPSW&lt;3&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">BUT&lt;0&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">BUT&lt;1&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="info" file="Par" num="459" delta="new" >The Clock Report is not displayed in the non timing-driven mode.
</msg>
<msg type="info" file="Timing" num="2761" delta="new" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg>
<msg type="warning" file="ParHelpers" num="361" delta="new" >There are <arg fmt="%d" index="1">13</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
</msg>
<msg type="warning" file="Par" num="283" delta="new" >There are <arg fmt="%d" index="1">13</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
</msg>
</messages>

3
_xmsgs/pn_parser.xmsgs
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@@ -8,5 +8,8 @@
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;C:/Users/Gabriel/Xilinx/Aula20220608/textovhdl.vhd&quot; into library work</arg>
</msg>
</messages>

17
_xmsgs/trce.xmsgs Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Timing" num="2698" delta="new" >No timing constraints found, doing default enumeration.</msg>
<msg type="info" file="Timing" num="3412" delta="new" >To improve timing, see the Timing Closure User Guide (UG612).</msg>
<msg type="info" file="Timing" num="2752" delta="new" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
<msg type="info" file="Timing" num="3339" delta="new" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
</messages>

108
_xmsgs/xst.xmsgs Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 64: Assignment to <arg fmt="%s" index="1">clk100k</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 65: Assignment to <arg fmt="%s" index="1">clk25k</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 66: Assignment to <arg fmt="%s" index="1">clk621ms</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 20: Net &lt;<arg fmt="%s" index="1">num7[3]</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">BUT</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">DIPSW</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">num7</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">num6</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">num5</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">num4</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">num3</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">num2</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">num1</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">num0</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="info" file="Xst" num="3218" delta="new" >HDL ADVISOR - The RAM &lt;<arg fmt="%s" index="1">Mram_proxdisplay</arg>&gt; will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_6</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_7</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_8</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_9</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_10</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_11</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_12</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_13</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_14</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_15</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_16</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_17</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_18</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_19</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_20</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_21</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_22</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_23</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
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<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2022-06-08T11:32:41</DateModified>
<ModuleName>textovhdl</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
<SavedFilePath>C:/Users/Gabriel/Xilinx/Aula20220608/iseconfig/textovhdl.xreport</SavedFilePath>
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<toc-item title="Design Overview" target="Design Overview" />
<toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
<toc-item title="Performance Summary" target="Performance Summary" />
<toc-item title="Failing Constraints" target="Failing Constraints" />
<toc-item title="Detailed Reports" target="Detailed Reports" />
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</viewgroup>
<viewgroup label="Errors and Warnings" >
<view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
<view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
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<view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
<view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
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<viewgroup label="Detailed Reports" >
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="textovhdl.syr" label="Synthesis Report" >
<toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
<toc-item title="HDL Compilation" target=" HDL Compilation " />
<toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
<toc-item title="HDL Analysis" target=" HDL Analysis " />
<toc-item title="HDL Parsing" target=" HDL Parsing " />
<toc-item title="HDL Elaboration" target=" HDL Elaboration " />
<toc-item title="HDL Synthesis" target=" HDL Synthesis " />
<toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
<toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" />
<toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
<toc-item title="Low Level Synthesis" target=" Low Level Synthesis " />
<toc-item title="Partition Report" target=" Partition Report " />
<toc-item title="Final Report" target=" Final Report " />
<toc-item title="Design Summary" target=" Design Summary " />
<toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
<toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
<toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
<toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
<toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
<toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
<toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
<toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
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<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Command Line" target="Command Line:" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
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<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="textovhdl_map.mrp" label="Map Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
<toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
<toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
<toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
<toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
<toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
<toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
<toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
<toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
<toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
<toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
<toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
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<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="textovhdl.par" label="Place and Route Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Device Utilization" target="Device Utilization Summary:" />
<toc-item title="Router Information" target="Starting Router" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Clock Report" target="Generating Clock Report" />
<toc-item title="Timing Results" target="Timing Score:" />
<toc-item title="Final Summary" target="Peak Memory Usage:" />
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<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="textovhdl.twr" label="Post-PAR Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
<toc-item title="Timing Constraints" target="Timing constraint:" />
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
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<toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
<toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
<toc-item title="Pin Resources" target="** Pin Resources **" />
<toc-item title="Global Resources" target="** Global Control Resources **" />
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<toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
<toc-item title="Performance Summary" target="Performance Summary:" />
</view>
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="textovhdl.pwr" label="Power Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Power summary" target="Power summary" />
<toc-item title="Thermal summary" target="Thermal summary" />
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<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="textovhdl.bgn" label="Bitgen Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
<toc-item title="Final Summary" target="DRC detected" />
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</viewgroup>
<viewgroup label="Secondary Reports" >
<view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/textovhdl_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/textovhdl_translate.nlf" label="Post-Translate Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="textovhdl_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
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<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Design Information" target="Design Information" />
<toc-item title="Design Summary" target="Design Summary" />
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<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
<toc-item title="Timing Constraints" target="Timing constraint:" />
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
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<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="textovhdl_map.psr" label="Physical Synthesis Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="textovhdl_pad.txt" label="Pad Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="textovhdl.unroutes" label="Unroutes Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="textovhdl_preroute.tsi" label="Post-Map Constraints Interaction Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
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<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="textovhdl.grf" label="Guide Results Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="textovhdl.dly" label="Asynchronous Delay Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="textovhdl.clk_rgn" label="Clock Region Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="textovhdl.tsi" label="Post-Place and Route Constraints Interaction Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="textovhdl_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
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<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="textovhdl_sta.nlf" label="Primetime Netlist Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="textovhdl.ibs" label="IBIS Model" >
<toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
<toc-item title="Component" target="Component " />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="textovhdl.lck" label="Back-annotate Pin Report" >
<toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
<toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="textovhdl.lpc" label="Locked Pin Constraints" >
<toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
<toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
</view>
<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/textovhdl_timesim.nlf" label="Post-Fit Simulation Model Report" />
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<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>39</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>104</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>104</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>100</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>4.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>4.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>4.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>5.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>5.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>5.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>5.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>5.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>5.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>5.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>2.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>2.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>9.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>4.1</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>0.6</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0050</xtag-par-property-value></TD></TR>
</xtag-section>
</TABLE>

134
textovhdl.bgn Normal file
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Release 14.7 - Bitgen P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '6slx16.nph' in environment
C:\Xilinx\14.7\ISE_DS\ISE\.
"textovhdl" is an NCD, version 3.2, device xc6slx16, package csg324, speed -2
Opened constraints file textovhdl.pcf.
Wed Jun 08 11:36:09 2022
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 textovhdl.ncd
Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name | Current Setting |
+----------------------+----------------------+
| Compress | (Not Specified)* |
+----------------------+----------------------+
| Readback | (Not Specified)* |
+----------------------+----------------------+
| CRC | Enable** |
+----------------------+----------------------+
| DebugBitstream | No** |
+----------------------+----------------------+
| ConfigRate | 2** |
+----------------------+----------------------+
| StartupClk | Cclk** |
+----------------------+----------------------+
| DonePin | Pullup* |
+----------------------+----------------------+
| ProgPin | Pullup** |
+----------------------+----------------------+
| TckPin | Pullup** |
+----------------------+----------------------+
| TdiPin | Pullup** |
+----------------------+----------------------+
| TdoPin | Pullup** |
+----------------------+----------------------+
| TmsPin | Pullup** |
+----------------------+----------------------+
| UnusedPin | Pulldown** |
+----------------------+----------------------+
| GWE_cycle | 6** |
+----------------------+----------------------+
| GTS_cycle | 5** |
+----------------------+----------------------+
| LCK_cycle | NoWait** |
+----------------------+----------------------+
| DONE_cycle | 4** |
+----------------------+----------------------+
| Persist | No* |
+----------------------+----------------------+
| DriveDone | No** |
+----------------------+----------------------+
| DonePipe | No** |
+----------------------+----------------------+
| Security | None** |
+----------------------+----------------------+
| UserID | 0xFFFFFFFF** |
+----------------------+----------------------+
| ActiveReconfig | No* |
+----------------------+----------------------+
| Partial | (Not Specified)* |
+----------------------+----------------------+
| Encrypt | No* |
+----------------------+----------------------+
| Key0 | pick* |
+----------------------+----------------------+
| StartCBC | pick* |
+----------------------+----------------------+
| KeyFile | (Not Specified)* |
+----------------------+----------------------+
| drive_awake | No** |
+----------------------+----------------------+
| Reset_on_err | No** |
+----------------------+----------------------+
| suspend_filter | Yes* |
+----------------------+----------------------+
| en_sw_gsr | No** |
+----------------------+----------------------+
| en_suspend | No* |
+----------------------+----------------------+
| sw_clk | Startupclk** |
+----------------------+----------------------+
| sw_gwe_cycle | 5** |
+----------------------+----------------------+
| sw_gts_cycle | 4** |
+----------------------+----------------------+
| multipin_wakeup | No** |
+----------------------+----------------------+
| wakeup_mask | 0x00* |
+----------------------+----------------------+
| ExtMasterCclk_en | No** |
+----------------------+----------------------+
| ExtMasterCclk_divide | 1* |
+----------------------+----------------------+
| CrcCoverage | No* |
+----------------------+----------------------+
| glutmask | Yes* |
+----------------------+----------------------+
| next_config_addr | 0x00000000* |
+----------------------+----------------------+
| next_config_new_mode | No* |
+----------------------+----------------------+
| next_config_boot_mode | 001* |
+----------------------+----------------------+
| next_config_register_write | Enable* |
+----------------------+----------------------+
| next_config_reboot | Enable* |
+----------------------+----------------------+
| golden_config_addr | 0x00000000* |
+----------------------+----------------------+
| failsafe_user | 0x0000* |
+----------------------+----------------------+
| TIMER_CFG | 0xFFFF |
+----------------------+----------------------+
| spi_buswidth | 1** |
+----------------------+----------------------+
| TimeStamp | Default* |
+----------------------+----------------------+
| IEEE1532 | No* |
+----------------------+----------------------+
| Binary | No** |
+----------------------+----------------------+
* Default setting.
** The specified setting matches the default setting.
There were 0 CONFIG constraint(s) processed from textovhdl.pcf.
Running DRC.
DRC detected 0 errors and 0 warnings.
Creating bit map...
Saving bit stream in "textovhdl.bit".
Bitstream generation is complete.

BIN
textovhdl.bit Normal file
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Binary file not shown.

41
textovhdl.bld Normal file
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Release 14.7 ngdbuild P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
-intstyle ise -dd _ngo -nt timestamp -uc restricoes.ucf -p xc6slx16-csg324-2
textovhdl.ngc textovhdl.ngd
Reading NGO file "C:/Users/Gabriel/Xilinx/Aula20220608/textovhdl.ngc" ...
Gathering constraint information from source properties...
Done.
Annotating constraints to design from ucf file "restricoes.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
Done...
Checking expanded design ...
WARNING:NgdBuild:470 - bidirect pad net 'GPIO<7>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'GPIO<6>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'GPIO<5>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'GPIO<4>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'GPIO<3>' has no legal driver
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 5
Total memory usage is 161712 kilobytes
Writing NGD file "textovhdl.ngd" ...
Total REAL time to NGDBUILD completion: 3 sec
Total CPU time to NGDBUILD completion: 3 sec
Writing NGDBUILD log file "textovhdl.bld"...

6
textovhdl.cmd_log Normal file
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xst -intstyle ise -ifn "C:/Users/Gabriel/Xilinx/Aula20220608/textovhdl.xst" -ofn "C:/Users/Gabriel/Xilinx/Aula20220608/textovhdl.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc restricoes.ucf -p xc6slx16-csg324-2 textovhdl.ngc textovhdl.ngd
map -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o textovhdl_map.ncd textovhdl.ngd textovhdl.pcf
par -w -intstyle ise -ol high -mt off textovhdl_map.ncd textovhdl.ncd textovhdl.pcf
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml textovhdl.twx textovhdl.ncd -o textovhdl.twr textovhdl.pcf -ucf restricoes.ucf
bitgen -intstyle ise -f textovhdl.ut textovhdl.ncd

8
textovhdl.drc Normal file
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Release 14.7 Drc P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Wed Jun 08 11:36:09 2022
drc -z textovhdl.ncd textovhdl.pcf
DRC detected 0 errors and 0 warnings.

1
textovhdl.lso Normal file
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work

3
textovhdl.ncd Normal file
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3
textovhdl.ngc Normal file
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File diff suppressed because one or more lines are too long

3
textovhdl.ngd Normal file
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File diff suppressed because one or more lines are too long

3
textovhdl.ngr Normal file
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354
textovhdl.pad Normal file
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Release 14.7 - par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Wed Jun 08 11:35:52 2022
# NOTE: This file is designed to be imported into a spreadsheet program
# such as Microsoft Excel for viewing, printing and sorting. The |
# character is used as the data field separator. This file is also designed
# to support parsing.
#
INPUT FILE: textovhdl_map.ncd
OUTPUT FILE: textovhdl.pad
PART TYPE: xc6slx16
SPEED GRADE: -2
PACKAGE: csg324
Pinout by Pin Number:
-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|IO Register|Signal Integrity|
A1|||GND||||||||||||
A2||IOBS|IO_L2N_0|UNUSED||0|||||||||
A3|GPIO<2>|IOB|IO_L4N_0|OUTPUT|LVCMOS25*|0|12|SLOW||||LOCATED|NO|NONE|
A4||IOBS|IO_L5N_0|UNUSED||0|||||||||
A5||IOBS|IO_L6N_0|UNUSED||0|||||||||
A6||IOBS|IO_L8N_VREF_0|UNUSED||0|||||||||
A7||IOBS|IO_L10N_0|UNUSED||0|||||||||
A8||IOBS|IO_L33N_0|UNUSED||0|||||||||
A9||IOBS|IO_L35N_GCLK16_0|UNUSED||0|||||||||
A10||IOBS|IO_L37N_GCLK12_0|UNUSED||0|||||||||
A11||IOBS|IO_L39N_0|UNUSED||0|||||||||
A12||IOBS|IO_L41N_0|UNUSED||0|||||||||
A13||IOBS|IO_L50N_0|UNUSED||0|||||||||
A14||IOBS|IO_L62N_VREF_0|UNUSED||0|||||||||
A15||IOBS|IO_L64N_SCP4_0|UNUSED||0|||||||||
A16||IOBS|IO_L66N_SCP0_0|UNUSED||0|||||||||
A17|||TCK||||||||||||
A18|||GND||||||||||||
B1|||VCCAUX||||||||2.5||||
B2||IOBM|IO_L2P_0|UNUSED||0|||||||||
B3||IOBM|IO_L4P_0|UNUSED||0|||||||||
B4|GPIO<5>|IOB|IO_L5P_0|INPUT|LVCMOS25*|0||||NONE||LOCATED|NO|NONE|
B5|||VCCO_0|||0|||||2.50||||
B6||IOBM|IO_L8P_0|UNUSED||0|||||||||
B7|||GND||||||||||||
B8||IOBM|IO_L33P_0|UNUSED||0|||||||||
B9||IOBM|IO_L35P_GCLK17_0|UNUSED||0|||||||||
B10|||VCCO_0|||0|||||2.50||||
B11||IOBM|IO_L39P_0|UNUSED||0|||||||||
B12||IOBM|IO_L41P_0|UNUSED||0|||||||||
B13|||GND||||||||||||
B14||IOBM|IO_L62P_0|UNUSED||0|||||||||
B15|||VCCO_0|||0|||||2.50||||
B16||IOBM|IO_L66P_SCP1_0|UNUSED||0|||||||||
B17|||VCCAUX||||||||2.5||||
B18|||TMS||||||||||||
C1||IOBS|IO_L83N_VREF_3|UNUSED||3|||||||||
C2||IOBM|IO_L83P_3|UNUSED||3|||||||||
C3|||GND||||||||||||
C4||IOBS|IO_L1N_VREF_0|UNUSED||0|||||||||
C5||IOBM|IO_L6P_0|UNUSED||0|||||||||
C6||IOBS|IO_L3N_0|UNUSED||0|||||||||
C7||IOBM|IO_L10P_0|UNUSED||0|||||||||
C8||IOBS|IO_L11N_0|UNUSED||0|||||||||
C9||IOBS|IO_L34N_GCLK18_0|UNUSED||0|||||||||
C10||IOBM|IO_L37P_GCLK13_0|UNUSED||0|||||||||
C11||IOBS|IO_L36N_GCLK14_0|UNUSED||0|||||||||
C12||IOBS|IO_L47N_0|UNUSED||0|||||||||
C13||IOBM|IO_L50P_0|UNUSED||0|||||||||
C14||IOBS|IO_L65N_SCP2_0|UNUSED||0|||||||||
C15||IOBM|IO_L64P_SCP5_0|UNUSED||0|||||||||
C16|||GND||||||||||||
C17||IOBM|IO_L29P_A23_M1A13_1|UNUSED||1|||||||||
C18||IOBS|IO_L29N_A22_M1A14_1|UNUSED||1|||||||||
D1||IOBS|IO_L52N_M3A9_3|UNUSED||3|||||||||
D2||IOBM|IO_L52P_M3A8_3|UNUSED||3|||||||||
D3||IOBS|IO_L54N_M3A11_3|UNUSED||3|||||||||
D4||IOBM|IO_L1P_HSWAPEN_0|UNUSED||0|||||||||
D5|||GND||||||||||||
D6||IOBM|IO_L3P_0|UNUSED||0|||||||||
D7|||VCCO_0|||0|||||2.50||||
D8||IOBM|IO_L11P_0|UNUSED||0|||||||||
D9||IOBM|IO_L34P_GCLK19_0|UNUSED||0|||||||||
D10|||GND||||||||||||
D11||IOBM|IO_L36P_GCLK15_0|UNUSED||0|||||||||
D12||IOBM|IO_L47P_0|UNUSED||0|||||||||
D13|||VCCO_0|||0|||||2.50||||
D14|DIPSW<0>|IOB|IO_L65P_SCP3_0|INPUT|LVCMOS25*|0||||NONE||LOCATED|NO|NONE|
D15|||TDI||||||||||||
D16|||TDO||||||||||||
D17||IOBM|IO_L31P_A19_M1CKE_1|UNUSED||1|||||||||
D18||IOBS|IO_L31N_A18_M1A12_1|UNUSED||1|||||||||
E1||IOBS|IO_L50N_M3BA2_3|UNUSED||3|||||||||
E2|||VCCO_3|||3|||||any******||||
E3||IOBM|IO_L50P_M3WE_3|UNUSED||3|||||||||
E4|BUT<2>|IOB|IO_L54P_M3RESET_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
E5|||VCCAUX||||||||2.5||||
E6||IOBS|IO_L7N_0|UNUSED||0|||||||||
E7||IOBM|IO_L9P_0|UNUSED||0|||||||||
E8||IOBS|IO_L9N_0|UNUSED||0|||||||||
E9|||VCCAUX||||||||2.5||||
E10|||VCCO_0|||0|||||2.50||||
E11||IOBS|IO_L42N_0|UNUSED||0|||||||||
E12|DIPSW<1>|IOB|IO_L51N_0|INPUT|LVCMOS25*|0||||NONE||LOCATED|NO|NONE|
E13||IOBS|IO_L63N_SCP6_0|UNUSED||0|||||||||
E14|||VCCAUX||||||||2.5||||
E15|||GND||||||||||||
E16||IOBM|IO_L33P_A15_M1A10_1|UNUSED||1|||||||||
E17|||VCCO_1|||1|||||2.50||||
E18||IOBS|IO_L33N_A14_M1A4_1|UNUSED||1|||||||||
F1||IOBS|IO_L48N_M3BA1_3|UNUSED||3|||||||||
F2||IOBM|IO_L48P_M3BA0_3|UNUSED||3|||||||||
F3||IOBS|IO_L51N_M3A4_3|UNUSED||3|||||||||
F4||IOBM|IO_L51P_M3A10_3|UNUSED||3|||||||||
F5|BUT<3>|IOB|IO_L55N_M3A14_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
F6|BUT<1>|IOB|IO_L55P_M3A13_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
F7||IOBM|IO_L7P_0|UNUSED||0|||||||||
F8||IOBS|IO_L32N_0|UNUSED||0|||||||||
F9||IOBS|IO_L38N_VREF_0|UNUSED||0|||||||||
F10||IOBS|IO_L40N_0|UNUSED||0|||||||||
F11||IOBM|IO_L42P_0|UNUSED||0|||||||||
F12|DIPSW<2>|IOB|IO_L51P_0|INPUT|LVCMOS25*|0||||NONE||LOCATED|NO|NONE|
F13|GPIO<6>|IOB|IO_L63P_SCP7_0|INPUT|LVCMOS25*|0||||NONE||LOCATED|NO|NONE|
F14||IOBM|IO_L30P_A21_M1RESET_1|UNUSED||1|||||||||
F15|GPIO<4>|IOB|IO_L1P_A25_1|INPUT|LVCMOS25*|1||||NONE||LOCATED|NO|NONE|
F16||IOBS|IO_L1N_A24_VREF_1|UNUSED||1|||||||||
F17||IOBM|IO_L35P_A11_M1A7_1|UNUSED||1|||||||||
F18||IOBS|IO_L35N_A10_M1A2_1|UNUSED||1|||||||||
G1||IOBS|IO_L46N_M3CLKN_3|UNUSED||3|||||||||
G2|||GND||||||||||||
G3||IOBM|IO_L46P_M3CLK_3|UNUSED||3|||||||||
G4|||VCCO_3|||3|||||any******||||
G5|||GND||||||||||||
G6||IOBS|IO_L53N_M3A12_3|UNUSED||3|||||||||
G7|||VCCINT||||||||1.2||||
G8||IOBM|IO_L32P_0|UNUSED||0|||||||||
G9||IOBM|IO_L38P_0|UNUSED||0|||||||||
G10|||VCCAUX||||||||2.5||||
G11||IOBM|IO_L40P_0|UNUSED||0|||||||||
G12|||GND||||||||||||
G13||IOBS|IO_L32N_A16_M1A9_1|UNUSED||1|||||||||
G14||IOBS|IO_L30N_A20_M1A11_1|UNUSED||1|||||||||
G15|||VCCO_1|||1|||||2.50||||
G16||IOBM|IO_L38P_A5_M1CLK_1|UNUSED||1|||||||||
G17|||GND||||||||||||
G18||IOBS|IO_L38N_A4_M1CLKN_1|UNUSED||1|||||||||
H1||IOBS|IO_L41N_GCLK26_M3DQ5_3|UNUSED||3|||||||||
H2||IOBM|IO_L41P_GCLK27_M3DQ4_3|UNUSED||3|||||||||
H3||IOBS|IO_L44N_GCLK20_M3A6_3|UNUSED||3|||||||||
H4||IOBM|IO_L44P_GCLK21_M3A5_3|UNUSED||3|||||||||
H5||IOBS|IO_L49N_M3A2_3|UNUSED||3|||||||||
H6||IOBM|IO_L49P_M3A7_3|UNUSED||3|||||||||
H7||IOBM|IO_L53P_M3CKE_3|UNUSED||3|||||||||
H8|||GND||||||||||||
H9|||VCCINT||||||||1.2||||
H10|||GND||||||||||||
H11|||VCCINT||||||||1.2||||
H12||IOBM|IO_L32P_A17_M1A8_1|UNUSED||1|||||||||
H13||IOBM|IO_L36P_A9_M1BA0_1|UNUSED||1|||||||||
H14||IOBS|IO_L36N_A8_M1BA1_1|UNUSED||1|||||||||
H15||IOBM|IO_L37P_A7_M1A0_1|UNUSED||1|||||||||
H16||IOBS|IO_L37N_A6_M1A1_1|UNUSED||1|||||||||
H17||IOBM|IO_L43P_GCLK5_M1DQ4_1|UNUSED||1|||||||||
H18||IOBS|IO_L43N_GCLK4_M1DQ5_1|UNUSED||1|||||||||
J1||IOBS|IO_L40N_M3DQ7_3|UNUSED||3|||||||||
J2|||VCCO_3|||3|||||any******||||
J3||IOBM|IO_L40P_M3DQ6_3|UNUSED||3|||||||||
J4|||GND||||||||||||
J5|||VCCO_3|||3|||||any******||||
J6||IOBS|IO_L47N_M3A1_3|UNUSED||3|||||||||
J7||IOBM|IO_L47P_M3A0_3|UNUSED||3|||||||||
J8|||VCCINT||||||||1.2||||
J9|||GND||||||||||||
J10|||VCCINT||||||||1.2||||
J11|||GND||||||||||||
J12|||VCCAUX||||||||2.5||||
J13||IOBM|IO_L39P_M1A3_1|UNUSED||1|||||||||
J14|||VCCO_1|||1|||||2.50||||
J15|||GND||||||||||||
J16||IOBM|IO_L44P_A3_M1DQ6_1|UNUSED||1|||||||||
J17|||VCCO_1|||1|||||2.50||||
J18||IOBS|IO_L44N_A2_M1DQ7_1|UNUSED||1|||||||||
K1||IOBS|IO_L38N_M3DQ3_3|UNUSED||3|||||||||
K2||IOBM|IO_L38P_M3DQ2_3|UNUSED||3|||||||||
K3||IOBS|IO_L42N_GCLK24_M3LDM_3|UNUSED||3|||||||||
K4||IOBM|IO_L42P_GCLK25_TRDY2_M3UDM_3|UNUSED||3|||||||||
K5||IOBS|IO_L43N_GCLK22_IRDY2_M3CASN_3|UNUSED||3|||||||||
K6||IOBS|IO_L45N_M3ODT_3|UNUSED||3|||||||||
K7|||VCCAUX||||||||2.5||||
K8|||GND||||||||||||
K9|||VCCINT||||||||1.2||||
K10|||GND||||||||||||
K11|||VCCINT||||||||1.2||||
K12||IOBM|IO_L34P_A13_M1WE_1|UNUSED||1|||||||||
K13||IOBS|IO_L34N_A12_M1BA2_1|UNUSED||1|||||||||
K14||IOBS|IO_L39N_M1ODT_1|UNUSED||1|||||||||
K15||IOBM|IO_L41P_GCLK9_IRDY1_M1RASN_1|UNUSED||1|||||||||
K16||IOBS|IO_L41N_GCLK8_M1CASN_1|UNUSED||1|||||||||
K17||IOBM|IO_L45P_A1_M1LDQS_1|UNUSED||1|||||||||
K18||IOBS|IO_L45N_A0_M1LDQSN_1|UNUSED||1|||||||||
L1||IOBS|IO_L37N_M3DQ1_3|UNUSED||3|||||||||
L2||IOBM|IO_L37P_M3DQ0_3|UNUSED||3|||||||||
L3||IOBS|IO_L39N_M3LDQSN_3|UNUSED||3|||||||||
L4||IOBM|IO_L39P_M3LDQS_3|UNUSED||3|||||||||
L5||IOBM|IO_L43P_GCLK23_M3RASN_3|UNUSED||3|||||||||
L6||IOBM|IO_L31P_3|UNUSED||3|||||||||
L7||IOBM|IO_L45P_M3A3_3|UNUSED||3|||||||||
L8|||VCCINT||||||||1.2||||
L9|||GND||||||||||||
L10|||VCCINT||||||||1.2||||
L11|||GND||||||||||||
L12||IOBM|IO_L40P_GCLK11_M1A5_1|UNUSED||1|||||||||
L13||IOBS|IO_L40N_GCLK10_M1A6_1|UNUSED||1|||||||||
L14||IOBM|IO_L61P_1|UNUSED||1|||||||||
L15|GPIO<3>|IOB|IO_L42P_GCLK7_M1UDM_1|INPUT|LVCMOS25*|1||||NONE||LOCATED|NO|NONE|
L16||IOBS|IO_L42N_GCLK6_TRDY1_M1LDM_1|UNUSED||1|||||||||
L17||IOBM|IO_L46P_FCS_B_M1DQ2_1|UNUSED||1|||||||||
L18||IOBS|IO_L46N_FOE_B_M1DQ3_1|UNUSED||1|||||||||
M1||IOBS|IO_L36N_M3DQ9_3|UNUSED||3|||||||||
M2|||GND||||||||||||
M3||IOBM|IO_L36P_M3DQ8_3|UNUSED||3|||||||||
M4|||VCCO_3|||3|||||any******||||
M5||IOBS|IO_L31N_VREF_3|UNUSED||3|||||||||
M6|||GND||||||||||||
M7|||VCCINT||||||||1.2||||
M8||IOBM|IO_L40P_2|UNUSED||2|||||||||
M9|||VCCAUX||||||||2.5||||
M10||IOBM|IO_L22P_2|UNUSED||2|||||||||
M11||IOBM|IO_L15P_2|UNUSED||2|||||||||
M12|||VCCINT||||||||1.2||||
M13||IOBS|IO_L61N_1|UNUSED||1|||||||||
M14||IOBM|IO_L53P_1|UNUSED||1|||||||||
M15|||VCCO_1|||1|||||2.50||||
M16||IOBM|IO_L47P_FWE_B_M1DQ0_1|UNUSED||1|||||||||
M17|||GND||||||||||||
M18|GPIO<1>|IOB|IO_L47N_LDC_M1DQ1_1|OUTPUT|LVCMOS25*|1|12|SLOW||||LOCATED|NO|NONE|
N1||IOBS|IO_L35N_M3DQ11_3|UNUSED||3|||||||||
N2||IOBM|IO_L35P_M3DQ10_3|UNUSED||3|||||||||
N3||IOBS|IO_L1N_VREF_3|UNUSED||3|||||||||
N4||IOBM|IO_L1P_3|UNUSED||3|||||||||
N5||IOBM|IO_L64P_D8_2|UNUSED||2|||||||||
N6||IOBM|IO_L47P_2|UNUSED||2|||||||||
N7||IOBM|IO_L44P_2|UNUSED||2|||||||||
N8||IOBS|IO_L40N_2|UNUSED||2|||||||||
N9||IOBS|IO_L22N_2|UNUSED||2|||||||||
N10||IOBM|IO_L20P_2|UNUSED||2|||||||||
N11||IOBS|IO_L15N_2|UNUSED||2|||||||||
N12||IOBM|IO_L13P_M1_2|UNUSED||2|||||||||
N13|||GND||||||||||||
N14||IOBS|IO_L53N_VREF_1|UNUSED||1|||||||||
N15||IOBM|IO_L50P_M1UDQS_1|UNUSED||1|||||||||
N16||IOBS|IO_L50N_M1UDQSN_1|UNUSED||1|||||||||
N17|GPIO<0>|IOB|IO_L48P_HDC_M1DQ8_1|OUTPUT|LVCMOS25*|1|12|SLOW||||LOCATED|NO|NONE|
N18||IOBS|IO_L48N_M1DQ9_1|UNUSED||1|||||||||
P1||IOBS|IO_L34N_M3UDQSN_3|UNUSED||3|||||||||
P2||IOBM|IO_L34P_M3UDQS_3|UNUSED||3|||||||||
P3||IOBS|IO_L2N_3|UNUSED||3|||||||||
P4|BUT<0>|IOB|IO_L2P_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
P5|||VCCAUX||||||||2.5||||
P6||IOBS|IO_L64N_D9_2|UNUSED||2|||||||||
P7||IOBS|IO_L47N_2|UNUSED||2|||||||||
P8||IOBS|IO_L44N_2|UNUSED||2|||||||||
P9|||VCCO_2|||2|||||any******||||
P10|||VCCAUX||||||||2.5||||
P11||IOBS|IO_L20N_2|UNUSED||2|||||||||
P12|GPIO<7>|IOB|IO_L13N_D10_2|INPUT|LVCMOS25*|2||||NONE||LOCATED|NO|NONE|
P13|||CMPCS_B_2||||||||||||
P14|||VCCAUX||||||||2.5||||
P15||IOBM|IO_L74P_AWAKE_1|UNUSED||1|||||||||
P16||IOBS|IO_L74N_DOUT_BUSY_1|UNUSED||1|||||||||
P17||IOBM|IO_L49P_M1DQ10_1|UNUSED||1|||||||||
P18||IOBS|IO_L49N_M1DQ11_1|UNUSED||1|||||||||
R1|||GND||||||||||||
R2|||VCCO_3|||3|||||any******||||
R3||IOBM|IO_L62P_D5_2|UNUSED||2|||||||||
R4|||GND||||||||||||
R5||IOBM|IO_L48P_D7_2|UNUSED||2|||||||||
R6|||VCCO_2|||2|||||any******||||
R7||IOBM|IO_L46P_2|UNUSED||2|||||||||
R8||IOBM|IO_L31P_GCLK31_D14_2|UNUSED||2|||||||||
R9|||GND||||||||||||
R10||IOBM|IO_L29P_GCLK3_2|UNUSED||2|||||||||
R11||IOBM|IO_L16P_2|UNUSED||2|||||||||
R12|||VCCO_2|||2|||||any******||||
R13||IOBM|IO_L3P_D0_DIN_MISO_MISO1_2|UNUSED||2|||||||||
R14|||GND||||||||||||
R15||IOBM|IO_L1P_CCLK_2|UNUSED||2|||||||||
R16|||SUSPEND||||||||||||
R17|||VCCO_1|||1|||||2.50||||
R18|||GND||||||||||||
T1||IOBS|IO_L33N_M3DQ13_3|UNUSED||3|||||||||
T2||IOBM|IO_L33P_M3DQ12_3|UNUSED||3|||||||||
T3||IOBS|IO_L62N_D6_2|UNUSED||2|||||||||
T4||IOBM|IO_L63P_2|UNUSED||2|||||||||
T5||IOBS|IO_L48N_RDWR_B_VREF_2|UNUSED||2|||||||||
T6||IOBM|IO_L45P_2|UNUSED||2|||||||||
T7||IOBS|IO_L46N_2|UNUSED||2|||||||||
T8||IOBS|IO_L31N_GCLK30_D15_2|UNUSED||2|||||||||
T9||IOBM|IO_L32P_GCLK29_2|UNUSED||2|||||||||
T10||IOBS|IO_L29N_GCLK2_2|UNUSED||2|||||||||
T11||IOBS|IO_L16N_VREF_2|UNUSED||2|||||||||
T12||IOBM|IO_L19P_2|UNUSED||2|||||||||
T13||IOBS|IO_L3N_MOSI_CSI_B_MISO0_2|UNUSED||2|||||||||
T14||IOBM|IO_L12P_D1_MISO2_2|UNUSED||2|||||||||
T15||IOBS|IO_L1N_M0_CMPMISO_2|UNUSED||2|||||||||
T16|||GND||||||||||||
T17||IOBM|IO_L51P_M1DQ12_1|UNUSED||1|||||||||
T18||IOBS|IO_L51N_M1DQ13_1|UNUSED||1|||||||||
U1||IOBS|IO_L32N_M3DQ15_3|UNUSED||3|||||||||
U2||IOBM|IO_L32P_M3DQ14_3|UNUSED||3|||||||||
U3||IOBM|IO_L65P_INIT_B_2|UNUSED||2|||||||||
U4|||VCCO_2|||2|||||any******||||
U5||IOBM|IO_L49P_D3_2|UNUSED||2|||||||||
U6|||GND||||||||||||
U7||IOBM|IO_L43P_2|UNUSED||2|||||||||
U8||IOBM|IO_L41P_2|UNUSED||2|||||||||
U9|||VCCO_2|||2|||||any******||||
U10||IOBM|IO_L30P_GCLK1_D13_2|UNUSED||2|||||||||
U11||IOBM|IO_L23P_2|UNUSED||2|||||||||
U12|||GND||||||||||||
U13||IOBM|IO_L14P_D11_2|UNUSED||2|||||||||
U14|||VCCO_2|||2|||||any******||||
U15||IOBM|IO_L5P_2|UNUSED||2|||||||||
U16||IOBM|IO_L2P_CMPCLK_2|UNUSED||2|||||||||
U17||IOBM|IO_L52P_M1DQ14_1|UNUSED||1|||||||||
U18||IOBS|IO_L52N_M1DQ15_1|UNUSED||1|||||||||
V1|||GND||||||||||||
V2|||PROGRAM_B_2||||||||||||
V3||IOBS|IO_L65N_CSO_B_2|UNUSED||2|||||||||
V4||IOBS|IO_L63N_2|UNUSED||2|||||||||
V5||IOBS|IO_L49N_D4_2|UNUSED||2|||||||||
V6||IOBS|IO_L45N_2|UNUSED||2|||||||||
V7||IOBS|IO_L43N_2|UNUSED||2|||||||||
V8||IOBS|IO_L41N_VREF_2|UNUSED||2|||||||||
V9||IOBS|IO_L32N_GCLK28_2|UNUSED||2|||||||||
V10|CLK27MHz|IOB|IO_L30N_GCLK0_USERCCLK_2|INPUT|LVCMOS25*|2||||NONE||LOCATED|NO|NONE|
V11||IOBS|IO_L23N_2|UNUSED||2|||||||||
V12||IOBS|IO_L19N_2|UNUSED||2|||||||||
V13|DIPSW<3>|IOB|IO_L14N_D12_2|INPUT|LVCMOS25*|2||||NONE||LOCATED|NO|NONE|
V14||IOBS|IO_L12N_D2_MISO3_2|UNUSED||2|||||||||
V15||IOBS|IO_L5N_2|UNUSED||2|||||||||
V16||IOBS|IO_L2N_CMPMOSI_2|UNUSED||2|||||||||
V17|||DONE_2||||||||||||
V18|||GND||||||||||||
-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
* Default value.
** This default Pullup/Pulldown value can be overridden in Bitgen.
****** Special VCCO requirements may apply. Please consult the device
family datasheet for specific guideline on VCCO requirements.

195
textovhdl.par Normal file
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Release 14.7 par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
GABRIEL-E5400:: Wed Jun 08 11:35:46 2022
par -w -intstyle ise -ol high -mt off textovhdl_map.ncd textovhdl.ncd
textovhdl.pcf
Constraints file: textovhdl.pcf.
Loading device for application Rf_Device from file '6slx16.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\.
"textovhdl" is an NCD, version 3.2, device xc6slx16, package csg324, speed -2
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
Device speed data version: "PRODUCTION 1.23 2013-10-13".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 32 out of 18,224 1%
Number used as Flip Flops: 32
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 31 out of 9,112 1%
Number used as logic: 29 out of 9,112 1%
Number using O6 output only: 14
Number using O5 output only: 11
Number using O5 and O6: 4
Number used as ROM: 0
Number used as Memory: 0 out of 2,176 0%
Number used exclusively as route-thrus: 2
Number with same-slice register load: 0
Number with same-slice carry load: 2
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 11 out of 2,278 1%
Number of MUXCYs used: 20 out of 4,556 1%
Number of LUT Flip Flop pairs used: 31
Number with an unused Flip Flop: 1 out of 31 3%
Number with an unused LUT: 0 out of 31 0%
Number of fully used LUT-FF pairs: 30 out of 31 96%
Number of slice register sites lost
to control set restrictions: 0 out of 18,224 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 17 out of 232 7%
Number of LOCed IOBs: 17 out of 17 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 32 0%
Number of RAMB8BWERs: 0 out of 64 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 2 out of 16 12%
Number used as BUFGs: 2
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 0 out of 248 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 248 0%
Number of OLOGIC2/OSERDES2s: 0 out of 248 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 32 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 2 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 4 secs
Finished initial Timing Analysis. REAL time: 4 secs
WARNING:Par:288 - The signal BUT<2>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal BUT<3>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO<3>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO<4>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO<5>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO<6>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO<7>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DIPSW<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DIPSW<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DIPSW<2>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DIPSW<3>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal BUT<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal BUT<1>_IBUF has no load. PAR will not attempt to route this signal.
Starting Router
Phase 1 : 119 unrouted; REAL time: 4 secs
Phase 2 : 93 unrouted; REAL time: 4 secs
Phase 3 : 4 unrouted; REAL time: 4 secs
Phase 4 : 4 unrouted; (Par is working to improve performance) REAL time: 5 secs
Updating file: textovhdl.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 5 secs
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 5 secs
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 5 secs
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 5 secs
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 5 secs
Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 5 secs
Total REAL time to Router completion: 5 secs
Total CPU time to Router completion: 5 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode.
Timing Score: 0 (Setup: 0, Hold: 0)
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net con | SETUP | N/A| 1.993ns| N/A| 0
taux_5_BUFG | HOLD | 0.463ns| | 0| 0
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net CLK | SETUP | N/A| 1.805ns| N/A| 0
27MHz_BUFGP | HOLD | 0.530ns| | 0| 0
----------------------------------------------------------------------------------------------------------
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 13 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 6 secs
Total CPU time to PAR completion: 6 secs
Peak Memory Usage: 305 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 15
Number of info messages: 2
Writing design to file textovhdl.ncd
PAR done!

28
textovhdl.pcf Normal file
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//! **************************************************************************
// Written by: Map P.20131013 on Wed Jun 08 11:35:43 2022
//! **************************************************************************
SCHEMATIC START;
COMP "BUT<2>" LOCATE = SITE "E4" LEVEL 1;
COMP "BUT<3>" LOCATE = SITE "F5" LEVEL 1;
COMP "GPIO<0>" LOCATE = SITE "N17" LEVEL 1;
COMP "GPIO<1>" LOCATE = SITE "M18" LEVEL 1;
COMP "GPIO<2>" LOCATE = SITE "A3" LEVEL 1;
COMP "GPIO<3>" LOCATE = SITE "L15" LEVEL 1;
COMP "GPIO<4>" LOCATE = SITE "F15" LEVEL 1;
PIN GPIO<4>_pin<0> = BEL "GPIO<4>" PINNAME PAD;
PIN "GPIO<4>_pin<0>" CLOCK_DEDICATED_ROUTE = FALSE;
COMP "GPIO<5>" LOCATE = SITE "B4" LEVEL 1;
COMP "GPIO<6>" LOCATE = SITE "F13" LEVEL 1;
PIN GPIO<6>_pin<0> = BEL "GPIO<6>" PINNAME PAD;
PIN "GPIO<6>_pin<0>" CLOCK_DEDICATED_ROUTE = FALSE;
COMP "GPIO<7>" LOCATE = SITE "P12" LEVEL 1;
COMP "DIPSW<0>" LOCATE = SITE "D14" LEVEL 1;
COMP "DIPSW<1>" LOCATE = SITE "E12" LEVEL 1;
COMP "CLK27MHz" LOCATE = SITE "V10" LEVEL 1;
COMP "DIPSW<2>" LOCATE = SITE "F12" LEVEL 1;
COMP "DIPSW<3>" LOCATE = SITE "V13" LEVEL 1;
COMP "BUT<0>" LOCATE = SITE "P4" LEVEL 1;
COMP "BUT<1>" LOCATE = SITE "F6" LEVEL 1;
SCHEMATIC END;

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vhdl work "textovhdl.vhd"

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE twReport [
<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
twDebug*, twFoot?, twClientInfo?)>
<!ATTLIST twReport version CDATA "10,4">
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
<!ELEMENT twExecVer (#PCDATA)>
<!ELEMENT twCopyright (#PCDATA)>
<!ELEMENT twCmdLine (#PCDATA)>
<!ELEMENT twDesign (#PCDATA)>
<!ELEMENT twPCF (#PCDATA)>
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
<!ELEMENT twDevName (#PCDATA)>
<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
<!ELEMENT twSpeedGrade (#PCDATA)>
<!ELEMENT twSpeedVer (#PCDATA)>
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
<!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
<!ELEMENT twItemLimit (#PCDATA)>
<!ELEMENT twUnconst EMPTY>
<!ELEMENT twUnconstLimit (#PCDATA)>
<!ELEMENT twEnvVar EMPTY>
<!ATTLIST twEnvVar name CDATA #REQUIRED>
<!ATTLIST twEnvVar description CDATA #REQUIRED>
<!ELEMENT twWarn (#PCDATA)>
<!ELEMENT twInfo (#PCDATA)>
<!ELEMENT twDebug (#PCDATA)>
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
<!ELEMENT twProc (#PCDATA)>
<!ELEMENT twTemp (#PCDATA)>
<!ELEMENT twVolt (#PCDATA)>
<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twCycles (twSigConn+)>
<!ATTLIST twCycles twNum CDATA #REQUIRED>
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
<!ELEMENT twSig (#PCDATA)>
<!ELEMENT twDriver (#PCDATA)>
<!ELEMENT twLoad (#PCDATA)>
<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* | (twPathRpt*, twRacePathRpt?) | twNetRpt* | twClkSkewLimit*))>
<!ATTLIST twConst twConstType (NET |
NETDELAY |
NETSKEW |
PATH |
DEFPERIOD |
UNCONSTPATH |
DEFPATH |
PATH2SETUP |
UNCONSTPATH2SETUP |
PATHCLASS |
PATHDELAY |
PERIOD |
FREQUENCY |
PATHBLOCK |
OFFSET |
OFFSETIN |
OFFSETINCLOCK |
UNCONSTOFFSETINCLOCK |
OFFSETINDELAY |
OFFSETINMOD |
OFFSETOUT |
OFFSETOUTCLOCK |
UNCONSTOFFSETOUTCLOCK |
OFFSETOUTDELAY |
OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
twEndPtCnt?,
twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
<!ELEMENT twConstName (#PCDATA)>
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
<!ATTLIST twConstHead uID CDATA #IMPLIED>
<!ELEMENT twItemCnt (#PCDATA)>
<!ELEMENT twErrCnt (#PCDATA)>
<!ELEMENT twErrCntEndPt (#PCDATA)>
<!ELEMENT twErrCntSetup (#PCDATA)>
<!ELEMENT twErrCntHold (#PCDATA)>
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
<!ELEMENT twEndPtCnt (#PCDATA)>
<!ELEMENT twPathErrCnt (#PCDATA)>
<!ELEMENT twMinPer (#PCDATA) >
<!ELEMENT twFootnote EMPTY>
<!ATTLIST twFootnote number CDATA #REQUIRED>
<!ELEMENT twMaxDel (#PCDATA)>
<!ELEMENT twMaxFreq (#PCDATA)>
<!ELEMENT twMinOff (#PCDATA)>
<!ELEMENT twMaxOff (#PCDATA)>
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
<!ELEMENT twTIGName (#PCDATA)>
<!ELEMENT twInstantiated (#PCDATA)>
<!ELEMENT twBlocked (#PCDATA)>
<!ELEMENT twRacePathRpt (twRacePath+)>
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
twSimpleMinPath CDATA #IMPLIED>
<!ELEMENT twTotDel (#PCDATA)>
<!ELEMENT twSrc (#PCDATA)>
<!ATTLIST twSrc BELType CDATA #IMPLIED>
<!ELEMENT twDest (#PCDATA)>
<!ATTLIST twDest BELType CDATA #IMPLIED>
<!ELEMENT twDel (#PCDATA)>
<!ELEMENT twSUTime (#PCDATA)>
<!ELEMENT twTotPathDel (#PCDATA)>
<!ELEMENT twClkSkew (#PCDATA)>
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
<!ELEMENT twSlack (#PCDATA)>
<!ELEMENT twDelConst (#PCDATA)>
<!ELEMENT tw2Phase EMPTY>
<!ELEMENT twClkUncert (#PCDATA)>
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
fDCMJit CDATA #IMPLIED
fPhaseErr CDATA #IMPLIED
sEqu CDATA #IMPLIED>
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
<!ELEMENT twPathRptBanner (#PCDATA)>
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
<!ELEMENT twOff (#PCDATA)>
<!ELEMENT twGuaranteed EMPTY>
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
<!ELEMENT twClkDel (#PCDATA)>
<!ELEMENT twClkSrc (#PCDATA)>
<!ELEMENT twClkDest (#PCDATA)>
<!ELEMENT twGuarInSetup (#PCDATA)>
<!ELEMENT twOffSrc (#PCDATA)>
<!ELEMENT twOffDest (#PCDATA)>
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
<!ELEMENT twDataDel (#PCDATA)>
<!ELEMENT twDataSrc (#PCDATA)>
<!ELEMENT twDataDest (#PCDATA)>
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twLogLvls (#PCDATA)>
<!ELEMENT twSrcSite (#PCDATA)>
<!ELEMENT twSrcClk (#PCDATA)>
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
<!ELEMENT twDelInfo (#PCDATA)>
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twSite (#PCDATA)>
<!ELEMENT twDelType (#PCDATA)>
<!ELEMENT twFanCnt (#PCDATA)>
<!ELEMENT twComp (#PCDATA)>
<!ELEMENT twNet (#PCDATA)>
<!ELEMENT twBEL (#PCDATA)>
<!ELEMENT twLogDel (#PCDATA)>
<!ELEMENT twRouteDel (#PCDATA)>
<!ELEMENT twDestClk (#PCDATA)>
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPctLog (#PCDATA)>
<!ELEMENT twPctRoute (#PCDATA)>
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
<!ELEMENT twTimeConst (#PCDATA)>
<!ELEMENT twAbsSlack (#PCDATA)>
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
<!ELEMENT twSkew (#PCDATA)>
<!ELEMENT twDetNet (twNetDel*)>
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
<!ELEMENT twNetDelInfo (#PCDATA)>
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twDetSkewNet (twNetSkew*)>
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
<!ELEMENT twClkSkewLimit EMPTY>
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
<!ELEMENT twConstRollupTable (twConstRollup*)>
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
<!ELEMENT twConstRollup EMPTY>
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
<!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
<!ELEMENT twConstList (twConstListItem)*>
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
<!ELEMENT twNotMet EMPTY>
<!ELEMENT twReqVal (#PCDATA)>
<!ELEMENT twActVal (#PCDATA)>
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
<!ELEMENT twConstStats (twConstName)>
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
<!ELEMENT twConstData EMPTY>
<!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
best CDATA #IMPLIED requested CDATA #IMPLIED
errors CDATA #IMPLIED
score CDATA #IMPLIED>
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
<!ELEMENT twTimeGrpName (#PCDATA)>
<!ELEMENT twCompList (twCompName+)>
<!ELEMENT twCompName (#PCDATA)>
<!ELEMENT twSigList (twSigName+)>
<!ELEMENT twSigName (#PCDATA)>
<!ELEMENT twBELList (twBELName+)>
<!ELEMENT twBELName (#PCDATA)>
<!ELEMENT twBlockList (twBlockName+)>
<!ELEMENT twBlockName (#PCDATA)>
<!ELEMENT twMacList (twMacName+)>
<!ELEMENT twMacName (#PCDATA)>
<!ELEMENT twPinList (twPinName+)>
<!ELEMENT twPinName (#PCDATA)>
<!ELEMENT twUnmetConstCnt (#PCDATA)>
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
<!ELEMENT twSU2ClkTime (#PCDATA)>
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twH2ClkTime (#PCDATA)>
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
<!ELEMENT twClk2Pad (twDest, twTime)>
<!ELEMENT twTime (#PCDATA)>
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
<!ELEMENT twClk2Out EMPTY>
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
<!ELEMENT twRiseRise (#PCDATA)>
<!ELEMENT twFallRise (#PCDATA)>
<!ELEMENT twRiseFall (#PCDATA)>
<!ELEMENT twFallFall (#PCDATA)>
<!ELEMENT twPad2PadList (twPad2Pad+)>
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffOutTblRow EMPTY>
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
<!ELEMENT twNonDedClk (#PCDATA)>
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
<!ELEMENT twScore (#PCDATA)>
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
<!ELEMENT twPathCnt (#PCDATA)>
<!ELEMENT twNetCnt (#PCDATA)>
<!ELEMENT twConnCnt (#PCDATA)>
<!ELEMENT twPct (#PCDATA)>
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
<!ELEMENT twMaxCombDel (#PCDATA)>
<!ELEMENT twMaxFromToDel (#PCDATA)>
<!ELEMENT twMaxNetDel (#PCDATA)>
<!ELEMENT twMaxNetSkew (#PCDATA)>
<!ELEMENT twMaxInAfterClk (#PCDATA)>
<!ELEMENT twMinInBeforeClk (#PCDATA)>
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
<!ELEMENT twMinOutAfterClk (#PCDATA)>
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
<!ELEMENT twTimestamp (#PCDATA)>
<!ELEMENT twFootnoteExplanation EMPTY>
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
<!ELEMENT twClientName (#PCDATA)>
<!ELEMENT twAttrList (twAttrListItem)*>
<!ELEMENT twAttrListItem (twName, twValue*)>
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net contaux_5_BUFG</twConstName><twConstData type="SETUP" best="1.993" units="ns" score="0"/><twConstData type="HOLD" slack="0.463" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net CLK27MHz_BUFGP</twConstName><twConstData type="SETUP" best="1.805" units="ns" score="0"/><twConstData type="HOLD" slack="0.530" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="6">0</twUnmetConstCnt><twInfo anchorID="7">INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</twInfo></twSumRpt></twBody></twReport>

0
textovhdl.stx Normal file
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textovhdl.syr Normal file
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Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.13 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.13 secs
--> Reading design: textovhdl.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Parsing
3) HDL Elaboration
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
5.1) Advanced HDL Synthesis Report
6) Low Level Synthesis
7) Partition Report
8) Design Summary
8.1) Primitive and Black Box Usage
8.2) Device utilization summary
8.3) Partition Resource Summary
8.4) Timing Report
8.4.1) Clock Information
8.4.2) Asynchronous Control Signals Information
8.4.3) Timing Summary
8.4.4) Timing Details
8.4.5) Cross Clock Domains Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "textovhdl.prj"
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "textovhdl"
Output Format : NGC
Target Device : xc6slx16-2-csg324
---- Source Options
Top Module Name : textovhdl
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Shift Register Extraction : YES
ROM Style : Auto
Resource Sharing : YES
Asynchronous To Synchronous : NO
Shift Register Minimum Size : 2
Use DSP Block : Auto
Automatic Register Balancing : No
---- Target Options
LUT Combining : Auto
Reduce Control Sets : Auto
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 16
Register Duplication : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Auto
Use Synchronous Set : Auto
Use Synchronous Reset : Auto
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Power Reduction : NO
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
DSP48 Utilization Ratio : 100
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Parsing *
=========================================================================
Parsing VHDL file "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" into library work
Parsing entity <textovhdl>.
Parsing architecture <comportamento> of entity <textovhdl>.
Parsing entity <CONTBCD_C>.
Parsing architecture <comportamento> of entity <contbcd_c>.
Parsing entity <display>.
Parsing architecture <comportamento> of entity <display>.
=========================================================================
* HDL Elaboration *
=========================================================================
Elaborating entity <textovhdl> (architecture <comportamento>) from library <work>.
Elaborating entity <display> (architecture <comportamento>) from library <work>.
WARNING:HDLCompiler:1127 - "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 64: Assignment to clk100k ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 65: Assignment to clk25k ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 66: Assignment to clk621ms ignored, since the identifier is never used
WARNING:HDLCompiler:634 - "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 20: Net <num7[3]> does not have a driver.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <textovhdl>.
Related source file is "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd".
WARNING:Xst:647 - Input <BUT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DIPSW> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Always blocking tristate driving signal <GPIO<7>> is removed.
Always blocking tristate driving signal <GPIO<6>> is removed.
Always blocking tristate driving signal <GPIO<5>> is removed.
Always blocking tristate driving signal <GPIO<4>> is removed.
Always blocking tristate driving signal <GPIO<3>> is removed.
Always blocking tristate driving signal <GPIO<2>> is removed.
Always blocking tristate driving signal <GPIO<1>> is removed.
Always blocking tristate driving signal <GPIO<0>> is removed.
WARNING:Xst:653 - Signal <num7> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <num6> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <num5> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <num4> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <num3> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <num2> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <num1> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <num0> is used but never assigned. This sourceless signal will be automatically connected to value GND.
Found 24-bit register for signal <contaux>.
Found 24-bit adder for signal <contaux[23]_GND_5_o_add_5_OUT> created at line 60.
Found 1-bit tristate buffer for signal <LEDS<3>> created at line 37
Found 1-bit tristate buffer for signal <LEDS<2>> created at line 37
Found 1-bit tristate buffer for signal <LEDS<1>> created at line 37
Found 1-bit tristate buffer for signal <LEDS<0>> created at line 37
Summary:
inferred 1 Adder/Subtractor(s).
inferred 24 D-type flip-flop(s).
inferred 4 Tristate(s).
Unit <textovhdl> synthesized.
Synthesizing Unit <display>.
Related source file is "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd".
Found 1-bit register for signal <configur>.
Found 16-bit register for signal <palavra>.
Found 9-bit register for signal <EN>.
Found 9-bit adder for signal <EN[8]_GND_18_o_add_37_OUT> created at line 179.
Found 8x4-bit Read Only RAM for signal <proxdisplay>
Summary:
inferred 1 RAM(s).
inferred 1 Adder/Subtractor(s).
inferred 26 D-type flip-flop(s).
inferred 4 Multiplexer(s).
Unit <display> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# RAMs : 1
8x4-bit single-port Read Only RAM : 1
# Adders/Subtractors : 2
24-bit adder : 1
9-bit adder : 1
# Registers : 4
1-bit register : 1
16-bit register : 1
24-bit register : 1
9-bit register : 1
# Multiplexers : 4
16-bit 2-to-1 multiplexer : 4
# Tristates : 4
1-bit tristate buffer : 4
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Synthesizing (advanced) Unit <display>.
The following registers are absorbed into counter <EN>: 1 register on signal <EN>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_proxdisplay> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
-----------------------------------------------------------------------
| ram_type | Distributed | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 8-word x 4-bit | |
| weA | connected to signal <GND> | high |
| addrA | connected to signal <EN<7:5>> | |
| diA | connected to signal <GND> | |
| doA | connected to signal <proxdisplay> | |
-----------------------------------------------------------------------
Unit <display> synthesized (advanced).
Synthesizing (advanced) Unit <textovhdl>.
The following registers are absorbed into counter <contaux>: 1 register on signal <contaux>.
Unit <textovhdl> synthesized (advanced).
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# RAMs : 1
8x4-bit single-port distributed Read Only RAM : 1
# Counters : 2
24-bit up counter : 1
9-bit up counter : 1
# Registers : 17
Flip-Flops : 17
# Multiplexers : 4
16-bit 2-to-1 multiplexer : 4
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
WARNING:Xst:2677 - Node <contaux_6> of sequential type is unconnected in block <textovhdl>.
WARNING:Xst:2677 - Node <contaux_7> of sequential type is unconnected in block <textovhdl>.
WARNING:Xst:2677 - Node <contaux_8> of sequential type is unconnected in block <textovhdl>.
WARNING:Xst:2677 - Node <contaux_9> of sequential type is unconnected in block <textovhdl>.
WARNING:Xst:2677 - Node <contaux_10> of sequential type is unconnected in block <textovhdl>.
WARNING:Xst:2677 - Node <contaux_11> of sequential type is unconnected in block <textovhdl>.
WARNING:Xst:2677 - Node <contaux_12> of sequential type is unconnected in block <textovhdl>.
WARNING:Xst:2677 - Node <contaux_13> of sequential type is unconnected in block <textovhdl>.
WARNING:Xst:2677 - Node <contaux_14> of sequential type is unconnected in block <textovhdl>.
WARNING:Xst:2677 - Node <contaux_15> of sequential type is unconnected in block <textovhdl>.
WARNING:Xst:2677 - Node <contaux_16> of sequential type is unconnected in block <textovhdl>.
WARNING:Xst:2677 - Node <contaux_17> of sequential type is unconnected in block <textovhdl>.
WARNING:Xst:2677 - Node <contaux_18> of sequential type is unconnected in block <textovhdl>.
WARNING:Xst:2677 - Node <contaux_19> of sequential type is unconnected in block <textovhdl>.
WARNING:Xst:2677 - Node <contaux_20> of sequential type is unconnected in block <textovhdl>.
WARNING:Xst:2677 - Node <contaux_21> of sequential type is unconnected in block <textovhdl>.
WARNING:Xst:2677 - Node <contaux_22> of sequential type is unconnected in block <textovhdl>.
WARNING:Xst:2677 - Node <contaux_23> of sequential type is unconnected in block <textovhdl>.
Optimizing unit <textovhdl> ...
Optimizing unit <display> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block textovhdl, actual ratio is 0.
Final Macro Processing ...
=========================================================================
Final Register Report
Macro Statistics
# Registers : 32
Flip-Flops : 32
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Design Summary *
=========================================================================
Top Level Output File Name : textovhdl.ngc
Primitive and Black Box Usage:
------------------------------
# BELS : 64
# GND : 1
# INV : 4
# LUT1 : 13
# LUT2 : 5
# LUT3 : 1
# LUT4 : 1
# LUT5 : 5
# LUT6 : 5
# MUXCY : 13
# VCC : 1
# XORCY : 15
# FlipFlops/Latches : 32
# FD : 15
# FD_1 : 17
# Clock Buffers : 2
# BUFG : 1
# BUFGP : 1
# IO Buffers : 7
# OBUF : 3
# OBUFT : 4
Device utilization summary:
---------------------------
Selected Device : 6slx16csg324-2
Slice Logic Utilization:
Number of Slice Registers: 32 out of 18224 0%
Number of Slice LUTs: 34 out of 9112 0%
Number used as Logic: 34 out of 9112 0%
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 34
Number with an unused Flip Flop: 2 out of 34 5%
Number with an unused LUT: 0 out of 34 0%
Number of fully used LUT-FF pairs: 32 out of 34 94%
Number of unique control sets: 3
IO Utilization:
Number of IOs: 21
Number of bonded IOBs: 8 out of 232 3%
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: 2 out of 16 12%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
Timing Report
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
CLK27MHz | BUFGP | 6 |
contaux_5 | BUFG | 26 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -2
Minimum period: 2.579ns (Maximum Frequency: 387.785MHz)
Minimum input arrival time before clock: No path found
Maximum output required time after clock: 5.607ns
Maximum combinational path delay: No path found
Timing Details:
---------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'CLK27MHz'
Clock period: 2.049ns (frequency: 488.043MHz)
Total number of paths / destination ports: 21 / 6
-------------------------------------------------------------------------
Delay: 2.049ns (Levels of Logic = 7)
Source: contaux_0 (FF)
Destination: contaux_5 (FF)
Source Clock: CLK27MHz rising
Destination Clock: CLK27MHz rising
Data Path: contaux_0 to contaux_5
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 1 0.525 0.681 contaux_0 (contaux_0)
INV:I->O 1 0.255 0.000 Mcount_contaux_lut<0>_INV_0 (Mcount_contaux_lut<0>)
MUXCY:S->O 1 0.215 0.000 Mcount_contaux_cy<0> (Mcount_contaux_cy<0>)
MUXCY:CI->O 1 0.023 0.000 Mcount_contaux_cy<1> (Mcount_contaux_cy<1>)
MUXCY:CI->O 1 0.023 0.000 Mcount_contaux_cy<2> (Mcount_contaux_cy<2>)
MUXCY:CI->O 1 0.023 0.000 Mcount_contaux_cy<3> (Mcount_contaux_cy<3>)
MUXCY:CI->O 0 0.023 0.000 Mcount_contaux_cy<4> (Mcount_contaux_cy<4>)
XORCY:CI->O 1 0.206 0.000 Mcount_contaux_xor<5> (Result<5>)
FD:D 0.074 contaux_5
----------------------------------------
Total 2.049ns (1.368ns logic, 0.681ns route)
(66.8% logic, 33.2% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'contaux_5'
Clock period: 2.579ns (frequency: 387.785MHz)
Total number of paths / destination ports: 117 / 26
-------------------------------------------------------------------------
Delay: 2.579ns (Levels of Logic = 6)
Source: UDISP/EN_4 (FF)
Destination: UDISP/EN_8 (FF)
Source Clock: contaux_5 falling
Destination Clock: contaux_5 falling
Data Path: UDISP/EN_4 to UDISP/EN_8
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 18 0.525 1.235 UDISP/EN_4 (UDISP/EN_4)
LUT1:I0->O 1 0.254 0.000 UDISP/Mcount_EN_cy<4>_rt (UDISP/Mcount_EN_cy<4>_rt)
MUXCY:S->O 1 0.215 0.000 UDISP/Mcount_EN_cy<4> (UDISP/Mcount_EN_cy<4>)
MUXCY:CI->O 1 0.023 0.000 UDISP/Mcount_EN_cy<5> (UDISP/Mcount_EN_cy<5>)
MUXCY:CI->O 1 0.023 0.000 UDISP/Mcount_EN_cy<6> (UDISP/Mcount_EN_cy<6>)
MUXCY:CI->O 0 0.023 0.000 UDISP/Mcount_EN_cy<7> (UDISP/Mcount_EN_cy<7>)
XORCY:CI->O 1 0.206 0.000 UDISP/Mcount_EN_xor<8> (UDISP/Result<8>)
FD:D 0.074 UDISP/EN_8
----------------------------------------
Total 2.579ns (1.344ns logic, 1.235ns route)
(52.1% logic, 47.9% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'contaux_5'
Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset: 5.607ns (Levels of Logic = 2)
Source: UDISP/EN_4 (FF)
Destination: GPIO<1> (PAD)
Source Clock: contaux_5 falling
Data Path: UDISP/EN_4 to GPIO<1>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 18 0.525 1.234 UDISP/EN_4 (UDISP/EN_4)
INV:I->O 1 0.255 0.681 UDISP/CS1_INV_0 (GPIO_1_OBUF)
OBUF:I->O 2.912 GPIO_1_OBUF (GPIO<1>)
----------------------------------------
Total 5.607ns (3.692ns logic, 1.915ns route)
(65.8% logic, 34.2% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK27MHz'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 4.162ns (Levels of Logic = 1)
Source: contaux_5 (FF)
Destination: GPIO<0> (PAD)
Source Clock: CLK27MHz rising
Data Path: contaux_5 to GPIO<0>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 2 0.525 0.725 contaux_5 (contaux_5)
OBUF:I->O 2.912 GPIO_0_OBUF (GPIO<0>)
----------------------------------------
Total 4.162ns (3.437ns logic, 0.725ns route)
(82.6% logic, 17.4% route)
=========================================================================
Cross Clock Domains Report:
--------------------------
Clock to Setup on destination clock CLK27MHz
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK27MHz | 2.049| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock contaux_5
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
contaux_5 | | | 2.579| |
---------------+---------+---------+---------+---------+
=========================================================================
Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 6.79 secs
-->
Total memory usage is 258824 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 32 ( 0 filtered)
Number of infos : 1 ( 0 filtered)

62
textovhdl.twr Normal file
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@@ -0,0 +1,62 @@
--------------------------------------------------------------------------------
Release 14.7 Trace (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 2
-n 3 -fastpaths -xml textovhdl.twx textovhdl.ncd -o textovhdl.twr textovhdl.pcf
-ucf restricoes.ucf
Design file: textovhdl.ncd
Physical constraint file: textovhdl.pcf
Device,package,speed: xc6slx16,csg324,C,-2 (PRODUCTION 1.23 2013-10-13)
Report level: verbose report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock CLK27MHz to Pad
------------+-----------------+------------+-----------------+------------+------------------+--------+
|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
------------+-----------------+------------+-----------------+------------+------------------+--------+
GPIO<0> | 9.967(R)| SLOW | 4.260(R)| FAST |CLK27MHz_BUFGP | 0.000|
------------+-----------------+------------+-----------------+------------+------------------+--------+
Clock to Setup on destination clock CLK27MHz
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK27MHz | 1.805| | | |
---------------+---------+---------+---------+---------+
Analysis completed Wed Jun 08 11:35:59 2022
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 218 MB

339
textovhdl.twx Normal file
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@@ -0,0 +1,339 @@
<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE twReport [
<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
twDebug*, twFoot?, twClientInfo?)>
<!ATTLIST twReport version CDATA "10,4">
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
<!ELEMENT twExecVer (#PCDATA)>
<!ELEMENT twCopyright (#PCDATA)>
<!ELEMENT twCmdLine (#PCDATA)>
<!ELEMENT twDesign (#PCDATA)>
<!ELEMENT twPCF (#PCDATA)>
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
<!ELEMENT twDevName (#PCDATA)>
<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
<!ELEMENT twSpeedGrade (#PCDATA)>
<!ELEMENT twSpeedVer (#PCDATA)>
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
<!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
<!ELEMENT twItemLimit (#PCDATA)>
<!ELEMENT twUnconst EMPTY>
<!ELEMENT twUnconstLimit (#PCDATA)>
<!ELEMENT twEnvVar EMPTY>
<!ATTLIST twEnvVar name CDATA #REQUIRED>
<!ATTLIST twEnvVar description CDATA #REQUIRED>
<!ELEMENT twWarn (#PCDATA)>
<!ELEMENT twInfo (#PCDATA)>
<!ELEMENT twDebug (#PCDATA)>
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
<!ELEMENT twProc (#PCDATA)>
<!ELEMENT twTemp (#PCDATA)>
<!ELEMENT twVolt (#PCDATA)>
<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twCycles (twSigConn+)>
<!ATTLIST twCycles twNum CDATA #REQUIRED>
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
<!ELEMENT twSig (#PCDATA)>
<!ELEMENT twDriver (#PCDATA)>
<!ELEMENT twLoad (#PCDATA)>
<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* | (twPathRpt*, twRacePathRpt?) | twNetRpt* | twClkSkewLimit*))>
<!ATTLIST twConst twConstType (NET |
NETDELAY |
NETSKEW |
PATH |
DEFPERIOD |
UNCONSTPATH |
DEFPATH |
PATH2SETUP |
UNCONSTPATH2SETUP |
PATHCLASS |
PATHDELAY |
PERIOD |
FREQUENCY |
PATHBLOCK |
OFFSET |
OFFSETIN |
OFFSETINCLOCK |
UNCONSTOFFSETINCLOCK |
OFFSETINDELAY |
OFFSETINMOD |
OFFSETOUT |
OFFSETOUTCLOCK |
UNCONSTOFFSETOUTCLOCK |
OFFSETOUTDELAY |
OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
twEndPtCnt?,
twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
<!ELEMENT twConstName (#PCDATA)>
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
<!ATTLIST twConstHead uID CDATA #IMPLIED>
<!ELEMENT twItemCnt (#PCDATA)>
<!ELEMENT twErrCnt (#PCDATA)>
<!ELEMENT twErrCntEndPt (#PCDATA)>
<!ELEMENT twErrCntSetup (#PCDATA)>
<!ELEMENT twErrCntHold (#PCDATA)>
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
<!ELEMENT twEndPtCnt (#PCDATA)>
<!ELEMENT twPathErrCnt (#PCDATA)>
<!ELEMENT twMinPer (#PCDATA) >
<!ELEMENT twFootnote EMPTY>
<!ATTLIST twFootnote number CDATA #REQUIRED>
<!ELEMENT twMaxDel (#PCDATA)>
<!ELEMENT twMaxFreq (#PCDATA)>
<!ELEMENT twMinOff (#PCDATA)>
<!ELEMENT twMaxOff (#PCDATA)>
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
<!ELEMENT twTIGName (#PCDATA)>
<!ELEMENT twInstantiated (#PCDATA)>
<!ELEMENT twBlocked (#PCDATA)>
<!ELEMENT twRacePathRpt (twRacePath+)>
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
twSimpleMinPath CDATA #IMPLIED>
<!ELEMENT twTotDel (#PCDATA)>
<!ELEMENT twSrc (#PCDATA)>
<!ATTLIST twSrc BELType CDATA #IMPLIED>
<!ELEMENT twDest (#PCDATA)>
<!ATTLIST twDest BELType CDATA #IMPLIED>
<!ELEMENT twDel (#PCDATA)>
<!ELEMENT twSUTime (#PCDATA)>
<!ELEMENT twTotPathDel (#PCDATA)>
<!ELEMENT twClkSkew (#PCDATA)>
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
<!ELEMENT twSlack (#PCDATA)>
<!ELEMENT twDelConst (#PCDATA)>
<!ELEMENT tw2Phase EMPTY>
<!ELEMENT twClkUncert (#PCDATA)>
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
fDCMJit CDATA #IMPLIED
fPhaseErr CDATA #IMPLIED
sEqu CDATA #IMPLIED>
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
<!ELEMENT twPathRptBanner (#PCDATA)>
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
<!ELEMENT twOff (#PCDATA)>
<!ELEMENT twGuaranteed EMPTY>
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
<!ELEMENT twClkDel (#PCDATA)>
<!ELEMENT twClkSrc (#PCDATA)>
<!ELEMENT twClkDest (#PCDATA)>
<!ELEMENT twGuarInSetup (#PCDATA)>
<!ELEMENT twOffSrc (#PCDATA)>
<!ELEMENT twOffDest (#PCDATA)>
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
<!ELEMENT twDataDel (#PCDATA)>
<!ELEMENT twDataSrc (#PCDATA)>
<!ELEMENT twDataDest (#PCDATA)>
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twLogLvls (#PCDATA)>
<!ELEMENT twSrcSite (#PCDATA)>
<!ELEMENT twSrcClk (#PCDATA)>
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
<!ELEMENT twDelInfo (#PCDATA)>
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twSite (#PCDATA)>
<!ELEMENT twDelType (#PCDATA)>
<!ELEMENT twFanCnt (#PCDATA)>
<!ELEMENT twComp (#PCDATA)>
<!ELEMENT twNet (#PCDATA)>
<!ELEMENT twBEL (#PCDATA)>
<!ELEMENT twLogDel (#PCDATA)>
<!ELEMENT twRouteDel (#PCDATA)>
<!ELEMENT twDestClk (#PCDATA)>
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPctLog (#PCDATA)>
<!ELEMENT twPctRoute (#PCDATA)>
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
<!ELEMENT twTimeConst (#PCDATA)>
<!ELEMENT twAbsSlack (#PCDATA)>
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
<!ELEMENT twSkew (#PCDATA)>
<!ELEMENT twDetNet (twNetDel*)>
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
<!ELEMENT twNetDelInfo (#PCDATA)>
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twDetSkewNet (twNetSkew*)>
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
<!ELEMENT twClkSkewLimit EMPTY>
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
<!ELEMENT twConstRollupTable (twConstRollup*)>
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
<!ELEMENT twConstRollup EMPTY>
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
<!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
<!ELEMENT twConstList (twConstListItem)*>
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
<!ELEMENT twNotMet EMPTY>
<!ELEMENT twReqVal (#PCDATA)>
<!ELEMENT twActVal (#PCDATA)>
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
<!ELEMENT twConstStats (twConstName)>
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
<!ELEMENT twConstData EMPTY>
<!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
best CDATA #IMPLIED requested CDATA #IMPLIED
errors CDATA #IMPLIED
score CDATA #IMPLIED>
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
<!ELEMENT twTimeGrpName (#PCDATA)>
<!ELEMENT twCompList (twCompName+)>
<!ELEMENT twCompName (#PCDATA)>
<!ELEMENT twSigList (twSigName+)>
<!ELEMENT twSigName (#PCDATA)>
<!ELEMENT twBELList (twBELName+)>
<!ELEMENT twBELName (#PCDATA)>
<!ELEMENT twBlockList (twBlockName+)>
<!ELEMENT twBlockName (#PCDATA)>
<!ELEMENT twMacList (twMacName+)>
<!ELEMENT twMacName (#PCDATA)>
<!ELEMENT twPinList (twPinName+)>
<!ELEMENT twPinName (#PCDATA)>
<!ELEMENT twUnmetConstCnt (#PCDATA)>
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
<!ELEMENT twSU2ClkTime (#PCDATA)>
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twH2ClkTime (#PCDATA)>
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
<!ELEMENT twClk2Pad (twDest, twTime)>
<!ELEMENT twTime (#PCDATA)>
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
<!ELEMENT twClk2Out EMPTY>
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
<!ELEMENT twRiseRise (#PCDATA)>
<!ELEMENT twFallRise (#PCDATA)>
<!ELEMENT twRiseFall (#PCDATA)>
<!ELEMENT twFallFall (#PCDATA)>
<!ELEMENT twPad2PadList (twPad2Pad+)>
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffOutTblRow EMPTY>
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
<!ELEMENT twNonDedClk (#PCDATA)>
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
<!ELEMENT twScore (#PCDATA)>
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
<!ELEMENT twPathCnt (#PCDATA)>
<!ELEMENT twNetCnt (#PCDATA)>
<!ELEMENT twConnCnt (#PCDATA)>
<!ELEMENT twPct (#PCDATA)>
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
<!ELEMENT twMaxCombDel (#PCDATA)>
<!ELEMENT twMaxFromToDel (#PCDATA)>
<!ELEMENT twMaxNetDel (#PCDATA)>
<!ELEMENT twMaxNetSkew (#PCDATA)>
<!ELEMENT twMaxInAfterClk (#PCDATA)>
<!ELEMENT twMinInBeforeClk (#PCDATA)>
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
<!ELEMENT twMinOutAfterClk (#PCDATA)>
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
<!ELEMENT twTimestamp (#PCDATA)>
<!ELEMENT twFootnoteExplanation EMPTY>
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
<!ELEMENT twClientName (#PCDATA)>
<!ELEMENT twAttrList (twAttrListItem)*>
<!ELEMENT twAttrListItem (twName, twValue*)>
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twHead anchorID="1"><twExecVer>Release 14.7 Trace (nt64)</twExecVer><twCopyright>Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 2
-n 3 -fastpaths -xml textovhdl.twx textovhdl.ncd -o textovhdl.twr textovhdl.pcf
-ucf restricoes.ucf
</twCmdLine><twDesign>textovhdl.ncd</twDesign><twDesignPath>textovhdl.ncd</twDesignPath><twPCF>textovhdl.pcf</twPCF><twPcfPath>textovhdl.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="csg324"><twDevName>xc6slx16</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-2</twSpeedGrade><twSpeedVer>PRODUCTION 1.23 2013-10-13</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:2698 - No timing constraints found, doing default enumeration.</twInfo><twInfo anchorID="3">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="4">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="5">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twDataSheet anchorID="6" twNameLen="15"><twClk2OutList anchorID="7" twDestWidth="7" twPhaseWidth="14"><twSrc>CLK27MHz</twSrc><twClk2Out twOutPad = "GPIO&lt;0&gt;" twMinTime = "4.260" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "9.967" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK27MHz_BUFGP" twClkPhase="0.000" ></twClk2Out></twClk2OutList><twClk2SUList anchorID="8" twDestWidth="8"><twDest>CLK27MHz</twDest><twClk2SU><twSrc>CLK27MHz</twSrc><twRiseRise>1.805</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twFoot><twTimestamp>Wed Jun 08 11:35:59 2022 </twTimestamp></twFoot><twClientInfo anchorID="9"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
Peak Memory Usage: 218 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>

25
textovhdl.unroutes Normal file
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@@ -0,0 +1,25 @@
Release 14.7 - par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Wed Jun 08 11:35:52 2022
All signals are completely routed.
WARNING:ParHelpers:361 - There are 13 loadless signals in this design. This design will cause Bitgen to issue DRC
warnings.
BUT<0>_IBUF
BUT<1>_IBUF
BUT<2>_IBUF
BUT<3>_IBUF
DIPSW<0>_IBUF
DIPSW<1>_IBUF
DIPSW<2>_IBUF
DIPSW<3>_IBUF
GPIO<3>_IBUF
GPIO<4>_IBUF
GPIO<5>_IBUF
GPIO<6>_IBUF
GPIO<7>_IBUF

30
textovhdl.ut Normal file
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@@ -0,0 +1,30 @@
-w
-g DebugBitstream:No
-g Binary:no
-g CRC:Enable
-g Reset_on_err:No
-g ConfigRate:2
-g ProgPin:PullUp
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullDown
-g UserID:0xFFFFFFFF
-g ExtMasterCclk_en:No
-g SPI_buswidth:1
-g TIMER_CFG:0xFFFF
-g multipin_wakeup:No
-g StartUpClk:CClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Security:None
-g DonePipe:No
-g DriveDone:No
-g en_sw_gsr:No
-g drive_awake:No
-g sw_clk:Startupclk
-g sw_gwe_cycle:5
-g sw_gts_cycle:4

125
textovhdl.vhd
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@@ -18,24 +18,6 @@ signal cont100k,contaux: std_logic_vector(23 downto 0);
signal CLK100k,clk621ms,clk25k: std_logic;
signal clkdisp,cs,din: std_logic;
signal num7,num6,num5,num4,num3,num2,num1,num0: std_logic_vector(3 downto 0);
signal EO: std_logic_vector (7 downto 0);
signal S_IR, CLR_cont_S: std_logic;
signal prox_S, atual_S: std_logic_vector(1 downto 0);
signal Q1ms, Q4ms, Q8ms: std_logic;
signal proxshift, atualshift, codigo32: std_logic_vector(31 downto 0);
signal SIshift, ENshift: std_logic;
signal proxnum7: std_logic_vector( 3 downto 0);
signal cont32TXIR: std_logic_vector(7 downto 0);
signal conttimeTXIR: std_logic_vector(11 downto 0);
signal clkcontbits, clrcontbits, contbitsigual32: std_logic;
signal EOTX8: std_logic_vector (1 downto 0);
signal EOTX12: std_logic_vector (2 downto 0);
signal clr12bits, Q900, Q450, Q55, Q165: std_logic;
signal loadshift, clkshift, Q0, outir, clk37915: std_logic;
signal proxTX, atualTX: std_logic_vector(3 downto 0);
signal proxshift32, atualshift32: std_logic_vector (31 downto 0);
signal cont37915: std_logic_vector(23 downto 0);
component display port( NUM7, NUM6, NUM5, NUM4, NUM3, NUM2, NUM1, NUM0: in std_logic_vector(3 downto 0);
CLK: in std_logic;
@@ -54,56 +36,6 @@ begin
GPIO <= "ZZZZZZZZ";
LEDS <= "ZZZZ";
--contador 8 bits de transmiss<73>o, conta at<61> 32
UT0: CONTBCD_C port map(CLK => clkcontbits, CLR => clrcontbits, UP => '1', EN => '1', ENOUT => EOTX8(0), Q => cont32TXIR(3 downto 0));
UT1: CONTBCD_C port map(CLK => clkcontbits, CLR => clrcontbits, UP => '1', EN => EOTX8(0), ENOUT => EOTX8(1), Q => cont32TXIR(7 downto 4));
contbitsigual32 <= '1' when cont32TXIR="00110010" else '0';
--contador de 12 bits transmiss<73>o, conta at<61> 900 x 10us
UT2: CONTBCD_C port map(CLK => clk100k, CLR => clr12bits, UP => '1', EN => '1', ENOUT => EOTX12(0), Q => conttimeTXIR(3 downto 0));
UT3: CONTBCD_C port map(CLK => clk100k, CLR => clr12bits, UP => '1', EN => EOTX12(0), ENOUT => EOTX12(1), Q => conttimeTXIR(7 downto 4));
UT4: CONTBCD_C port map(CLK => clk100k, CLR => clr12bits, UP => '1', EN => EOTX12(1), ENOUT => EOTX12(2), Q => conttimeTXIR(11 downto 8));
Q900 <= '1' when conttimeTXIR(11 downto 8)="1001" else '0';
Q450 <= '1' when conttimeTXIR(11 downto 4)="01000101" else '0';
Q55 <= '1' when conttimeTXIR(7 downto 0)="01010101" else '0';
Q165 <= '1' when conttimeTXIR="000101100101" else '0';
--shift register
proxshift32 <= codigo32 when loadshift='1' else '0'&atualshift32(31 downto 1);
Q0 <= atualshift32(0);
process (clkshift)
begin
if (clkshift'event and clkshift='1') then
atualshift32 <=proxshift32;
end if;
end process;
--gera 37915Hz
process(CLK27MHz)
begin
if(CLK27MHz'event and CLK27MHz = '1') then
if (cont37915 = "000000000000000000000000") then cont37915 <= "0000_0000_0000_0001_0110_0011";
else cont37915 <= cont37915-"000000000000000000000001";
end if;
end if;
end process;
process(cont37915(8))
begin
if(cont37915(8)'event and cont37915(8) = '1') then
clk37915 <= not clk37915;
end if;
end process;
proxTX <= "000"&BUT(0) when atualTX="0000" else
"00"&(not BUT(0))&'1' when atualTX="0001" else
"001"&Q900 when atualTX="0011" else
"0110" when atualTX="0010" else
"011"&(not Q450) when atualTX="0110" else
@@ -119,60 +51,6 @@ proxTX <= "000"&BUT(0) when atualTX="0000" else
UDISP: display port map(num7=>num7, num6=>num6, num5=>num5, num4=>num4, num3=>num3, num2=>num2,
num1=>num1, num0=>num0, clk=>clkdisp, cs=>cs, dout=>din);
CLR_cont_S <= atual_S(1) and atual_S(0);
prox_S <= '0'&(not S_IR) when atual_S="00" else
"11" when atual_S="01" else
"10" when atual_S="11" else
(not S_IR & '0');
proxshift <= atualshift when ENshift = '0' else
SIshift & atualshift (31 downto 1);
process (S_IR)
begin
if (S_IR'event and S_IR='0') then
atualshift <= proxshift;
end if;
end process;
process (Q8ms)
begin
if (Q8ms'event and Q8ms='1') then
codigo32 <= atualshift;
end if;
end process;
process (CLK100k)
begin
if (CLK100k'event and CLK100k='1') then
atual_S <= prox_S;
num7 <= proxnum7;
end if;
end process;
UC0: CONTBCD_C port map(CLK => CLK100k, CLR => CLR_cont_S, UP => '1', EN => (S_IR and not Q8ms), ENOUT => EO(0), Q => num0);
UC1: CONTBCD_C port map(CLK => CLK100k, CLR => CLR_cont_S, UP => '1', EN => EO(0), ENOUT => EO(1), Q => num1);
UC2: CONTBCD_C port map(CLK => CLK100k, CLR => CLR_cont_S, UP => '1', EN => EO(1), ENOUT => EO(2), Q => num2);
Q1ms <= num2(0);
Q4ms <= num2(2);
Q8ms <= num2(3);
ENshift <= not Q8ms and not Q4ms;
SIshift <= Q1ms;
proxnum7 <= "0000" when codigo32(31 downto 24)="11101001" else -- 0 = E9
"0001" when codigo32(31 downto 24)="11110011" else -- 1 = F3
"0010" when codigo32(31 downto 24)="11100111" else -- 2 = E7
"0011" when codigo32(31 downto 24)="10100001" else -- 3 = A1
"0100" when codigo32(31 downto 24)="11110111" else -- 4 = F7
"0101" when codigo32(31 downto 24)="11100011" else -- 5 = E3
"0110" when codigo32(31 downto 24)="10100101" else -- 6 = A5
"0111" when codigo32(31 downto 24)="10111101" else -- 7 = BD
"1000" when codigo32(31 downto 24)="10101101" else -- 8 = AD
"1001" when codigo32(31 downto 24)="10110101" else -- 9 = B5
num7;
process(CLK27MHz)
begin
if(CLK27MHz'event and CLK27MHz = '1') then
@@ -190,9 +68,6 @@ clkdisp <= contaux(5); -- 421875 Hz
GPIO(0) <= clkdisp;
GPIO(1) <= cs;
GPIO(2) <= din;
S_IR <= GPIO(4);
LEDS <= num7;
GPIO(5) <= CLK37915 and OUTIR;
end comportamento;

3
textovhdl.xpi Normal file
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@@ -0,0 +1,3 @@
PROGRAM=PAR
STATE=ROUTED
TIMESPECS_MET=OFF

52
textovhdl.xst Normal file
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@@ -0,0 +1,52 @@
set -tmpdir "xst/projnav.tmp"
set -xsthdpdir "xst"
run
-ifn textovhdl.prj
-ofn textovhdl
-ofmt NGC
-p xc6slx16-2-csg324
-top textovhdl
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-keep_hierarchy No
-netlist_hierarchy As_Optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case Maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-lc Auto
-reduce_control_sets Auto
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style LUT
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-shreg_extract YES
-rom_style Auto
-auto_bram_packing NO
-resource_sharing YES
-async_to_sync NO
-shreg_min_size 2
-use_dsp48 Auto
-iobuf YES
-max_fanout 100000
-bufg 16
-register_duplication YES
-register_balancing No
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob Auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5

8
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INTSTYLE=ise
INFILE=C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.ncd
OUTFILE=C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.bit
FAMILY=Spartan6
PART=xc6slx16-2csg324
WORKINGDIR=C:\Users\Gabriel\Xilinx\Aula20220608
LICENSE=WebPack
USER_INFO=212425623_0_0_843

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<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<center><big><big><b>System Settings</b></big></big></center><br>
<A NAME="Environment Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Environment Variable</b></td>
<td><b>xst</b></td>
<td><b>ngdbuild</b></td>
<td><b>map</b></td>
<td><b>par</b></td>
</tr>
<tr>
<td>PATHEXT</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
</tr>
<tr>
<td>Path</td>
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ProgramData\Oracle\Java\javapath;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Intel\WiFi\bin\;<br>C:\Program Files\Common Files\Intel\WirelessCommon\;<br>C:\Program Files\TortoiseGit\bin;<br>C:\Program Files\Git\cmd;<br>C:\Program Files\Microsoft VS Code\bin;<br>C:\Program Files\MATLAB\R2022a\bin</td>
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ProgramData\Oracle\Java\javapath;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Intel\WiFi\bin\;<br>C:\Program Files\Common Files\Intel\WirelessCommon\;<br>C:\Program Files\TortoiseGit\bin;<br>C:\Program Files\Git\cmd;<br>C:\Program Files\Microsoft VS Code\bin;<br>C:\Program Files\MATLAB\R2022a\bin</td>
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ProgramData\Oracle\Java\javapath;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Intel\WiFi\bin\;<br>C:\Program Files\Common Files\Intel\WirelessCommon\;<br>C:\Program Files\TortoiseGit\bin;<br>C:\Program Files\Git\cmd;<br>C:\Program Files\Microsoft VS Code\bin;<br>C:\Program Files\MATLAB\R2022a\bin</td>
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ProgramData\Oracle\Java\javapath;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Intel\WiFi\bin\;<br>C:\Program Files\Common Files\Intel\WirelessCommon\;<br>C:\Program Files\TortoiseGit\bin;<br>C:\Program Files\Git\cmd;<br>C:\Program Files\Microsoft VS Code\bin;<br>C:\Program Files\MATLAB\R2022a\bin</td>
</tr>
<tr>
<td>XILINX</td>
<td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
<td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
<td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
<td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
</tr>
<tr>
<td>XILINX_DSP</td>
<td>C:\Xilinx\14.7\ISE_DS\ISE</td>
<td>C:\Xilinx\14.7\ISE_DS\ISE</td>
<td>C:\Xilinx\14.7\ISE_DS\ISE</td>
<td>C:\Xilinx\14.7\ISE_DS\ISE</td>
</tr>
<tr>
<td>XILINX_EDK</td>
<td>C:\Xilinx\14.7\ISE_DS\EDK</td>
<td>C:\Xilinx\14.7\ISE_DS\EDK</td>
<td>C:\Xilinx\14.7\ISE_DS\EDK</td>
<td>C:\Xilinx\14.7\ISE_DS\EDK</td>
</tr>
<tr>
<td>XILINX_PLANAHEAD</td>
<td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
<td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
<td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
<td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
</tr>
</TABLE>
<A NAME="Synthesis Property Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-ifn</td>
<td>&nbsp;</td>
<td>textovhdl.prj</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-ofn</td>
<td>&nbsp;</td>
<td>textovhdl</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-ofmt</td>
<td>&nbsp;</td>
<td>NGC</td>
<td>NGC</td>
</tr>
<tr>
<td>-p</td>
<td>&nbsp;</td>
<td>xc6slx16-2-csg324</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-top</td>
<td>&nbsp;</td>
<td>textovhdl</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-opt_mode</td>
<td>Optimization Goal</td>
<td>Speed</td>
<td>Speed</td>
</tr>
<tr>
<td>-opt_level</td>
<td>Optimization Effort</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>-power</td>
<td>Power Reduction</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-iuc</td>
<td>Use synthesis Constraints File</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-keep_hierarchy</td>
<td>Keep Hierarchy</td>
<td>No</td>
<td>No</td>
</tr>
<tr>
<td>-netlist_hierarchy</td>
<td>Netlist Hierarchy</td>
<td>As_Optimized</td>
<td>As_Optimized</td>
</tr>
<tr>
<td>-rtlview</td>
<td>Generate RTL Schematic</td>
<td>Yes</td>
<td>No</td>
</tr>
<tr>
<td>-glob_opt</td>
<td>Global Optimization Goal</td>
<td>AllClockNets</td>
<td>AllClockNets</td>
</tr>
<tr>
<td>-read_cores</td>
<td>Read Cores</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-write_timing_constraints</td>
<td>Write Timing Constraints</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-cross_clock_analysis</td>
<td>Cross Clock Analysis</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-bus_delimiter</td>
<td>Bus Delimiter</td>
<td>&lt;&gt;</td>
<td>&lt;&gt;</td>
</tr>
<tr>
<td>-slice_utilization_ratio</td>
<td>Slice Utilization Ratio</td>
<td>100</td>
<td>100</td>
</tr>
<tr>
<td>-bram_utilization_ratio</td>
<td>BRAM Utilization Ratio</td>
<td>100</td>
<td>100</td>
</tr>
<tr>
<td>-dsp_utilization_ratio</td>
<td>DSP Utilization Ratio</td>
<td>100</td>
<td>100</td>
</tr>
<tr>
<td>-reduce_control_sets</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-fsm_extract</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-fsm_encoding</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-safe_implementation</td>
<td>&nbsp;</td>
<td>No</td>
<td>No</td>
</tr>
<tr>
<td>-fsm_style</td>
<td>&nbsp;</td>
<td>LUT</td>
<td>LUT</td>
</tr>
<tr>
<td>-ram_extract</td>
<td>&nbsp;</td>
<td>Yes</td>
<td>Yes</td>
</tr>
<tr>
<td>-ram_style</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-rom_extract</td>
<td>&nbsp;</td>
<td>Yes</td>
<td>Yes</td>
</tr>
<tr>
<td>-shreg_extract</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-rom_style</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-auto_bram_packing</td>
<td>&nbsp;</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-resource_sharing</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-async_to_sync</td>
<td>&nbsp;</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-use_dsp48</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-iobuf</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-max_fanout</td>
<td>&nbsp;</td>
<td>100000</td>
<td>100000</td>
</tr>
<tr>
<td>-bufg</td>
<td>&nbsp;</td>
<td>16</td>
<td>16</td>
</tr>
<tr>
<td>-register_duplication</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-register_balancing</td>
<td>&nbsp;</td>
<td>No</td>
<td>No</td>
</tr>
<tr>
<td>-optimize_primitives</td>
<td>&nbsp;</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-use_clock_enable</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-use_sync_set</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-use_sync_reset</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-iob</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-equivalent_register_removal</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-slice_utilization_ratio_maxmargin</td>
<td>&nbsp;</td>
<td>5</td>
<td>0</td>
</tr>
</TABLE>
<A NAME="Translation Property Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-intstyle</td>
<td>&nbsp;</td>
<td>ise</td>
<td>None</td>
</tr>
<tr>
<td>-dd</td>
<td>&nbsp;</td>
<td>_ngo</td>
<td>None</td>
</tr>
<tr>
<td>-p</td>
<td>&nbsp;</td>
<td>xc6slx16-csg324-2</td>
<td>None</td>
</tr>
<tr>
<td>-uc</td>
<td>&nbsp;</td>
<td>restricoes.ucf</td>
<td>None</td>
</tr>
</TABLE>
<A NAME="Map Property Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Map Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-ol</td>
<td>Place & Route Effort Level (Overall)</td>
<td>high</td>
<td>high</td>
</tr>
<tr>
<td>-xt</td>
<td>Extra Cost Tables</td>
<td>0</td>
<td>0</td>
</tr>
<tr>
<td>-ir</td>
<td>Use RLOC Constraints</td>
<td>OFF</td>
<td>OFF</td>
</tr>
<tr>
<td>-t</td>
<td>Starting Placer Cost Table (1-100) Map</td>
<td>1</td>
<td>0</td>
</tr>
<tr>
<td>-r</td>
<td>Register Ordering</td>
<td>4</td>
<td>4</td>
</tr>
<tr>
<td>-intstyle</td>
<td>&nbsp;</td>
<td>ise</td>
<td>None</td>
</tr>
<tr>
<td>-lc</td>
<td>LUT Combining</td>
<td>off</td>
<td>off</td>
</tr>
<tr>
<td>-o</td>
<td>&nbsp;</td>
<td>textovhdl_map.ncd</td>
<td>None</td>
</tr>
<tr>
<td>-w</td>
<td>&nbsp;</td>
<td>true</td>
<td>false</td>
</tr>
<tr>
<td>-pr</td>
<td>Pack I/O Registers/Latches into IOBs</td>
<td>off</td>
<td>off</td>
</tr>
<tr>
<td>-p</td>
<td>&nbsp;</td>
<td>xc6slx16-csg324-2</td>
<td>None</td>
</tr>
</TABLE>
<A NAME="Place and Route Property Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Place and Route Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-intstyle</td>
<td>&nbsp;</td>
<td>ise</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-mt</td>
<td>Enable Multi-Threading</td>
<td>off</td>
<td>off</td>
</tr>
<tr>
<td>-ol</td>
<td>Place & Route Effort Level (Overall)</td>
<td>high</td>
<td>std</td>
</tr>
<tr>
<td>-w</td>
<td>&nbsp;</td>
<td>true</td>
<td>false</td>
</tr>
</TABLE>
<A NAME="Operating System Information"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Operating System Information</b></td>
<td><b>xst</b></td>
<td><b>ngdbuild</b></td>
<td><b>map</b></td>
<td><b>par</b></td>
</tr>
<tr>
<td>CPU Architecture/Speed</td>
<td>Intel(R) Core(TM)2 Duo CPU T9600 @ 2.80GHz/2793 MHz</td>
<td>Intel(R) Core(TM)2 Duo CPU T9600 @ 2.80GHz/2793 MHz</td>
<td>Intel(R) Core(TM)2 Duo CPU T9600 @ 2.80GHz/2793 MHz</td>
<td>Intel(R) Core(TM)2 Duo CPU T9600 @ 2.80GHz/2793 MHz</td>
</tr>
<tr>
<td>Host</td>
<td>GABRIEL-E5400</td>
<td>GABRIEL-E5400</td>
<td>GABRIEL-E5400</td>
<td>GABRIEL-E5400</td>
</tr>
<tr>
<td>OS Name</td>
<td>Microsoft Windows 7 , 64-bit</td>
<td>Microsoft Windows 7 , 64-bit</td>
<td>Microsoft Windows 7 , 64-bit</td>
<td>Microsoft Windows 7 , 64-bit</td>
</tr>
<tr>
<td>OS Release</td>
<td>Service Pack 1 (build 7601)</td>
<td>Service Pack 1 (build 7601)</td>
<td>Service Pack 1 (build 7601)</td>
<td>Service Pack 1 (build 7601)</td>
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Release 14.7 Map P.20131013 (nt64)
Xilinx Map Application Log File for Design 'textovhdl'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
-pr off -lc off -power off -o textovhdl_map.ncd textovhdl.ngd textovhdl.pcf
Target Device : xc6slx16
Target Package : csg324
Target Speed : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Wed Jun 08 11:35:36 2022
Mapping design into LUTs...
WARNING:MapLib:701 - Signal LEDS<3> connected to top level port LEDS<3> has been
removed.
WARNING:MapLib:701 - Signal LEDS<2> connected to top level port LEDS<2> has been
removed.
WARNING:MapLib:701 - Signal LEDS<1> connected to top level port LEDS<1> has been
removed.
WARNING:MapLib:701 - Signal LEDS<0> connected to top level port LEDS<0> has been
removed.
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 5 secs
Total CPU time at the beginning of Placer: 5 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:3fba7d2c) REAL time: 5 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:3fba7d2c) REAL time: 5 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:3fba7d2c) REAL time: 5 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:a88cf486) REAL time: 6 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:a88cf486) REAL time: 6 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:a88cf486) REAL time: 6 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:a88cf486) REAL time: 6 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:a88cf486) REAL time: 6 secs
Phase 9.8 Global Placement
....
....
Phase 9.8 Global Placement (Checksum:74c7df35) REAL time: 6 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:74c7df35) REAL time: 6 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:b8849b8d) REAL time: 6 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:b8849b8d) REAL time: 6 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:b8849b8d) REAL time: 6 secs
Total REAL time to Placer completion: 6 secs
Total CPU time to Placer completion: 6 secs
Running post-placement packing...
Writing output files...
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 4
Slice Logic Utilization:
Number of Slice Registers: 32 out of 18,224 1%
Number used as Flip Flops: 32
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 31 out of 9,112 1%
Number used as logic: 29 out of 9,112 1%
Number using O6 output only: 14
Number using O5 output only: 11
Number using O5 and O6: 4
Number used as ROM: 0
Number used as Memory: 0 out of 2,176 0%
Number used exclusively as route-thrus: 2
Number with same-slice register load: 0
Number with same-slice carry load: 2
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 11 out of 2,278 1%
Number of MUXCYs used: 20 out of 4,556 1%
Number of LUT Flip Flop pairs used: 31
Number with an unused Flip Flop: 1 out of 31 3%
Number with an unused LUT: 0 out of 31 0%
Number of fully used LUT-FF pairs: 30 out of 31 96%
Number of unique control sets: 2
Number of slice register sites lost
to control set restrictions: 8 out of 18,224 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 17 out of 232 7%
Number of LOCed IOBs: 17 out of 17 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 32 0%
Number of RAMB8BWERs: 0 out of 64 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 2 out of 16 12%
Number used as BUFGs: 2
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 0 out of 248 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 248 0%
Number of OLOGIC2/OSERDES2s: 0 out of 248 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 32 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 2 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 1.88
Peak Memory Usage: 346 MB
Total REAL time to MAP completion: 7 secs
Total CPU time to MAP completion: 6 secs
Mapping completed.
See MAP report file "textovhdl_map.mrp" for details.

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Release 14.7 Map P.20131013 (nt64)
Xilinx Mapping Report File for Design 'textovhdl'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
-pr off -lc off -power off -o textovhdl_map.ncd textovhdl.ngd textovhdl.pcf
Target Device : xc6slx16
Target Package : csg324
Target Speed : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Wed Jun 08 11:35:36 2022
Design Summary
--------------
Number of errors: 0
Number of warnings: 4
Slice Logic Utilization:
Number of Slice Registers: 32 out of 18,224 1%
Number used as Flip Flops: 32
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 31 out of 9,112 1%
Number used as logic: 29 out of 9,112 1%
Number using O6 output only: 14
Number using O5 output only: 11
Number using O5 and O6: 4
Number used as ROM: 0
Number used as Memory: 0 out of 2,176 0%
Number used exclusively as route-thrus: 2
Number with same-slice register load: 0
Number with same-slice carry load: 2
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 11 out of 2,278 1%
Number of MUXCYs used: 20 out of 4,556 1%
Number of LUT Flip Flop pairs used: 31
Number with an unused Flip Flop: 1 out of 31 3%
Number with an unused LUT: 0 out of 31 0%
Number of fully used LUT-FF pairs: 30 out of 31 96%
Number of unique control sets: 2
Number of slice register sites lost
to control set restrictions: 8 out of 18,224 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 17 out of 232 7%
Number of LOCed IOBs: 17 out of 17 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 32 0%
Number of RAMB8BWERs: 0 out of 64 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 2 out of 16 12%
Number used as BUFGs: 2
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 0 out of 248 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 248 0%
Number of OLOGIC2/OSERDES2s: 0 out of 248 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 32 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 2 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 1.88
Peak Memory Usage: 346 MB
Total REAL time to MAP completion: 7 secs
Total CPU time to MAP completion: 6 secs
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
WARNING:MapLib:701 - Signal LEDS<3> connected to top level port LEDS<3> has been
removed.
WARNING:MapLib:701 - Signal LEDS<2> connected to top level port LEDS<2> has been
removed.
WARNING:MapLib:701 - Signal LEDS<1> connected to top level port LEDS<1> has been
removed.
WARNING:MapLib:701 - Signal LEDS<0> connected to top level port LEDS<0> has been
removed.
Section 3 - Informational
-------------------------
INFO:LIT:243 - Logical network BUT<3>_IBUF has no load.
INFO:LIT:395 - The above info message is repeated 12 more times for the
following (max. 5 shown):
BUT<2>_IBUF,
BUT<1>_IBUF,
BUT<0>_IBUF,
DIPSW<3>_IBUF,
DIPSW<2>_IBUF
To see the details of these info messages, please use the -detail switch.
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
1.260 Volts)
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
INFO:Pack:1650 - Map created a placed design.
Section 4 - Removed Logic Summary
---------------------------------
8 block(s) removed
2 block(s) optimized away
4 signal(s) removed
Section 5 - Removed Logic
-------------------------
The trimmed logic reported below is either:
1. part of a cycle
2. part of disabled logic
3. a side-effect of other trimmed logic
The signal "LEDS<3>" is unused and has been removed.
Unused block "LEDS_3_OBUFT" (TRI) removed.
The signal "LEDS<2>" is unused and has been removed.
Unused block "LEDS_2_OBUFT" (TRI) removed.
The signal "LEDS<1>" is unused and has been removed.
Unused block "LEDS_1_OBUFT" (TRI) removed.
The signal "LEDS<0>" is unused and has been removed.
Unused block "LEDS_0_OBUFT" (TRI) removed.
Unused block "LEDS<0>" (PAD) removed.
Unused block "LEDS<1>" (PAD) removed.
Unused block "LEDS<2>" (PAD) removed.
Unused block "LEDS<3>" (PAD) removed.
Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 6 - IOB Properties
--------------------------
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Term | Strength | Rate | | | Delay |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| BUT<0> | IOB | INPUT | LVCMOS25 | | | | | | |
| BUT<1> | IOB | INPUT | LVCMOS25 | | | | | | |
| BUT<2> | IOB | INPUT | LVCMOS25 | | | | | | |
| BUT<3> | IOB | INPUT | LVCMOS25 | | | | | | |
| CLK27MHz | IOB | INPUT | LVCMOS25 | | | | | | |
| DIPSW<0> | IOB | INPUT | LVCMOS25 | | | | | | |
| DIPSW<1> | IOB | INPUT | LVCMOS25 | | | | | | |
| DIPSW<2> | IOB | INPUT | LVCMOS25 | | | | | | |
| DIPSW<3> | IOB | INPUT | LVCMOS25 | | | | | | |
| GPIO<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| GPIO<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| GPIO<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| GPIO<3> | IOB | INPUT | LVCMOS25 | | | | | | |
| GPIO<4> | IOB | INPUT | LVCMOS25 | | | | | | |
| GPIO<5> | IOB | INPUT | LVCMOS25 | | | | | | |
| GPIO<6> | IOB | INPUT | LVCMOS25 | | | | | | |
| GPIO<7> | IOB | INPUT | LVCMOS25 | | | | | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Timing Report
--------------------------
A logic-level (pre-route) timing report can be generated by using Xilinx static
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
mapped NCD and PCF files. Please note that this timing report will be generated
using estimated delay information. For accurate numbers, please generate a
timing report with the post Place and Route NCD file.
For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
Command Line Tools User Guide "TRACE" chapter.
Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 12 - Control Set Information
------------------------------------
Use the "-detail" map option to print out Control Set Information.
Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.

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<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt64" product="ISE" version="14.7">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Map" timeStamp="Wed Jun 08 11:35:43 2022">
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<row stringID="row" value="1">
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<item stringID="User_EnvOsname" value="Microsoft Windows 7 , 64-bit"/>
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<item stringID="User_EnvHost" value="GABRIEL-E5400"/>
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<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
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<item stringID="speed" value="2793 MHz"/>
</row>
</table>
</section>
<section stringID="MAP_OPTION_SUMMARY">
<item DEFAULT="high" label="-ol" stringID="MAP_EFFORTLEVEL" value="high"/>
<item DEFAULT="0" label="-xt" stringID="MAP_EXTRA_COST_TABLE" value="0"/>
<item DEFAULT="OFF" label="-ir" stringID="MAP_IGNORERLOCS" value="OFF"/>
<item DEFAULT="OFF" stringID="MAP_LUTCOMPRESSIONMODE" value="OFF"/>
<item DEFAULT="0" label="-t" stringID="MAP_PLACERCOSTTABLE" value="1"/>
<item DEFAULT="4" label="-r" stringID="MAP_REGORDERING" value="4"/>
<item DEFAULT="FALSE" stringID="MAP_REPLICATELUTS" value="TRUE"/>
<item DEFAULT="None" label="-intstyle" stringID="MAP_INTSTYLE" value="ise"/>
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<section stringID="MAP_DESIGN_SUMMARY">
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<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="4"/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="353868"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="7 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="6 secs "/>
</section>
<section stringID="MAP_SLICE_REPORTING">
<item AVAILABLE="18224" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="32">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="32"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
</item>
<item AVAILABLE="9112" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="31">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="11"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="14"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="4"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_DPRAM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_DPRAM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_DPRAM_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_SPRAM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SPRAM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SPRAM_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_SRL_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="2"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="2"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item>
<item AVAILABLE="2278" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="11">
<item AVAILABLE="595" dataType="int" stringID="MAP_NUM_SLICEL" value="5"/>
<item AVAILABLE="544" dataType="int" stringID="MAP_NUM_SLICEM" value="0"/>
<item AVAILABLE="1139" dataType="int" stringID="MAP_NUM_SLICEX" value="6"/>
</item>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="31">
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="1"/>
<item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="0"/>
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="30"/>
</item>
</section>
<section stringID="MAP_IOB_REPORTING">
<item AVAILABLE="232" dataType="int" stringID="MAP_AGG_BONDED_IO" value="17"/>
<item AVAILABLE="12" dataType="int" stringID="MAP_AGG_UNBONDED_IO" value="0"/>
<item AVAILABLE="0" dataType="int" label="IOB Flip Flops" stringID="MAP_NUM_IOB_FF" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IOB_LATCH" value="0"/>
<item AVAILABLE="6" dataType="int" stringID="MAP_NUM_IOBM" value="0"/>
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<item AVAILABLE="6" dataType="int" stringID="MAP_NUM_IOBS" value="0"/>
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<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IPAD" value="0"/>
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<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_OPAD" value="0"/>
</section>
<section stringID="MAP_HARD_IP_REPORTING"/>
<section stringID="MAP_RAM_FIFO_DATA">
<item AVAILABLE="32" dataType="int" stringID="MAP_NUM_RAMB16BWER" value="0"/>
<item AVAILABLE="64" dataType="int" stringID="MAP_NUM_RAMB8BWER" value="0"/>
</section>
<section stringID="MAP_IP_DATA">
<item AVAILABLE="4" dataType="int" stringID="MAP_NUM_BSCAN" value="0"/>
<item AVAILABLE="128" dataType="int" stringID="MAP_NUM_BUFH" value="0"/>
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<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_STARTUP" value="0"/>
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_SUSPEND_SYNC" value="0"/>
</section>
<section stringID="MAP_BUFG_DATA">
<item dataType="int" label="Number used as BUFGs" stringID="MAP_NUM_BUFG" value="2"/>
<item dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="0"/>
<item dataType="int" stringID="MAP_AVAILABLE" value="16"/>
</section>
<section stringID="MAP_MACRO_RPM_REPORTING">
<item dataType="int" stringID="MAP_HARD_MACROS" value="0"/>
<item dataType="int" stringID="MAP_RPMS" value="0"/>
</section>
<section stringID="MAP_IOB_PROPERTIES">
<table stringID="MAP_IOB_TABLE">
<column label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME"/>
<column stringID="Type"/>
<column stringID="Direction"/>
<column label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD"/>
<column label="Diff&#xA;Term" stringID="DIFF_TERM"/>
<column label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH"/>
<column label="Slew&#xA;Rate" stringID="SLEW_RATE"/>
<column label="Reg&#xA;(s)" stringID="REGS"/>
<column stringID="Resistor"/>
<column label="IOB&#xA;Delay" stringID="IOB_DELAY"/>
<row stringID="row" value="1">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="BUT&lt;0>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="2">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="BUT&lt;1>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="3">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="BUT&lt;2>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="4">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="BUT&lt;3>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="5">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="CLK27MHz"/>
<item stringID="Type" value="IOB"/>
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<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="6">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="DIPSW&lt;0>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="7">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="DIPSW&lt;1>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="8">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="DIPSW&lt;2>"/>
<item stringID="Type" value="IOB"/>
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</row>
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<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="DIPSW&lt;3>"/>
<item stringID="Type" value="IOB"/>
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</row>
<row stringID="row" value="10">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="GPIO&lt;0>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="11">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="GPIO&lt;1>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="12">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="GPIO&lt;2>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="13">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="GPIO&lt;3>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="14">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="GPIO&lt;4>"/>
<item stringID="Type" value="IOB"/>
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<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="15">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="GPIO&lt;5>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="16">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="GPIO&lt;6>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="17">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="GPIO&lt;7>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
</table>
</section>
<section stringID="MAP_RPM_MACROS">
<section stringID="MAP_SHAPE_SECTION">
<item dataType="int" stringID="MAP_NUM_SHAPE" value="2"/>
</section>
</section>
<section stringID="MAP_GUIDE_REPORT"/>
<section stringID="MAP_AREA_GROUPS_PARTITIONS"/>
<section stringID="MAP_TIMING_REPORT"/>
<section stringID="MAP_CONFIGURATION_STRING_DETAILS"/>
<section stringID="MAP_GENERAL_CONFIG_DATA"/>
<section stringID="MAP_CONTROL_SET_INFORMATION">
<item dataType="int" label="Number of unique control sets" stringID="MAP_NUM_CONTROL_SETS" value="2"/>
<tree stringID="MAP_CONTROL_SET_HIERARCHY">
<property stringID="MAP_CLOCK_SIGNAL"/>
<property stringID="MAP_RESET_SIGNAL"/>
<property stringID="MAP_SET_SIGNAL"/>
<property stringID="MAP_ENABLE_SIGNAL"/>
<property label="Slice&#xA;Load Count" stringID="MAP_SLICE_LOAD_COUNT"/>
<property label="Bel&#xA;Load Count" stringID="MAP_BEL_LOAD_COUNT"/>
</tree>
</section>
</task>
<section stringID="MAP_RAM_FIFO_DATA">
<item AVAILABLE="32" dataType="int" stringID="MAP_NUM_RAMB16BWER" value="0"/>
<item AVAILABLE="64" dataType="int" stringID="MAP_NUM_RAMB8BWER" value="0"/>
</section>
<section stringID="MAP_IP_DATA">
<item AVAILABLE="4" dataType="int" stringID="MAP_NUM_BSCAN" value="0"/>
<item AVAILABLE="128" dataType="int" stringID="MAP_NUM_BUFH" value="0"/>
<item AVAILABLE="8" dataType="int" stringID="MAP_NUM_BUFPLL" value="0"/>
<item AVAILABLE="4" dataType="int" stringID="MAP_NUM_BUFPLL_MCB" value="0"/>
<item AVAILABLE="32" dataType="int" stringID="MAP_NUM_DSP48A1" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_GTPA1_DUAL" value="0"/>
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_ICAP" value="0"/>
<item AVAILABLE="2" dataType="int" stringID="MAP_NUM_MCB" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_PCIE_A1" value="0"/>
<item AVAILABLE="2" dataType="int" stringID="MAP_NUM_PCILOGICSE" value="0"/>
<item AVAILABLE="2" dataType="int" stringID="MAP_NUM_PLL_ADV" value="0"/>
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_PMV" value="0"/>
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_STARTUP" value="0"/>
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_SUSPEND_SYNC" value="0"/>
</section>
<section stringID="MAP_BUFG_DATA">
<item dataType="int" label="Number used as BUFGs" stringID="MAP_NUM_BUFG" value="2"/>
<item dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="0"/>
<item dataType="int" stringID="MAP_AVAILABLE" value="16"/>
<item dataType="int" stringID="MAP_HARD_MACROS" value="0"/>
<item dataType="int" stringID="MAP_RPMS" value="0"/>
</section>
</application>
</document>

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<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt64" product="ISE" version="14.7">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
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</row>
<row stringID="row" value="1">
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</table>
<item stringID="User_EnvOs" value="OS Information">
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</item>
<item stringID="User_EnvHost" value="GABRIEL-E5400"/>
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</table>
</section>
<task stringID="NGDBUILD_OPTION_SUMMARY">
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<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="5"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="5"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="13"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="15"/>
</section>
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
<section stringID="NGDBUILD_CORE_INSTANCES"/>
</section>
</task>
</application>
</document>

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#Release 14.7 - par P.20131013 (nt64)
#Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
#Wed Jun 08 11:35:52 2022
#
## NOTE: This file is designed to be imported into a spreadsheet program
# such as Microsoft Excel for viewing, printing and sorting. The |
# character is used as the data field separator. This file is also designed
# to support parsing.
#
#INPUT FILE: textovhdl_map.ncd
#OUTPUT FILE: textovhdl_pad.csv
#PART TYPE: xc6slx16
#SPEED GRADE: -2
#PACKAGE: csg324
#
# Pinout by Pin Number:
#
# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,Drive (mA),Slew Rate,Termination,IOB Delay,Voltage,Constraint,IO Register,Signal Integrity,
A1,,,GND,,,,,,,,,,,,
A2,,IOBS,IO_L2N_0,UNUSED,,0,,,,,,,,,
A3,GPIO<2>,IOB,IO_L4N_0,OUTPUT,LVCMOS25*,0,12,SLOW,,,,LOCATED,NO,NONE,
A4,,IOBS,IO_L5N_0,UNUSED,,0,,,,,,,,,
A5,,IOBS,IO_L6N_0,UNUSED,,0,,,,,,,,,
A6,,IOBS,IO_L8N_VREF_0,UNUSED,,0,,,,,,,,,
A7,,IOBS,IO_L10N_0,UNUSED,,0,,,,,,,,,
A8,,IOBS,IO_L33N_0,UNUSED,,0,,,,,,,,,
A9,,IOBS,IO_L35N_GCLK16_0,UNUSED,,0,,,,,,,,,
A10,,IOBS,IO_L37N_GCLK12_0,UNUSED,,0,,,,,,,,,
A11,,IOBS,IO_L39N_0,UNUSED,,0,,,,,,,,,
A12,,IOBS,IO_L41N_0,UNUSED,,0,,,,,,,,,
A13,,IOBS,IO_L50N_0,UNUSED,,0,,,,,,,,,
A14,,IOBS,IO_L62N_VREF_0,UNUSED,,0,,,,,,,,,
A15,,IOBS,IO_L64N_SCP4_0,UNUSED,,0,,,,,,,,,
A16,,IOBS,IO_L66N_SCP0_0,UNUSED,,0,,,,,,,,,
A17,,,TCK,,,,,,,,,,,,
A18,,,GND,,,,,,,,,,,,
B1,,,VCCAUX,,,,,,,,2.5,,,,
B2,,IOBM,IO_L2P_0,UNUSED,,0,,,,,,,,,
B3,,IOBM,IO_L4P_0,UNUSED,,0,,,,,,,,,
B4,GPIO<5>,IOB,IO_L5P_0,INPUT,LVCMOS25*,0,,,,NONE,,LOCATED,NO,NONE,
B5,,,VCCO_0,,,0,,,,,2.50,,,,
B6,,IOBM,IO_L8P_0,UNUSED,,0,,,,,,,,,
B7,,,GND,,,,,,,,,,,,
B8,,IOBM,IO_L33P_0,UNUSED,,0,,,,,,,,,
B9,,IOBM,IO_L35P_GCLK17_0,UNUSED,,0,,,,,,,,,
B10,,,VCCO_0,,,0,,,,,2.50,,,,
B11,,IOBM,IO_L39P_0,UNUSED,,0,,,,,,,,,
B12,,IOBM,IO_L41P_0,UNUSED,,0,,,,,,,,,
B13,,,GND,,,,,,,,,,,,
B14,,IOBM,IO_L62P_0,UNUSED,,0,,,,,,,,,
B15,,,VCCO_0,,,0,,,,,2.50,,,,
B16,,IOBM,IO_L66P_SCP1_0,UNUSED,,0,,,,,,,,,
B17,,,VCCAUX,,,,,,,,2.5,,,,
B18,,,TMS,,,,,,,,,,,,
C1,,IOBS,IO_L83N_VREF_3,UNUSED,,3,,,,,,,,,
C2,,IOBM,IO_L83P_3,UNUSED,,3,,,,,,,,,
C3,,,GND,,,,,,,,,,,,
C4,,IOBS,IO_L1N_VREF_0,UNUSED,,0,,,,,,,,,
C5,,IOBM,IO_L6P_0,UNUSED,,0,,,,,,,,,
C6,,IOBS,IO_L3N_0,UNUSED,,0,,,,,,,,,
C7,,IOBM,IO_L10P_0,UNUSED,,0,,,,,,,,,
C8,,IOBS,IO_L11N_0,UNUSED,,0,,,,,,,,,
C9,,IOBS,IO_L34N_GCLK18_0,UNUSED,,0,,,,,,,,,
C10,,IOBM,IO_L37P_GCLK13_0,UNUSED,,0,,,,,,,,,
C11,,IOBS,IO_L36N_GCLK14_0,UNUSED,,0,,,,,,,,,
C12,,IOBS,IO_L47N_0,UNUSED,,0,,,,,,,,,
C13,,IOBM,IO_L50P_0,UNUSED,,0,,,,,,,,,
C14,,IOBS,IO_L65N_SCP2_0,UNUSED,,0,,,,,,,,,
C15,,IOBM,IO_L64P_SCP5_0,UNUSED,,0,,,,,,,,,
C16,,,GND,,,,,,,,,,,,
C17,,IOBM,IO_L29P_A23_M1A13_1,UNUSED,,1,,,,,,,,,
C18,,IOBS,IO_L29N_A22_M1A14_1,UNUSED,,1,,,,,,,,,
D1,,IOBS,IO_L52N_M3A9_3,UNUSED,,3,,,,,,,,,
D2,,IOBM,IO_L52P_M3A8_3,UNUSED,,3,,,,,,,,,
D3,,IOBS,IO_L54N_M3A11_3,UNUSED,,3,,,,,,,,,
D4,,IOBM,IO_L1P_HSWAPEN_0,UNUSED,,0,,,,,,,,,
D5,,,GND,,,,,,,,,,,,
D6,,IOBM,IO_L3P_0,UNUSED,,0,,,,,,,,,
D7,,,VCCO_0,,,0,,,,,2.50,,,,
D8,,IOBM,IO_L11P_0,UNUSED,,0,,,,,,,,,
D9,,IOBM,IO_L34P_GCLK19_0,UNUSED,,0,,,,,,,,,
D10,,,GND,,,,,,,,,,,,
D11,,IOBM,IO_L36P_GCLK15_0,UNUSED,,0,,,,,,,,,
D12,,IOBM,IO_L47P_0,UNUSED,,0,,,,,,,,,
D13,,,VCCO_0,,,0,,,,,2.50,,,,
D14,DIPSW<0>,IOB,IO_L65P_SCP3_0,INPUT,LVCMOS25*,0,,,,NONE,,LOCATED,NO,NONE,
D15,,,TDI,,,,,,,,,,,,
D16,,,TDO,,,,,,,,,,,,
D17,,IOBM,IO_L31P_A19_M1CKE_1,UNUSED,,1,,,,,,,,,
D18,,IOBS,IO_L31N_A18_M1A12_1,UNUSED,,1,,,,,,,,,
E1,,IOBS,IO_L50N_M3BA2_3,UNUSED,,3,,,,,,,,,
E2,,,VCCO_3,,,3,,,,,any******,,,,
E3,,IOBM,IO_L50P_M3WE_3,UNUSED,,3,,,,,,,,,
E4,BUT<2>,IOB,IO_L54P_M3RESET_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
E5,,,VCCAUX,,,,,,,,2.5,,,,
E6,,IOBS,IO_L7N_0,UNUSED,,0,,,,,,,,,
E7,,IOBM,IO_L9P_0,UNUSED,,0,,,,,,,,,
E8,,IOBS,IO_L9N_0,UNUSED,,0,,,,,,,,,
E9,,,VCCAUX,,,,,,,,2.5,,,,
E10,,,VCCO_0,,,0,,,,,2.50,,,,
E11,,IOBS,IO_L42N_0,UNUSED,,0,,,,,,,,,
E12,DIPSW<1>,IOB,IO_L51N_0,INPUT,LVCMOS25*,0,,,,NONE,,LOCATED,NO,NONE,
E13,,IOBS,IO_L63N_SCP6_0,UNUSED,,0,,,,,,,,,
E14,,,VCCAUX,,,,,,,,2.5,,,,
E15,,,GND,,,,,,,,,,,,
E16,,IOBM,IO_L33P_A15_M1A10_1,UNUSED,,1,,,,,,,,,
E17,,,VCCO_1,,,1,,,,,2.50,,,,
E18,,IOBS,IO_L33N_A14_M1A4_1,UNUSED,,1,,,,,,,,,
F1,,IOBS,IO_L48N_M3BA1_3,UNUSED,,3,,,,,,,,,
F2,,IOBM,IO_L48P_M3BA0_3,UNUSED,,3,,,,,,,,,
F3,,IOBS,IO_L51N_M3A4_3,UNUSED,,3,,,,,,,,,
F4,,IOBM,IO_L51P_M3A10_3,UNUSED,,3,,,,,,,,,
F5,BUT<3>,IOB,IO_L55N_M3A14_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
F6,BUT<1>,IOB,IO_L55P_M3A13_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
F7,,IOBM,IO_L7P_0,UNUSED,,0,,,,,,,,,
F8,,IOBS,IO_L32N_0,UNUSED,,0,,,,,,,,,
F9,,IOBS,IO_L38N_VREF_0,UNUSED,,0,,,,,,,,,
F10,,IOBS,IO_L40N_0,UNUSED,,0,,,,,,,,,
F11,,IOBM,IO_L42P_0,UNUSED,,0,,,,,,,,,
F12,DIPSW<2>,IOB,IO_L51P_0,INPUT,LVCMOS25*,0,,,,NONE,,LOCATED,NO,NONE,
F13,GPIO<6>,IOB,IO_L63P_SCP7_0,INPUT,LVCMOS25*,0,,,,NONE,,LOCATED,NO,NONE,
F14,,IOBM,IO_L30P_A21_M1RESET_1,UNUSED,,1,,,,,,,,,
F15,GPIO<4>,IOB,IO_L1P_A25_1,INPUT,LVCMOS25*,1,,,,NONE,,LOCATED,NO,NONE,
F16,,IOBS,IO_L1N_A24_VREF_1,UNUSED,,1,,,,,,,,,
F17,,IOBM,IO_L35P_A11_M1A7_1,UNUSED,,1,,,,,,,,,
F18,,IOBS,IO_L35N_A10_M1A2_1,UNUSED,,1,,,,,,,,,
G1,,IOBS,IO_L46N_M3CLKN_3,UNUSED,,3,,,,,,,,,
G2,,,GND,,,,,,,,,,,,
G3,,IOBM,IO_L46P_M3CLK_3,UNUSED,,3,,,,,,,,,
G4,,,VCCO_3,,,3,,,,,any******,,,,
G5,,,GND,,,,,,,,,,,,
G6,,IOBS,IO_L53N_M3A12_3,UNUSED,,3,,,,,,,,,
G7,,,VCCINT,,,,,,,,1.2,,,,
G8,,IOBM,IO_L32P_0,UNUSED,,0,,,,,,,,,
G9,,IOBM,IO_L38P_0,UNUSED,,0,,,,,,,,,
G10,,,VCCAUX,,,,,,,,2.5,,,,
G11,,IOBM,IO_L40P_0,UNUSED,,0,,,,,,,,,
G12,,,GND,,,,,,,,,,,,
G13,,IOBS,IO_L32N_A16_M1A9_1,UNUSED,,1,,,,,,,,,
G14,,IOBS,IO_L30N_A20_M1A11_1,UNUSED,,1,,,,,,,,,
G15,,,VCCO_1,,,1,,,,,2.50,,,,
G16,,IOBM,IO_L38P_A5_M1CLK_1,UNUSED,,1,,,,,,,,,
G17,,,GND,,,,,,,,,,,,
G18,,IOBS,IO_L38N_A4_M1CLKN_1,UNUSED,,1,,,,,,,,,
H1,,IOBS,IO_L41N_GCLK26_M3DQ5_3,UNUSED,,3,,,,,,,,,
H2,,IOBM,IO_L41P_GCLK27_M3DQ4_3,UNUSED,,3,,,,,,,,,
H3,,IOBS,IO_L44N_GCLK20_M3A6_3,UNUSED,,3,,,,,,,,,
H4,,IOBM,IO_L44P_GCLK21_M3A5_3,UNUSED,,3,,,,,,,,,
H5,,IOBS,IO_L49N_M3A2_3,UNUSED,,3,,,,,,,,,
H6,,IOBM,IO_L49P_M3A7_3,UNUSED,,3,,,,,,,,,
H7,,IOBM,IO_L53P_M3CKE_3,UNUSED,,3,,,,,,,,,
H8,,,GND,,,,,,,,,,,,
H9,,,VCCINT,,,,,,,,1.2,,,,
H10,,,GND,,,,,,,,,,,,
H11,,,VCCINT,,,,,,,,1.2,,,,
H12,,IOBM,IO_L32P_A17_M1A8_1,UNUSED,,1,,,,,,,,,
H13,,IOBM,IO_L36P_A9_M1BA0_1,UNUSED,,1,,,,,,,,,
H14,,IOBS,IO_L36N_A8_M1BA1_1,UNUSED,,1,,,,,,,,,
H15,,IOBM,IO_L37P_A7_M1A0_1,UNUSED,,1,,,,,,,,,
H16,,IOBS,IO_L37N_A6_M1A1_1,UNUSED,,1,,,,,,,,,
H17,,IOBM,IO_L43P_GCLK5_M1DQ4_1,UNUSED,,1,,,,,,,,,
H18,,IOBS,IO_L43N_GCLK4_M1DQ5_1,UNUSED,,1,,,,,,,,,
J1,,IOBS,IO_L40N_M3DQ7_3,UNUSED,,3,,,,,,,,,
J2,,,VCCO_3,,,3,,,,,any******,,,,
J3,,IOBM,IO_L40P_M3DQ6_3,UNUSED,,3,,,,,,,,,
J4,,,GND,,,,,,,,,,,,
J5,,,VCCO_3,,,3,,,,,any******,,,,
J6,,IOBS,IO_L47N_M3A1_3,UNUSED,,3,,,,,,,,,
J7,,IOBM,IO_L47P_M3A0_3,UNUSED,,3,,,,,,,,,
J8,,,VCCINT,,,,,,,,1.2,,,,
J9,,,GND,,,,,,,,,,,,
J10,,,VCCINT,,,,,,,,1.2,,,,
J11,,,GND,,,,,,,,,,,,
J12,,,VCCAUX,,,,,,,,2.5,,,,
J13,,IOBM,IO_L39P_M1A3_1,UNUSED,,1,,,,,,,,,
J14,,,VCCO_1,,,1,,,,,2.50,,,,
J15,,,GND,,,,,,,,,,,,
J16,,IOBM,IO_L44P_A3_M1DQ6_1,UNUSED,,1,,,,,,,,,
J17,,,VCCO_1,,,1,,,,,2.50,,,,
J18,,IOBS,IO_L44N_A2_M1DQ7_1,UNUSED,,1,,,,,,,,,
K1,,IOBS,IO_L38N_M3DQ3_3,UNUSED,,3,,,,,,,,,
K2,,IOBM,IO_L38P_M3DQ2_3,UNUSED,,3,,,,,,,,,
K3,,IOBS,IO_L42N_GCLK24_M3LDM_3,UNUSED,,3,,,,,,,,,
K4,,IOBM,IO_L42P_GCLK25_TRDY2_M3UDM_3,UNUSED,,3,,,,,,,,,
K5,,IOBS,IO_L43N_GCLK22_IRDY2_M3CASN_3,UNUSED,,3,,,,,,,,,
K6,,IOBS,IO_L45N_M3ODT_3,UNUSED,,3,,,,,,,,,
K7,,,VCCAUX,,,,,,,,2.5,,,,
K8,,,GND,,,,,,,,,,,,
K9,,,VCCINT,,,,,,,,1.2,,,,
K10,,,GND,,,,,,,,,,,,
K11,,,VCCINT,,,,,,,,1.2,,,,
K12,,IOBM,IO_L34P_A13_M1WE_1,UNUSED,,1,,,,,,,,,
K13,,IOBS,IO_L34N_A12_M1BA2_1,UNUSED,,1,,,,,,,,,
K14,,IOBS,IO_L39N_M1ODT_1,UNUSED,,1,,,,,,,,,
K15,,IOBM,IO_L41P_GCLK9_IRDY1_M1RASN_1,UNUSED,,1,,,,,,,,,
K16,,IOBS,IO_L41N_GCLK8_M1CASN_1,UNUSED,,1,,,,,,,,,
K17,,IOBM,IO_L45P_A1_M1LDQS_1,UNUSED,,1,,,,,,,,,
K18,,IOBS,IO_L45N_A0_M1LDQSN_1,UNUSED,,1,,,,,,,,,
L1,,IOBS,IO_L37N_M3DQ1_3,UNUSED,,3,,,,,,,,,
L2,,IOBM,IO_L37P_M3DQ0_3,UNUSED,,3,,,,,,,,,
L3,,IOBS,IO_L39N_M3LDQSN_3,UNUSED,,3,,,,,,,,,
L4,,IOBM,IO_L39P_M3LDQS_3,UNUSED,,3,,,,,,,,,
L5,,IOBM,IO_L43P_GCLK23_M3RASN_3,UNUSED,,3,,,,,,,,,
L6,,IOBM,IO_L31P_3,UNUSED,,3,,,,,,,,,
L7,,IOBM,IO_L45P_M3A3_3,UNUSED,,3,,,,,,,,,
L8,,,VCCINT,,,,,,,,1.2,,,,
L9,,,GND,,,,,,,,,,,,
L10,,,VCCINT,,,,,,,,1.2,,,,
L11,,,GND,,,,,,,,,,,,
L12,,IOBM,IO_L40P_GCLK11_M1A5_1,UNUSED,,1,,,,,,,,,
L13,,IOBS,IO_L40N_GCLK10_M1A6_1,UNUSED,,1,,,,,,,,,
L14,,IOBM,IO_L61P_1,UNUSED,,1,,,,,,,,,
L15,GPIO<3>,IOB,IO_L42P_GCLK7_M1UDM_1,INPUT,LVCMOS25*,1,,,,NONE,,LOCATED,NO,NONE,
L16,,IOBS,IO_L42N_GCLK6_TRDY1_M1LDM_1,UNUSED,,1,,,,,,,,,
L17,,IOBM,IO_L46P_FCS_B_M1DQ2_1,UNUSED,,1,,,,,,,,,
L18,,IOBS,IO_L46N_FOE_B_M1DQ3_1,UNUSED,,1,,,,,,,,,
M1,,IOBS,IO_L36N_M3DQ9_3,UNUSED,,3,,,,,,,,,
M2,,,GND,,,,,,,,,,,,
M3,,IOBM,IO_L36P_M3DQ8_3,UNUSED,,3,,,,,,,,,
M4,,,VCCO_3,,,3,,,,,any******,,,,
M5,,IOBS,IO_L31N_VREF_3,UNUSED,,3,,,,,,,,,
M6,,,GND,,,,,,,,,,,,
M7,,,VCCINT,,,,,,,,1.2,,,,
M8,,IOBM,IO_L40P_2,UNUSED,,2,,,,,,,,,
M9,,,VCCAUX,,,,,,,,2.5,,,,
M10,,IOBM,IO_L22P_2,UNUSED,,2,,,,,,,,,
M11,,IOBM,IO_L15P_2,UNUSED,,2,,,,,,,,,
M12,,,VCCINT,,,,,,,,1.2,,,,
M13,,IOBS,IO_L61N_1,UNUSED,,1,,,,,,,,,
M14,,IOBM,IO_L53P_1,UNUSED,,1,,,,,,,,,
M15,,,VCCO_1,,,1,,,,,2.50,,,,
M16,,IOBM,IO_L47P_FWE_B_M1DQ0_1,UNUSED,,1,,,,,,,,,
M17,,,GND,,,,,,,,,,,,
M18,GPIO<1>,IOB,IO_L47N_LDC_M1DQ1_1,OUTPUT,LVCMOS25*,1,12,SLOW,,,,LOCATED,NO,NONE,
N1,,IOBS,IO_L35N_M3DQ11_3,UNUSED,,3,,,,,,,,,
N2,,IOBM,IO_L35P_M3DQ10_3,UNUSED,,3,,,,,,,,,
N3,,IOBS,IO_L1N_VREF_3,UNUSED,,3,,,,,,,,,
N4,,IOBM,IO_L1P_3,UNUSED,,3,,,,,,,,,
N5,,IOBM,IO_L64P_D8_2,UNUSED,,2,,,,,,,,,
N6,,IOBM,IO_L47P_2,UNUSED,,2,,,,,,,,,
N7,,IOBM,IO_L44P_2,UNUSED,,2,,,,,,,,,
N8,,IOBS,IO_L40N_2,UNUSED,,2,,,,,,,,,
N9,,IOBS,IO_L22N_2,UNUSED,,2,,,,,,,,,
N10,,IOBM,IO_L20P_2,UNUSED,,2,,,,,,,,,
N11,,IOBS,IO_L15N_2,UNUSED,,2,,,,,,,,,
N12,,IOBM,IO_L13P_M1_2,UNUSED,,2,,,,,,,,,
N13,,,GND,,,,,,,,,,,,
N14,,IOBS,IO_L53N_VREF_1,UNUSED,,1,,,,,,,,,
N15,,IOBM,IO_L50P_M1UDQS_1,UNUSED,,1,,,,,,,,,
N16,,IOBS,IO_L50N_M1UDQSN_1,UNUSED,,1,,,,,,,,,
N17,GPIO<0>,IOB,IO_L48P_HDC_M1DQ8_1,OUTPUT,LVCMOS25*,1,12,SLOW,,,,LOCATED,NO,NONE,
N18,,IOBS,IO_L48N_M1DQ9_1,UNUSED,,1,,,,,,,,,
P1,,IOBS,IO_L34N_M3UDQSN_3,UNUSED,,3,,,,,,,,,
P2,,IOBM,IO_L34P_M3UDQS_3,UNUSED,,3,,,,,,,,,
P3,,IOBS,IO_L2N_3,UNUSED,,3,,,,,,,,,
P4,BUT<0>,IOB,IO_L2P_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
P5,,,VCCAUX,,,,,,,,2.5,,,,
P6,,IOBS,IO_L64N_D9_2,UNUSED,,2,,,,,,,,,
P7,,IOBS,IO_L47N_2,UNUSED,,2,,,,,,,,,
P8,,IOBS,IO_L44N_2,UNUSED,,2,,,,,,,,,
P9,,,VCCO_2,,,2,,,,,any******,,,,
P10,,,VCCAUX,,,,,,,,2.5,,,,
P11,,IOBS,IO_L20N_2,UNUSED,,2,,,,,,,,,
P12,GPIO<7>,IOB,IO_L13N_D10_2,INPUT,LVCMOS25*,2,,,,NONE,,LOCATED,NO,NONE,
P13,,,CMPCS_B_2,,,,,,,,,,,,
P14,,,VCCAUX,,,,,,,,2.5,,,,
P15,,IOBM,IO_L74P_AWAKE_1,UNUSED,,1,,,,,,,,,
P16,,IOBS,IO_L74N_DOUT_BUSY_1,UNUSED,,1,,,,,,,,,
P17,,IOBM,IO_L49P_M1DQ10_1,UNUSED,,1,,,,,,,,,
P18,,IOBS,IO_L49N_M1DQ11_1,UNUSED,,1,,,,,,,,,
R1,,,GND,,,,,,,,,,,,
R2,,,VCCO_3,,,3,,,,,any******,,,,
R3,,IOBM,IO_L62P_D5_2,UNUSED,,2,,,,,,,,,
R4,,,GND,,,,,,,,,,,,
R5,,IOBM,IO_L48P_D7_2,UNUSED,,2,,,,,,,,,
R6,,,VCCO_2,,,2,,,,,any******,,,,
R7,,IOBM,IO_L46P_2,UNUSED,,2,,,,,,,,,
R8,,IOBM,IO_L31P_GCLK31_D14_2,UNUSED,,2,,,,,,,,,
R9,,,GND,,,,,,,,,,,,
R10,,IOBM,IO_L29P_GCLK3_2,UNUSED,,2,,,,,,,,,
R11,,IOBM,IO_L16P_2,UNUSED,,2,,,,,,,,,
R12,,,VCCO_2,,,2,,,,,any******,,,,
R13,,IOBM,IO_L3P_D0_DIN_MISO_MISO1_2,UNUSED,,2,,,,,,,,,
R14,,,GND,,,,,,,,,,,,
R15,,IOBM,IO_L1P_CCLK_2,UNUSED,,2,,,,,,,,,
R16,,,SUSPEND,,,,,,,,,,,,
R17,,,VCCO_1,,,1,,,,,2.50,,,,
R18,,,GND,,,,,,,,,,,,
T1,,IOBS,IO_L33N_M3DQ13_3,UNUSED,,3,,,,,,,,,
T2,,IOBM,IO_L33P_M3DQ12_3,UNUSED,,3,,,,,,,,,
T3,,IOBS,IO_L62N_D6_2,UNUSED,,2,,,,,,,,,
T4,,IOBM,IO_L63P_2,UNUSED,,2,,,,,,,,,
T5,,IOBS,IO_L48N_RDWR_B_VREF_2,UNUSED,,2,,,,,,,,,
T6,,IOBM,IO_L45P_2,UNUSED,,2,,,,,,,,,
T7,,IOBS,IO_L46N_2,UNUSED,,2,,,,,,,,,
T8,,IOBS,IO_L31N_GCLK30_D15_2,UNUSED,,2,,,,,,,,,
T9,,IOBM,IO_L32P_GCLK29_2,UNUSED,,2,,,,,,,,,
T10,,IOBS,IO_L29N_GCLK2_2,UNUSED,,2,,,,,,,,,
T11,,IOBS,IO_L16N_VREF_2,UNUSED,,2,,,,,,,,,
T12,,IOBM,IO_L19P_2,UNUSED,,2,,,,,,,,,
T13,,IOBS,IO_L3N_MOSI_CSI_B_MISO0_2,UNUSED,,2,,,,,,,,,
T14,,IOBM,IO_L12P_D1_MISO2_2,UNUSED,,2,,,,,,,,,
T15,,IOBS,IO_L1N_M0_CMPMISO_2,UNUSED,,2,,,,,,,,,
T16,,,GND,,,,,,,,,,,,
T17,,IOBM,IO_L51P_M1DQ12_1,UNUSED,,1,,,,,,,,,
T18,,IOBS,IO_L51N_M1DQ13_1,UNUSED,,1,,,,,,,,,
U1,,IOBS,IO_L32N_M3DQ15_3,UNUSED,,3,,,,,,,,,
U2,,IOBM,IO_L32P_M3DQ14_3,UNUSED,,3,,,,,,,,,
U3,,IOBM,IO_L65P_INIT_B_2,UNUSED,,2,,,,,,,,,
U4,,,VCCO_2,,,2,,,,,any******,,,,
U5,,IOBM,IO_L49P_D3_2,UNUSED,,2,,,,,,,,,
U6,,,GND,,,,,,,,,,,,
U7,,IOBM,IO_L43P_2,UNUSED,,2,,,,,,,,,
U8,,IOBM,IO_L41P_2,UNUSED,,2,,,,,,,,,
U9,,,VCCO_2,,,2,,,,,any******,,,,
U10,,IOBM,IO_L30P_GCLK1_D13_2,UNUSED,,2,,,,,,,,,
U11,,IOBM,IO_L23P_2,UNUSED,,2,,,,,,,,,
U12,,,GND,,,,,,,,,,,,
U13,,IOBM,IO_L14P_D11_2,UNUSED,,2,,,,,,,,,
U14,,,VCCO_2,,,2,,,,,any******,,,,
U15,,IOBM,IO_L5P_2,UNUSED,,2,,,,,,,,,
U16,,IOBM,IO_L2P_CMPCLK_2,UNUSED,,2,,,,,,,,,
U17,,IOBM,IO_L52P_M1DQ14_1,UNUSED,,1,,,,,,,,,
U18,,IOBS,IO_L52N_M1DQ15_1,UNUSED,,1,,,,,,,,,
V1,,,GND,,,,,,,,,,,,
V2,,,PROGRAM_B_2,,,,,,,,,,,,
V3,,IOBS,IO_L65N_CSO_B_2,UNUSED,,2,,,,,,,,,
V4,,IOBS,IO_L63N_2,UNUSED,,2,,,,,,,,,
V5,,IOBS,IO_L49N_D4_2,UNUSED,,2,,,,,,,,,
V6,,IOBS,IO_L45N_2,UNUSED,,2,,,,,,,,,
V7,,IOBS,IO_L43N_2,UNUSED,,2,,,,,,,,,
V8,,IOBS,IO_L41N_VREF_2,UNUSED,,2,,,,,,,,,
V9,,IOBS,IO_L32N_GCLK28_2,UNUSED,,2,,,,,,,,,
V10,CLK27MHz,IOB,IO_L30N_GCLK0_USERCCLK_2,INPUT,LVCMOS25*,2,,,,NONE,,LOCATED,NO,NONE,
V11,,IOBS,IO_L23N_2,UNUSED,,2,,,,,,,,,
V12,,IOBS,IO_L19N_2,UNUSED,,2,,,,,,,,,
V13,DIPSW<3>,IOB,IO_L14N_D12_2,INPUT,LVCMOS25*,2,,,,NONE,,LOCATED,NO,NONE,
V14,,IOBS,IO_L12N_D2_MISO3_2,UNUSED,,2,,,,,,,,,
V15,,IOBS,IO_L5N_2,UNUSED,,2,,,,,,,,,
V16,,IOBS,IO_L2N_CMPMOSI_2,UNUSED,,2,,,,,,,,,
V17,,,DONE_2,,,,,,,,,,,,
V18,,,GND,,,,,,,,,,,,
# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
#
#* Default value.
#** This default Pullup/Pulldown value can be overridden in Bitgen.
#****** Special VCCO requirements may apply. Please consult the device
# family datasheet for specific guideline on VCCO requirements.
#
#
#
1 #Release 14.7 - par P.20131013 (nt64)
2 #Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
3 #Wed Jun 08 11:35:52 2022
4 #
5 ## NOTE: This file is designed to be imported into a spreadsheet program
6 # such as Microsoft Excel for viewing, printing and sorting. The |
7 # character is used as the data field separator. This file is also designed
8 # to support parsing.
9 #
10 #INPUT FILE: textovhdl_map.ncd
11 #OUTPUT FILE: textovhdl_pad.csv
12 #PART TYPE: xc6slx16
13 #SPEED GRADE: -2
14 #PACKAGE: csg324
15 #
16 # Pinout by Pin Number:
17 #
18 # -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
19 Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,Drive (mA),Slew Rate,Termination,IOB Delay,Voltage,Constraint,IO Register,Signal Integrity,
20 A1,,,GND,,,,,,,,,,,,
21 A2,,IOBS,IO_L2N_0,UNUSED,,0,,,,,,,,,
22 A3,GPIO<2>,IOB,IO_L4N_0,OUTPUT,LVCMOS25*,0,12,SLOW,,,,LOCATED,NO,NONE,
23 A4,,IOBS,IO_L5N_0,UNUSED,,0,,,,,,,,,
24 A5,,IOBS,IO_L6N_0,UNUSED,,0,,,,,,,,,
25 A6,,IOBS,IO_L8N_VREF_0,UNUSED,,0,,,,,,,,,
26 A7,,IOBS,IO_L10N_0,UNUSED,,0,,,,,,,,,
27 A8,,IOBS,IO_L33N_0,UNUSED,,0,,,,,,,,,
28 A9,,IOBS,IO_L35N_GCLK16_0,UNUSED,,0,,,,,,,,,
29 A10,,IOBS,IO_L37N_GCLK12_0,UNUSED,,0,,,,,,,,,
30 A11,,IOBS,IO_L39N_0,UNUSED,,0,,,,,,,,,
31 A12,,IOBS,IO_L41N_0,UNUSED,,0,,,,,,,,,
32 A13,,IOBS,IO_L50N_0,UNUSED,,0,,,,,,,,,
33 A14,,IOBS,IO_L62N_VREF_0,UNUSED,,0,,,,,,,,,
34 A15,,IOBS,IO_L64N_SCP4_0,UNUSED,,0,,,,,,,,,
35 A16,,IOBS,IO_L66N_SCP0_0,UNUSED,,0,,,,,,,,,
36 A17,,,TCK,,,,,,,,,,,,
37 A18,,,GND,,,,,,,,,,,,
38 B1,,,VCCAUX,,,,,,,,2.5,,,,
39 B2,,IOBM,IO_L2P_0,UNUSED,,0,,,,,,,,,
40 B3,,IOBM,IO_L4P_0,UNUSED,,0,,,,,,,,,
41 B4,GPIO<5>,IOB,IO_L5P_0,INPUT,LVCMOS25*,0,,,,NONE,,LOCATED,NO,NONE,
42 B5,,,VCCO_0,,,0,,,,,2.50,,,,
43 B6,,IOBM,IO_L8P_0,UNUSED,,0,,,,,,,,,
44 B7,,,GND,,,,,,,,,,,,
45 B8,,IOBM,IO_L33P_0,UNUSED,,0,,,,,,,,,
46 B9,,IOBM,IO_L35P_GCLK17_0,UNUSED,,0,,,,,,,,,
47 B10,,,VCCO_0,,,0,,,,,2.50,,,,
48 B11,,IOBM,IO_L39P_0,UNUSED,,0,,,,,,,,,
49 B12,,IOBM,IO_L41P_0,UNUSED,,0,,,,,,,,,
50 B13,,,GND,,,,,,,,,,,,
51 B14,,IOBM,IO_L62P_0,UNUSED,,0,,,,,,,,,
52 B15,,,VCCO_0,,,0,,,,,2.50,,,,
53 B16,,IOBM,IO_L66P_SCP1_0,UNUSED,,0,,,,,,,,,
54 B17,,,VCCAUX,,,,,,,,2.5,,,,
55 B18,,,TMS,,,,,,,,,,,,
56 C1,,IOBS,IO_L83N_VREF_3,UNUSED,,3,,,,,,,,,
57 C2,,IOBM,IO_L83P_3,UNUSED,,3,,,,,,,,,
58 C3,,,GND,,,,,,,,,,,,
59 C4,,IOBS,IO_L1N_VREF_0,UNUSED,,0,,,,,,,,,
60 C5,,IOBM,IO_L6P_0,UNUSED,,0,,,,,,,,,
61 C6,,IOBS,IO_L3N_0,UNUSED,,0,,,,,,,,,
62 C7,,IOBM,IO_L10P_0,UNUSED,,0,,,,,,,,,
63 C8,,IOBS,IO_L11N_0,UNUSED,,0,,,,,,,,,
64 C9,,IOBS,IO_L34N_GCLK18_0,UNUSED,,0,,,,,,,,,
65 C10,,IOBM,IO_L37P_GCLK13_0,UNUSED,,0,,,,,,,,,
66 C11,,IOBS,IO_L36N_GCLK14_0,UNUSED,,0,,,,,,,,,
67 C12,,IOBS,IO_L47N_0,UNUSED,,0,,,,,,,,,
68 C13,,IOBM,IO_L50P_0,UNUSED,,0,,,,,,,,,
69 C14,,IOBS,IO_L65N_SCP2_0,UNUSED,,0,,,,,,,,,
70 C15,,IOBM,IO_L64P_SCP5_0,UNUSED,,0,,,,,,,,,
71 C16,,,GND,,,,,,,,,,,,
72 C17,,IOBM,IO_L29P_A23_M1A13_1,UNUSED,,1,,,,,,,,,
73 C18,,IOBS,IO_L29N_A22_M1A14_1,UNUSED,,1,,,,,,,,,
74 D1,,IOBS,IO_L52N_M3A9_3,UNUSED,,3,,,,,,,,,
75 D2,,IOBM,IO_L52P_M3A8_3,UNUSED,,3,,,,,,,,,
76 D3,,IOBS,IO_L54N_M3A11_3,UNUSED,,3,,,,,,,,,
77 D4,,IOBM,IO_L1P_HSWAPEN_0,UNUSED,,0,,,,,,,,,
78 D5,,,GND,,,,,,,,,,,,
79 D6,,IOBM,IO_L3P_0,UNUSED,,0,,,,,,,,,
80 D7,,,VCCO_0,,,0,,,,,2.50,,,,
81 D8,,IOBM,IO_L11P_0,UNUSED,,0,,,,,,,,,
82 D9,,IOBM,IO_L34P_GCLK19_0,UNUSED,,0,,,,,,,,,
83 D10,,,GND,,,,,,,,,,,,
84 D11,,IOBM,IO_L36P_GCLK15_0,UNUSED,,0,,,,,,,,,
85 D12,,IOBM,IO_L47P_0,UNUSED,,0,,,,,,,,,
86 D13,,,VCCO_0,,,0,,,,,2.50,,,,
87 D14,DIPSW<0>,IOB,IO_L65P_SCP3_0,INPUT,LVCMOS25*,0,,,,NONE,,LOCATED,NO,NONE,
88 D15,,,TDI,,,,,,,,,,,,
89 D16,,,TDO,,,,,,,,,,,,
90 D17,,IOBM,IO_L31P_A19_M1CKE_1,UNUSED,,1,,,,,,,,,
91 D18,,IOBS,IO_L31N_A18_M1A12_1,UNUSED,,1,,,,,,,,,
92 E1,,IOBS,IO_L50N_M3BA2_3,UNUSED,,3,,,,,,,,,
93 E2,,,VCCO_3,,,3,,,,,any******,,,,
94 E3,,IOBM,IO_L50P_M3WE_3,UNUSED,,3,,,,,,,,,
95 E4,BUT<2>,IOB,IO_L54P_M3RESET_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
96 E5,,,VCCAUX,,,,,,,,2.5,,,,
97 E6,,IOBS,IO_L7N_0,UNUSED,,0,,,,,,,,,
98 E7,,IOBM,IO_L9P_0,UNUSED,,0,,,,,,,,,
99 E8,,IOBS,IO_L9N_0,UNUSED,,0,,,,,,,,,
100 E9,,,VCCAUX,,,,,,,,2.5,,,,
101 E10,,,VCCO_0,,,0,,,,,2.50,,,,
102 E11,,IOBS,IO_L42N_0,UNUSED,,0,,,,,,,,,
103 E12,DIPSW<1>,IOB,IO_L51N_0,INPUT,LVCMOS25*,0,,,,NONE,,LOCATED,NO,NONE,
104 E13,,IOBS,IO_L63N_SCP6_0,UNUSED,,0,,,,,,,,,
105 E14,,,VCCAUX,,,,,,,,2.5,,,,
106 E15,,,GND,,,,,,,,,,,,
107 E16,,IOBM,IO_L33P_A15_M1A10_1,UNUSED,,1,,,,,,,,,
108 E17,,,VCCO_1,,,1,,,,,2.50,,,,
109 E18,,IOBS,IO_L33N_A14_M1A4_1,UNUSED,,1,,,,,,,,,
110 F1,,IOBS,IO_L48N_M3BA1_3,UNUSED,,3,,,,,,,,,
111 F2,,IOBM,IO_L48P_M3BA0_3,UNUSED,,3,,,,,,,,,
112 F3,,IOBS,IO_L51N_M3A4_3,UNUSED,,3,,,,,,,,,
113 F4,,IOBM,IO_L51P_M3A10_3,UNUSED,,3,,,,,,,,,
114 F5,BUT<3>,IOB,IO_L55N_M3A14_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
115 F6,BUT<1>,IOB,IO_L55P_M3A13_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
116 F7,,IOBM,IO_L7P_0,UNUSED,,0,,,,,,,,,
117 F8,,IOBS,IO_L32N_0,UNUSED,,0,,,,,,,,,
118 F9,,IOBS,IO_L38N_VREF_0,UNUSED,,0,,,,,,,,,
119 F10,,IOBS,IO_L40N_0,UNUSED,,0,,,,,,,,,
120 F11,,IOBM,IO_L42P_0,UNUSED,,0,,,,,,,,,
121 F12,DIPSW<2>,IOB,IO_L51P_0,INPUT,LVCMOS25*,0,,,,NONE,,LOCATED,NO,NONE,
122 F13,GPIO<6>,IOB,IO_L63P_SCP7_0,INPUT,LVCMOS25*,0,,,,NONE,,LOCATED,NO,NONE,
123 F14,,IOBM,IO_L30P_A21_M1RESET_1,UNUSED,,1,,,,,,,,,
124 F15,GPIO<4>,IOB,IO_L1P_A25_1,INPUT,LVCMOS25*,1,,,,NONE,,LOCATED,NO,NONE,
125 F16,,IOBS,IO_L1N_A24_VREF_1,UNUSED,,1,,,,,,,,,
126 F17,,IOBM,IO_L35P_A11_M1A7_1,UNUSED,,1,,,,,,,,,
127 F18,,IOBS,IO_L35N_A10_M1A2_1,UNUSED,,1,,,,,,,,,
128 G1,,IOBS,IO_L46N_M3CLKN_3,UNUSED,,3,,,,,,,,,
129 G2,,,GND,,,,,,,,,,,,
130 G3,,IOBM,IO_L46P_M3CLK_3,UNUSED,,3,,,,,,,,,
131 G4,,,VCCO_3,,,3,,,,,any******,,,,
132 G5,,,GND,,,,,,,,,,,,
133 G6,,IOBS,IO_L53N_M3A12_3,UNUSED,,3,,,,,,,,,
134 G7,,,VCCINT,,,,,,,,1.2,,,,
135 G8,,IOBM,IO_L32P_0,UNUSED,,0,,,,,,,,,
136 G9,,IOBM,IO_L38P_0,UNUSED,,0,,,,,,,,,
137 G10,,,VCCAUX,,,,,,,,2.5,,,,
138 G11,,IOBM,IO_L40P_0,UNUSED,,0,,,,,,,,,
139 G12,,,GND,,,,,,,,,,,,
140 G13,,IOBS,IO_L32N_A16_M1A9_1,UNUSED,,1,,,,,,,,,
141 G14,,IOBS,IO_L30N_A20_M1A11_1,UNUSED,,1,,,,,,,,,
142 G15,,,VCCO_1,,,1,,,,,2.50,,,,
143 G16,,IOBM,IO_L38P_A5_M1CLK_1,UNUSED,,1,,,,,,,,,
144 G17,,,GND,,,,,,,,,,,,
145 G18,,IOBS,IO_L38N_A4_M1CLKN_1,UNUSED,,1,,,,,,,,,
146 H1,,IOBS,IO_L41N_GCLK26_M3DQ5_3,UNUSED,,3,,,,,,,,,
147 H2,,IOBM,IO_L41P_GCLK27_M3DQ4_3,UNUSED,,3,,,,,,,,,
148 H3,,IOBS,IO_L44N_GCLK20_M3A6_3,UNUSED,,3,,,,,,,,,
149 H4,,IOBM,IO_L44P_GCLK21_M3A5_3,UNUSED,,3,,,,,,,,,
150 H5,,IOBS,IO_L49N_M3A2_3,UNUSED,,3,,,,,,,,,
151 H6,,IOBM,IO_L49P_M3A7_3,UNUSED,,3,,,,,,,,,
152 H7,,IOBM,IO_L53P_M3CKE_3,UNUSED,,3,,,,,,,,,
153 H8,,,GND,,,,,,,,,,,,
154 H9,,,VCCINT,,,,,,,,1.2,,,,
155 H10,,,GND,,,,,,,,,,,,
156 H11,,,VCCINT,,,,,,,,1.2,,,,
157 H12,,IOBM,IO_L32P_A17_M1A8_1,UNUSED,,1,,,,,,,,,
158 H13,,IOBM,IO_L36P_A9_M1BA0_1,UNUSED,,1,,,,,,,,,
159 H14,,IOBS,IO_L36N_A8_M1BA1_1,UNUSED,,1,,,,,,,,,
160 H15,,IOBM,IO_L37P_A7_M1A0_1,UNUSED,,1,,,,,,,,,
161 H16,,IOBS,IO_L37N_A6_M1A1_1,UNUSED,,1,,,,,,,,,
162 H17,,IOBM,IO_L43P_GCLK5_M1DQ4_1,UNUSED,,1,,,,,,,,,
163 H18,,IOBS,IO_L43N_GCLK4_M1DQ5_1,UNUSED,,1,,,,,,,,,
164 J1,,IOBS,IO_L40N_M3DQ7_3,UNUSED,,3,,,,,,,,,
165 J2,,,VCCO_3,,,3,,,,,any******,,,,
166 J3,,IOBM,IO_L40P_M3DQ6_3,UNUSED,,3,,,,,,,,,
167 J4,,,GND,,,,,,,,,,,,
168 J5,,,VCCO_3,,,3,,,,,any******,,,,
169 J6,,IOBS,IO_L47N_M3A1_3,UNUSED,,3,,,,,,,,,
170 J7,,IOBM,IO_L47P_M3A0_3,UNUSED,,3,,,,,,,,,
171 J8,,,VCCINT,,,,,,,,1.2,,,,
172 J9,,,GND,,,,,,,,,,,,
173 J10,,,VCCINT,,,,,,,,1.2,,,,
174 J11,,,GND,,,,,,,,,,,,
175 J12,,,VCCAUX,,,,,,,,2.5,,,,
176 J13,,IOBM,IO_L39P_M1A3_1,UNUSED,,1,,,,,,,,,
177 J14,,,VCCO_1,,,1,,,,,2.50,,,,
178 J15,,,GND,,,,,,,,,,,,
179 J16,,IOBM,IO_L44P_A3_M1DQ6_1,UNUSED,,1,,,,,,,,,
180 J17,,,VCCO_1,,,1,,,,,2.50,,,,
181 J18,,IOBS,IO_L44N_A2_M1DQ7_1,UNUSED,,1,,,,,,,,,
182 K1,,IOBS,IO_L38N_M3DQ3_3,UNUSED,,3,,,,,,,,,
183 K2,,IOBM,IO_L38P_M3DQ2_3,UNUSED,,3,,,,,,,,,
184 K3,,IOBS,IO_L42N_GCLK24_M3LDM_3,UNUSED,,3,,,,,,,,,
185 K4,,IOBM,IO_L42P_GCLK25_TRDY2_M3UDM_3,UNUSED,,3,,,,,,,,,
186 K5,,IOBS,IO_L43N_GCLK22_IRDY2_M3CASN_3,UNUSED,,3,,,,,,,,,
187 K6,,IOBS,IO_L45N_M3ODT_3,UNUSED,,3,,,,,,,,,
188 K7,,,VCCAUX,,,,,,,,2.5,,,,
189 K8,,,GND,,,,,,,,,,,,
190 K9,,,VCCINT,,,,,,,,1.2,,,,
191 K10,,,GND,,,,,,,,,,,,
192 K11,,,VCCINT,,,,,,,,1.2,,,,
193 K12,,IOBM,IO_L34P_A13_M1WE_1,UNUSED,,1,,,,,,,,,
194 K13,,IOBS,IO_L34N_A12_M1BA2_1,UNUSED,,1,,,,,,,,,
195 K14,,IOBS,IO_L39N_M1ODT_1,UNUSED,,1,,,,,,,,,
196 K15,,IOBM,IO_L41P_GCLK9_IRDY1_M1RASN_1,UNUSED,,1,,,,,,,,,
197 K16,,IOBS,IO_L41N_GCLK8_M1CASN_1,UNUSED,,1,,,,,,,,,
198 K17,,IOBM,IO_L45P_A1_M1LDQS_1,UNUSED,,1,,,,,,,,,
199 K18,,IOBS,IO_L45N_A0_M1LDQSN_1,UNUSED,,1,,,,,,,,,
200 L1,,IOBS,IO_L37N_M3DQ1_3,UNUSED,,3,,,,,,,,,
201 L2,,IOBM,IO_L37P_M3DQ0_3,UNUSED,,3,,,,,,,,,
202 L3,,IOBS,IO_L39N_M3LDQSN_3,UNUSED,,3,,,,,,,,,
203 L4,,IOBM,IO_L39P_M3LDQS_3,UNUSED,,3,,,,,,,,,
204 L5,,IOBM,IO_L43P_GCLK23_M3RASN_3,UNUSED,,3,,,,,,,,,
205 L6,,IOBM,IO_L31P_3,UNUSED,,3,,,,,,,,,
206 L7,,IOBM,IO_L45P_M3A3_3,UNUSED,,3,,,,,,,,,
207 L8,,,VCCINT,,,,,,,,1.2,,,,
208 L9,,,GND,,,,,,,,,,,,
209 L10,,,VCCINT,,,,,,,,1.2,,,,
210 L11,,,GND,,,,,,,,,,,,
211 L12,,IOBM,IO_L40P_GCLK11_M1A5_1,UNUSED,,1,,,,,,,,,
212 L13,,IOBS,IO_L40N_GCLK10_M1A6_1,UNUSED,,1,,,,,,,,,
213 L14,,IOBM,IO_L61P_1,UNUSED,,1,,,,,,,,,
214 L15,GPIO<3>,IOB,IO_L42P_GCLK7_M1UDM_1,INPUT,LVCMOS25*,1,,,,NONE,,LOCATED,NO,NONE,
215 L16,,IOBS,IO_L42N_GCLK6_TRDY1_M1LDM_1,UNUSED,,1,,,,,,,,,
216 L17,,IOBM,IO_L46P_FCS_B_M1DQ2_1,UNUSED,,1,,,,,,,,,
217 L18,,IOBS,IO_L46N_FOE_B_M1DQ3_1,UNUSED,,1,,,,,,,,,
218 M1,,IOBS,IO_L36N_M3DQ9_3,UNUSED,,3,,,,,,,,,
219 M2,,,GND,,,,,,,,,,,,
220 M3,,IOBM,IO_L36P_M3DQ8_3,UNUSED,,3,,,,,,,,,
221 M4,,,VCCO_3,,,3,,,,,any******,,,,
222 M5,,IOBS,IO_L31N_VREF_3,UNUSED,,3,,,,,,,,,
223 M6,,,GND,,,,,,,,,,,,
224 M7,,,VCCINT,,,,,,,,1.2,,,,
225 M8,,IOBM,IO_L40P_2,UNUSED,,2,,,,,,,,,
226 M9,,,VCCAUX,,,,,,,,2.5,,,,
227 M10,,IOBM,IO_L22P_2,UNUSED,,2,,,,,,,,,
228 M11,,IOBM,IO_L15P_2,UNUSED,,2,,,,,,,,,
229 M12,,,VCCINT,,,,,,,,1.2,,,,
230 M13,,IOBS,IO_L61N_1,UNUSED,,1,,,,,,,,,
231 M14,,IOBM,IO_L53P_1,UNUSED,,1,,,,,,,,,
232 M15,,,VCCO_1,,,1,,,,,2.50,,,,
233 M16,,IOBM,IO_L47P_FWE_B_M1DQ0_1,UNUSED,,1,,,,,,,,,
234 M17,,,GND,,,,,,,,,,,,
235 M18,GPIO<1>,IOB,IO_L47N_LDC_M1DQ1_1,OUTPUT,LVCMOS25*,1,12,SLOW,,,,LOCATED,NO,NONE,
236 N1,,IOBS,IO_L35N_M3DQ11_3,UNUSED,,3,,,,,,,,,
237 N2,,IOBM,IO_L35P_M3DQ10_3,UNUSED,,3,,,,,,,,,
238 N3,,IOBS,IO_L1N_VREF_3,UNUSED,,3,,,,,,,,,
239 N4,,IOBM,IO_L1P_3,UNUSED,,3,,,,,,,,,
240 N5,,IOBM,IO_L64P_D8_2,UNUSED,,2,,,,,,,,,
241 N6,,IOBM,IO_L47P_2,UNUSED,,2,,,,,,,,,
242 N7,,IOBM,IO_L44P_2,UNUSED,,2,,,,,,,,,
243 N8,,IOBS,IO_L40N_2,UNUSED,,2,,,,,,,,,
244 N9,,IOBS,IO_L22N_2,UNUSED,,2,,,,,,,,,
245 N10,,IOBM,IO_L20P_2,UNUSED,,2,,,,,,,,,
246 N11,,IOBS,IO_L15N_2,UNUSED,,2,,,,,,,,,
247 N12,,IOBM,IO_L13P_M1_2,UNUSED,,2,,,,,,,,,
248 N13,,,GND,,,,,,,,,,,,
249 N14,,IOBS,IO_L53N_VREF_1,UNUSED,,1,,,,,,,,,
250 N15,,IOBM,IO_L50P_M1UDQS_1,UNUSED,,1,,,,,,,,,
251 N16,,IOBS,IO_L50N_M1UDQSN_1,UNUSED,,1,,,,,,,,,
252 N17,GPIO<0>,IOB,IO_L48P_HDC_M1DQ8_1,OUTPUT,LVCMOS25*,1,12,SLOW,,,,LOCATED,NO,NONE,
253 N18,,IOBS,IO_L48N_M1DQ9_1,UNUSED,,1,,,,,,,,,
254 P1,,IOBS,IO_L34N_M3UDQSN_3,UNUSED,,3,,,,,,,,,
255 P2,,IOBM,IO_L34P_M3UDQS_3,UNUSED,,3,,,,,,,,,
256 P3,,IOBS,IO_L2N_3,UNUSED,,3,,,,,,,,,
257 P4,BUT<0>,IOB,IO_L2P_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
258 P5,,,VCCAUX,,,,,,,,2.5,,,,
259 P6,,IOBS,IO_L64N_D9_2,UNUSED,,2,,,,,,,,,
260 P7,,IOBS,IO_L47N_2,UNUSED,,2,,,,,,,,,
261 P8,,IOBS,IO_L44N_2,UNUSED,,2,,,,,,,,,
262 P9,,,VCCO_2,,,2,,,,,any******,,,,
263 P10,,,VCCAUX,,,,,,,,2.5,,,,
264 P11,,IOBS,IO_L20N_2,UNUSED,,2,,,,,,,,,
265 P12,GPIO<7>,IOB,IO_L13N_D10_2,INPUT,LVCMOS25*,2,,,,NONE,,LOCATED,NO,NONE,
266 P13,,,CMPCS_B_2,,,,,,,,,,,,
267 P14,,,VCCAUX,,,,,,,,2.5,,,,
268 P15,,IOBM,IO_L74P_AWAKE_1,UNUSED,,1,,,,,,,,,
269 P16,,IOBS,IO_L74N_DOUT_BUSY_1,UNUSED,,1,,,,,,,,,
270 P17,,IOBM,IO_L49P_M1DQ10_1,UNUSED,,1,,,,,,,,,
271 P18,,IOBS,IO_L49N_M1DQ11_1,UNUSED,,1,,,,,,,,,
272 R1,,,GND,,,,,,,,,,,,
273 R2,,,VCCO_3,,,3,,,,,any******,,,,
274 R3,,IOBM,IO_L62P_D5_2,UNUSED,,2,,,,,,,,,
275 R4,,,GND,,,,,,,,,,,,
276 R5,,IOBM,IO_L48P_D7_2,UNUSED,,2,,,,,,,,,
277 R6,,,VCCO_2,,,2,,,,,any******,,,,
278 R7,,IOBM,IO_L46P_2,UNUSED,,2,,,,,,,,,
279 R8,,IOBM,IO_L31P_GCLK31_D14_2,UNUSED,,2,,,,,,,,,
280 R9,,,GND,,,,,,,,,,,,
281 R10,,IOBM,IO_L29P_GCLK3_2,UNUSED,,2,,,,,,,,,
282 R11,,IOBM,IO_L16P_2,UNUSED,,2,,,,,,,,,
283 R12,,,VCCO_2,,,2,,,,,any******,,,,
284 R13,,IOBM,IO_L3P_D0_DIN_MISO_MISO1_2,UNUSED,,2,,,,,,,,,
285 R14,,,GND,,,,,,,,,,,,
286 R15,,IOBM,IO_L1P_CCLK_2,UNUSED,,2,,,,,,,,,
287 R16,,,SUSPEND,,,,,,,,,,,,
288 R17,,,VCCO_1,,,1,,,,,2.50,,,,
289 R18,,,GND,,,,,,,,,,,,
290 T1,,IOBS,IO_L33N_M3DQ13_3,UNUSED,,3,,,,,,,,,
291 T2,,IOBM,IO_L33P_M3DQ12_3,UNUSED,,3,,,,,,,,,
292 T3,,IOBS,IO_L62N_D6_2,UNUSED,,2,,,,,,,,,
293 T4,,IOBM,IO_L63P_2,UNUSED,,2,,,,,,,,,
294 T5,,IOBS,IO_L48N_RDWR_B_VREF_2,UNUSED,,2,,,,,,,,,
295 T6,,IOBM,IO_L45P_2,UNUSED,,2,,,,,,,,,
296 T7,,IOBS,IO_L46N_2,UNUSED,,2,,,,,,,,,
297 T8,,IOBS,IO_L31N_GCLK30_D15_2,UNUSED,,2,,,,,,,,,
298 T9,,IOBM,IO_L32P_GCLK29_2,UNUSED,,2,,,,,,,,,
299 T10,,IOBS,IO_L29N_GCLK2_2,UNUSED,,2,,,,,,,,,
300 T11,,IOBS,IO_L16N_VREF_2,UNUSED,,2,,,,,,,,,
301 T12,,IOBM,IO_L19P_2,UNUSED,,2,,,,,,,,,
302 T13,,IOBS,IO_L3N_MOSI_CSI_B_MISO0_2,UNUSED,,2,,,,,,,,,
303 T14,,IOBM,IO_L12P_D1_MISO2_2,UNUSED,,2,,,,,,,,,
304 T15,,IOBS,IO_L1N_M0_CMPMISO_2,UNUSED,,2,,,,,,,,,
305 T16,,,GND,,,,,,,,,,,,
306 T17,,IOBM,IO_L51P_M1DQ12_1,UNUSED,,1,,,,,,,,,
307 T18,,IOBS,IO_L51N_M1DQ13_1,UNUSED,,1,,,,,,,,,
308 U1,,IOBS,IO_L32N_M3DQ15_3,UNUSED,,3,,,,,,,,,
309 U2,,IOBM,IO_L32P_M3DQ14_3,UNUSED,,3,,,,,,,,,
310 U3,,IOBM,IO_L65P_INIT_B_2,UNUSED,,2,,,,,,,,,
311 U4,,,VCCO_2,,,2,,,,,any******,,,,
312 U5,,IOBM,IO_L49P_D3_2,UNUSED,,2,,,,,,,,,
313 U6,,,GND,,,,,,,,,,,,
314 U7,,IOBM,IO_L43P_2,UNUSED,,2,,,,,,,,,
315 U8,,IOBM,IO_L41P_2,UNUSED,,2,,,,,,,,,
316 U9,,,VCCO_2,,,2,,,,,any******,,,,
317 U10,,IOBM,IO_L30P_GCLK1_D13_2,UNUSED,,2,,,,,,,,,
318 U11,,IOBM,IO_L23P_2,UNUSED,,2,,,,,,,,,
319 U12,,,GND,,,,,,,,,,,,
320 U13,,IOBM,IO_L14P_D11_2,UNUSED,,2,,,,,,,,,
321 U14,,,VCCO_2,,,2,,,,,any******,,,,
322 U15,,IOBM,IO_L5P_2,UNUSED,,2,,,,,,,,,
323 U16,,IOBM,IO_L2P_CMPCLK_2,UNUSED,,2,,,,,,,,,
324 U17,,IOBM,IO_L52P_M1DQ14_1,UNUSED,,1,,,,,,,,,
325 U18,,IOBS,IO_L52N_M1DQ15_1,UNUSED,,1,,,,,,,,,
326 V1,,,GND,,,,,,,,,,,,
327 V2,,,PROGRAM_B_2,,,,,,,,,,,,
328 V3,,IOBS,IO_L65N_CSO_B_2,UNUSED,,2,,,,,,,,,
329 V4,,IOBS,IO_L63N_2,UNUSED,,2,,,,,,,,,
330 V5,,IOBS,IO_L49N_D4_2,UNUSED,,2,,,,,,,,,
331 V6,,IOBS,IO_L45N_2,UNUSED,,2,,,,,,,,,
332 V7,,IOBS,IO_L43N_2,UNUSED,,2,,,,,,,,,
333 V8,,IOBS,IO_L41N_VREF_2,UNUSED,,2,,,,,,,,,
334 V9,,IOBS,IO_L32N_GCLK28_2,UNUSED,,2,,,,,,,,,
335 V10,CLK27MHz,IOB,IO_L30N_GCLK0_USERCCLK_2,INPUT,LVCMOS25*,2,,,,NONE,,LOCATED,NO,NONE,
336 V11,,IOBS,IO_L23N_2,UNUSED,,2,,,,,,,,,
337 V12,,IOBS,IO_L19N_2,UNUSED,,2,,,,,,,,,
338 V13,DIPSW<3>,IOB,IO_L14N_D12_2,INPUT,LVCMOS25*,2,,,,NONE,,LOCATED,NO,NONE,
339 V14,,IOBS,IO_L12N_D2_MISO3_2,UNUSED,,2,,,,,,,,,
340 V15,,IOBS,IO_L5N_2,UNUSED,,2,,,,,,,,,
341 V16,,IOBS,IO_L2N_CMPMOSI_2,UNUSED,,2,,,,,,,,,
342 V17,,,DONE_2,,,,,,,,,,,,
343 V18,,,GND,,,,,,,,,,,,
344 # -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
345 #
346 #* Default value.
347 #** This default Pullup/Pulldown value can be overridden in Bitgen.
348 #****** Special VCCO requirements may apply. Please consult the device
349 # family datasheet for specific guideline on VCCO requirements.
350 #
351 #
352 #

354
textovhdl_pad.txt Normal file
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@@ -0,0 +1,354 @@
Release 14.7 - par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Wed Jun 08 11:35:52 2022
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
1. The <design name>_pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors.
2. The <design namd>_pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information.
3. The <design name>.pad file designed for parsing by customers. It uses the "|" as a data field separator.
INPUT FILE: textovhdl_map.ncd
OUTPUT FILE: textovhdl_pad.txt
PART TYPE: xc6slx16
SPEED GRADE: -2
PACKAGE: csg324
Pinout by Pin Number:
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|Pin Number|Signal Name|Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|IO Register|Signal Integrity|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|A1 | | |GND | | | | | | | | | | | |
|A2 | |IOBS |IO_L2N_0 |UNUSED | |0 | | | | | | | | |
|A3 |GPIO<2> |IOB |IO_L4N_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW | | | |LOCATED |NO |NONE |
|A4 | |IOBS |IO_L5N_0 |UNUSED | |0 | | | | | | | | |
|A5 | |IOBS |IO_L6N_0 |UNUSED | |0 | | | | | | | | |
|A6 | |IOBS |IO_L8N_VREF_0 |UNUSED | |0 | | | | | | | | |
|A7 | |IOBS |IO_L10N_0 |UNUSED | |0 | | | | | | | | |
|A8 | |IOBS |IO_L33N_0 |UNUSED | |0 | | | | | | | | |
|A9 | |IOBS |IO_L35N_GCLK16_0 |UNUSED | |0 | | | | | | | | |
|A10 | |IOBS |IO_L37N_GCLK12_0 |UNUSED | |0 | | | | | | | | |
|A11 | |IOBS |IO_L39N_0 |UNUSED | |0 | | | | | | | | |
|A12 | |IOBS |IO_L41N_0 |UNUSED | |0 | | | | | | | | |
|A13 | |IOBS |IO_L50N_0 |UNUSED | |0 | | | | | | | | |
|A14 | |IOBS |IO_L62N_VREF_0 |UNUSED | |0 | | | | | | | | |
|A15 | |IOBS |IO_L64N_SCP4_0 |UNUSED | |0 | | | | | | | | |
|A16 | |IOBS |IO_L66N_SCP0_0 |UNUSED | |0 | | | | | | | | |
|A17 | | |TCK | | | | | | | | | | | |
|A18 | | |GND | | | | | | | | | | | |
|B1 | | |VCCAUX | | | | | | | |2.5 | | | |
|B2 | |IOBM |IO_L2P_0 |UNUSED | |0 | | | | | | | | |
|B3 | |IOBM |IO_L4P_0 |UNUSED | |0 | | | | | | | | |
|B4 |GPIO<5> |IOB |IO_L5P_0 |INPUT |LVCMOS25* |0 | | | |NONE | |LOCATED |NO |NONE |
|B5 | | |VCCO_0 | | |0 | | | | |2.50 | | | |
|B6 | |IOBM |IO_L8P_0 |UNUSED | |0 | | | | | | | | |
|B7 | | |GND | | | | | | | | | | | |
|B8 | |IOBM |IO_L33P_0 |UNUSED | |0 | | | | | | | | |
|B9 | |IOBM |IO_L35P_GCLK17_0 |UNUSED | |0 | | | | | | | | |
|B10 | | |VCCO_0 | | |0 | | | | |2.50 | | | |
|B11 | |IOBM |IO_L39P_0 |UNUSED | |0 | | | | | | | | |
|B12 | |IOBM |IO_L41P_0 |UNUSED | |0 | | | | | | | | |
|B13 | | |GND | | | | | | | | | | | |
|B14 | |IOBM |IO_L62P_0 |UNUSED | |0 | | | | | | | | |
|B15 | | |VCCO_0 | | |0 | | | | |2.50 | | | |
|B16 | |IOBM |IO_L66P_SCP1_0 |UNUSED | |0 | | | | | | | | |
|B17 | | |VCCAUX | | | | | | | |2.5 | | | |
|B18 | | |TMS | | | | | | | | | | | |
|C1 | |IOBS |IO_L83N_VREF_3 |UNUSED | |3 | | | | | | | | |
|C2 | |IOBM |IO_L83P_3 |UNUSED | |3 | | | | | | | | |
|C3 | | |GND | | | | | | | | | | | |
|C4 | |IOBS |IO_L1N_VREF_0 |UNUSED | |0 | | | | | | | | |
|C5 | |IOBM |IO_L6P_0 |UNUSED | |0 | | | | | | | | |
|C6 | |IOBS |IO_L3N_0 |UNUSED | |0 | | | | | | | | |
|C7 | |IOBM |IO_L10P_0 |UNUSED | |0 | | | | | | | | |
|C8 | |IOBS |IO_L11N_0 |UNUSED | |0 | | | | | | | | |
|C9 | |IOBS |IO_L34N_GCLK18_0 |UNUSED | |0 | | | | | | | | |
|C10 | |IOBM |IO_L37P_GCLK13_0 |UNUSED | |0 | | | | | | | | |
|C11 | |IOBS |IO_L36N_GCLK14_0 |UNUSED | |0 | | | | | | | | |
|C12 | |IOBS |IO_L47N_0 |UNUSED | |0 | | | | | | | | |
|C13 | |IOBM |IO_L50P_0 |UNUSED | |0 | | | | | | | | |
|C14 | |IOBS |IO_L65N_SCP2_0 |UNUSED | |0 | | | | | | | | |
|C15 | |IOBM |IO_L64P_SCP5_0 |UNUSED | |0 | | | | | | | | |
|C16 | | |GND | | | | | | | | | | | |
|C17 | |IOBM |IO_L29P_A23_M1A13_1 |UNUSED | |1 | | | | | | | | |
|C18 | |IOBS |IO_L29N_A22_M1A14_1 |UNUSED | |1 | | | | | | | | |
|D1 | |IOBS |IO_L52N_M3A9_3 |UNUSED | |3 | | | | | | | | |
|D2 | |IOBM |IO_L52P_M3A8_3 |UNUSED | |3 | | | | | | | | |
|D3 | |IOBS |IO_L54N_M3A11_3 |UNUSED | |3 | | | | | | | | |
|D4 | |IOBM |IO_L1P_HSWAPEN_0 |UNUSED | |0 | | | | | | | | |
|D5 | | |GND | | | | | | | | | | | |
|D6 | |IOBM |IO_L3P_0 |UNUSED | |0 | | | | | | | | |
|D7 | | |VCCO_0 | | |0 | | | | |2.50 | | | |
|D8 | |IOBM |IO_L11P_0 |UNUSED | |0 | | | | | | | | |
|D9 | |IOBM |IO_L34P_GCLK19_0 |UNUSED | |0 | | | | | | | | |
|D10 | | |GND | | | | | | | | | | | |
|D11 | |IOBM |IO_L36P_GCLK15_0 |UNUSED | |0 | | | | | | | | |
|D12 | |IOBM |IO_L47P_0 |UNUSED | |0 | | | | | | | | |
|D13 | | |VCCO_0 | | |0 | | | | |2.50 | | | |
|D14 |DIPSW<0> |IOB |IO_L65P_SCP3_0 |INPUT |LVCMOS25* |0 | | | |NONE | |LOCATED |NO |NONE |
|D15 | | |TDI | | | | | | | | | | | |
|D16 | | |TDO | | | | | | | | | | | |
|D17 | |IOBM |IO_L31P_A19_M1CKE_1 |UNUSED | |1 | | | | | | | | |
|D18 | |IOBS |IO_L31N_A18_M1A12_1 |UNUSED | |1 | | | | | | | | |
|E1 | |IOBS |IO_L50N_M3BA2_3 |UNUSED | |3 | | | | | | | | |
|E2 | | |VCCO_3 | | |3 | | | | |any******| | | |
|E3 | |IOBM |IO_L50P_M3WE_3 |UNUSED | |3 | | | | | | | | |
|E4 |BUT<2> |IOB |IO_L54P_M3RESET_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
|E5 | | |VCCAUX | | | | | | | |2.5 | | | |
|E6 | |IOBS |IO_L7N_0 |UNUSED | |0 | | | | | | | | |
|E7 | |IOBM |IO_L9P_0 |UNUSED | |0 | | | | | | | | |
|E8 | |IOBS |IO_L9N_0 |UNUSED | |0 | | | | | | | | |
|E9 | | |VCCAUX | | | | | | | |2.5 | | | |
|E10 | | |VCCO_0 | | |0 | | | | |2.50 | | | |
|E11 | |IOBS |IO_L42N_0 |UNUSED | |0 | | | | | | | | |
|E12 |DIPSW<1> |IOB |IO_L51N_0 |INPUT |LVCMOS25* |0 | | | |NONE | |LOCATED |NO |NONE |
|E13 | |IOBS |IO_L63N_SCP6_0 |UNUSED | |0 | | | | | | | | |
|E14 | | |VCCAUX | | | | | | | |2.5 | | | |
|E15 | | |GND | | | | | | | | | | | |
|E16 | |IOBM |IO_L33P_A15_M1A10_1 |UNUSED | |1 | | | | | | | | |
|E17 | | |VCCO_1 | | |1 | | | | |2.50 | | | |
|E18 | |IOBS |IO_L33N_A14_M1A4_1 |UNUSED | |1 | | | | | | | | |
|F1 | |IOBS |IO_L48N_M3BA1_3 |UNUSED | |3 | | | | | | | | |
|F2 | |IOBM |IO_L48P_M3BA0_3 |UNUSED | |3 | | | | | | | | |
|F3 | |IOBS |IO_L51N_M3A4_3 |UNUSED | |3 | | | | | | | | |
|F4 | |IOBM |IO_L51P_M3A10_3 |UNUSED | |3 | | | | | | | | |
|F5 |BUT<3> |IOB |IO_L55N_M3A14_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
|F6 |BUT<1> |IOB |IO_L55P_M3A13_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
|F7 | |IOBM |IO_L7P_0 |UNUSED | |0 | | | | | | | | |
|F8 | |IOBS |IO_L32N_0 |UNUSED | |0 | | | | | | | | |
|F9 | |IOBS |IO_L38N_VREF_0 |UNUSED | |0 | | | | | | | | |
|F10 | |IOBS |IO_L40N_0 |UNUSED | |0 | | | | | | | | |
|F11 | |IOBM |IO_L42P_0 |UNUSED | |0 | | | | | | | | |
|F12 |DIPSW<2> |IOB |IO_L51P_0 |INPUT |LVCMOS25* |0 | | | |NONE | |LOCATED |NO |NONE |
|F13 |GPIO<6> |IOB |IO_L63P_SCP7_0 |INPUT |LVCMOS25* |0 | | | |NONE | |LOCATED |NO |NONE |
|F14 | |IOBM |IO_L30P_A21_M1RESET_1 |UNUSED | |1 | | | | | | | | |
|F15 |GPIO<4> |IOB |IO_L1P_A25_1 |INPUT |LVCMOS25* |1 | | | |NONE | |LOCATED |NO |NONE |
|F16 | |IOBS |IO_L1N_A24_VREF_1 |UNUSED | |1 | | | | | | | | |
|F17 | |IOBM |IO_L35P_A11_M1A7_1 |UNUSED | |1 | | | | | | | | |
|F18 | |IOBS |IO_L35N_A10_M1A2_1 |UNUSED | |1 | | | | | | | | |
|G1 | |IOBS |IO_L46N_M3CLKN_3 |UNUSED | |3 | | | | | | | | |
|G2 | | |GND | | | | | | | | | | | |
|G3 | |IOBM |IO_L46P_M3CLK_3 |UNUSED | |3 | | | | | | | | |
|G4 | | |VCCO_3 | | |3 | | | | |any******| | | |
|G5 | | |GND | | | | | | | | | | | |
|G6 | |IOBS |IO_L53N_M3A12_3 |UNUSED | |3 | | | | | | | | |
|G7 | | |VCCINT | | | | | | | |1.2 | | | |
|G8 | |IOBM |IO_L32P_0 |UNUSED | |0 | | | | | | | | |
|G9 | |IOBM |IO_L38P_0 |UNUSED | |0 | | | | | | | | |
|G10 | | |VCCAUX | | | | | | | |2.5 | | | |
|G11 | |IOBM |IO_L40P_0 |UNUSED | |0 | | | | | | | | |
|G12 | | |GND | | | | | | | | | | | |
|G13 | |IOBS |IO_L32N_A16_M1A9_1 |UNUSED | |1 | | | | | | | | |
|G14 | |IOBS |IO_L30N_A20_M1A11_1 |UNUSED | |1 | | | | | | | | |
|G15 | | |VCCO_1 | | |1 | | | | |2.50 | | | |
|G16 | |IOBM |IO_L38P_A5_M1CLK_1 |UNUSED | |1 | | | | | | | | |
|G17 | | |GND | | | | | | | | | | | |
|G18 | |IOBS |IO_L38N_A4_M1CLKN_1 |UNUSED | |1 | | | | | | | | |
|H1 | |IOBS |IO_L41N_GCLK26_M3DQ5_3 |UNUSED | |3 | | | | | | | | |
|H2 | |IOBM |IO_L41P_GCLK27_M3DQ4_3 |UNUSED | |3 | | | | | | | | |
|H3 | |IOBS |IO_L44N_GCLK20_M3A6_3 |UNUSED | |3 | | | | | | | | |
|H4 | |IOBM |IO_L44P_GCLK21_M3A5_3 |UNUSED | |3 | | | | | | | | |
|H5 | |IOBS |IO_L49N_M3A2_3 |UNUSED | |3 | | | | | | | | |
|H6 | |IOBM |IO_L49P_M3A7_3 |UNUSED | |3 | | | | | | | | |
|H7 | |IOBM |IO_L53P_M3CKE_3 |UNUSED | |3 | | | | | | | | |
|H8 | | |GND | | | | | | | | | | | |
|H9 | | |VCCINT | | | | | | | |1.2 | | | |
|H10 | | |GND | | | | | | | | | | | |
|H11 | | |VCCINT | | | | | | | |1.2 | | | |
|H12 | |IOBM |IO_L32P_A17_M1A8_1 |UNUSED | |1 | | | | | | | | |
|H13 | |IOBM |IO_L36P_A9_M1BA0_1 |UNUSED | |1 | | | | | | | | |
|H14 | |IOBS |IO_L36N_A8_M1BA1_1 |UNUSED | |1 | | | | | | | | |
|H15 | |IOBM |IO_L37P_A7_M1A0_1 |UNUSED | |1 | | | | | | | | |
|H16 | |IOBS |IO_L37N_A6_M1A1_1 |UNUSED | |1 | | | | | | | | |
|H17 | |IOBM |IO_L43P_GCLK5_M1DQ4_1 |UNUSED | |1 | | | | | | | | |
|H18 | |IOBS |IO_L43N_GCLK4_M1DQ5_1 |UNUSED | |1 | | | | | | | | |
|J1 | |IOBS |IO_L40N_M3DQ7_3 |UNUSED | |3 | | | | | | | | |
|J2 | | |VCCO_3 | | |3 | | | | |any******| | | |
|J3 | |IOBM |IO_L40P_M3DQ6_3 |UNUSED | |3 | | | | | | | | |
|J4 | | |GND | | | | | | | | | | | |
|J5 | | |VCCO_3 | | |3 | | | | |any******| | | |
|J6 | |IOBS |IO_L47N_M3A1_3 |UNUSED | |3 | | | | | | | | |
|J7 | |IOBM |IO_L47P_M3A0_3 |UNUSED | |3 | | | | | | | | |
|J8 | | |VCCINT | | | | | | | |1.2 | | | |
|J9 | | |GND | | | | | | | | | | | |
|J10 | | |VCCINT | | | | | | | |1.2 | | | |
|J11 | | |GND | | | | | | | | | | | |
|J12 | | |VCCAUX | | | | | | | |2.5 | | | |
|J13 | |IOBM |IO_L39P_M1A3_1 |UNUSED | |1 | | | | | | | | |
|J14 | | |VCCO_1 | | |1 | | | | |2.50 | | | |
|J15 | | |GND | | | | | | | | | | | |
|J16 | |IOBM |IO_L44P_A3_M1DQ6_1 |UNUSED | |1 | | | | | | | | |
|J17 | | |VCCO_1 | | |1 | | | | |2.50 | | | |
|J18 | |IOBS |IO_L44N_A2_M1DQ7_1 |UNUSED | |1 | | | | | | | | |
|K1 | |IOBS |IO_L38N_M3DQ3_3 |UNUSED | |3 | | | | | | | | |
|K2 | |IOBM |IO_L38P_M3DQ2_3 |UNUSED | |3 | | | | | | | | |
|K3 | |IOBS |IO_L42N_GCLK24_M3LDM_3 |UNUSED | |3 | | | | | | | | |
|K4 | |IOBM |IO_L42P_GCLK25_TRDY2_M3UDM_3 |UNUSED | |3 | | | | | | | | |
|K5 | |IOBS |IO_L43N_GCLK22_IRDY2_M3CASN_3|UNUSED | |3 | | | | | | | | |
|K6 | |IOBS |IO_L45N_M3ODT_3 |UNUSED | |3 | | | | | | | | |
|K7 | | |VCCAUX | | | | | | | |2.5 | | | |
|K8 | | |GND | | | | | | | | | | | |
|K9 | | |VCCINT | | | | | | | |1.2 | | | |
|K10 | | |GND | | | | | | | | | | | |
|K11 | | |VCCINT | | | | | | | |1.2 | | | |
|K12 | |IOBM |IO_L34P_A13_M1WE_1 |UNUSED | |1 | | | | | | | | |
|K13 | |IOBS |IO_L34N_A12_M1BA2_1 |UNUSED | |1 | | | | | | | | |
|K14 | |IOBS |IO_L39N_M1ODT_1 |UNUSED | |1 | | | | | | | | |
|K15 | |IOBM |IO_L41P_GCLK9_IRDY1_M1RASN_1 |UNUSED | |1 | | | | | | | | |
|K16 | |IOBS |IO_L41N_GCLK8_M1CASN_1 |UNUSED | |1 | | | | | | | | |
|K17 | |IOBM |IO_L45P_A1_M1LDQS_1 |UNUSED | |1 | | | | | | | | |
|K18 | |IOBS |IO_L45N_A0_M1LDQSN_1 |UNUSED | |1 | | | | | | | | |
|L1 | |IOBS |IO_L37N_M3DQ1_3 |UNUSED | |3 | | | | | | | | |
|L2 | |IOBM |IO_L37P_M3DQ0_3 |UNUSED | |3 | | | | | | | | |
|L3 | |IOBS |IO_L39N_M3LDQSN_3 |UNUSED | |3 | | | | | | | | |
|L4 | |IOBM |IO_L39P_M3LDQS_3 |UNUSED | |3 | | | | | | | | |
|L5 | |IOBM |IO_L43P_GCLK23_M3RASN_3 |UNUSED | |3 | | | | | | | | |
|L6 | |IOBM |IO_L31P_3 |UNUSED | |3 | | | | | | | | |
|L7 | |IOBM |IO_L45P_M3A3_3 |UNUSED | |3 | | | | | | | | |
|L8 | | |VCCINT | | | | | | | |1.2 | | | |
|L9 | | |GND | | | | | | | | | | | |
|L10 | | |VCCINT | | | | | | | |1.2 | | | |
|L11 | | |GND | | | | | | | | | | | |
|L12 | |IOBM |IO_L40P_GCLK11_M1A5_1 |UNUSED | |1 | | | | | | | | |
|L13 | |IOBS |IO_L40N_GCLK10_M1A6_1 |UNUSED | |1 | | | | | | | | |
|L14 | |IOBM |IO_L61P_1 |UNUSED | |1 | | | | | | | | |
|L15 |GPIO<3> |IOB |IO_L42P_GCLK7_M1UDM_1 |INPUT |LVCMOS25* |1 | | | |NONE | |LOCATED |NO |NONE |
|L16 | |IOBS |IO_L42N_GCLK6_TRDY1_M1LDM_1 |UNUSED | |1 | | | | | | | | |
|L17 | |IOBM |IO_L46P_FCS_B_M1DQ2_1 |UNUSED | |1 | | | | | | | | |
|L18 | |IOBS |IO_L46N_FOE_B_M1DQ3_1 |UNUSED | |1 | | | | | | | | |
|M1 | |IOBS |IO_L36N_M3DQ9_3 |UNUSED | |3 | | | | | | | | |
|M2 | | |GND | | | | | | | | | | | |
|M3 | |IOBM |IO_L36P_M3DQ8_3 |UNUSED | |3 | | | | | | | | |
|M4 | | |VCCO_3 | | |3 | | | | |any******| | | |
|M5 | |IOBS |IO_L31N_VREF_3 |UNUSED | |3 | | | | | | | | |
|M6 | | |GND | | | | | | | | | | | |
|M7 | | |VCCINT | | | | | | | |1.2 | | | |
|M8 | |IOBM |IO_L40P_2 |UNUSED | |2 | | | | | | | | |
|M9 | | |VCCAUX | | | | | | | |2.5 | | | |
|M10 | |IOBM |IO_L22P_2 |UNUSED | |2 | | | | | | | | |
|M11 | |IOBM |IO_L15P_2 |UNUSED | |2 | | | | | | | | |
|M12 | | |VCCINT | | | | | | | |1.2 | | | |
|M13 | |IOBS |IO_L61N_1 |UNUSED | |1 | | | | | | | | |
|M14 | |IOBM |IO_L53P_1 |UNUSED | |1 | | | | | | | | |
|M15 | | |VCCO_1 | | |1 | | | | |2.50 | | | |
|M16 | |IOBM |IO_L47P_FWE_B_M1DQ0_1 |UNUSED | |1 | | | | | | | | |
|M17 | | |GND | | | | | | | | | | | |
|M18 |GPIO<1> |IOB |IO_L47N_LDC_M1DQ1_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW | | | |LOCATED |NO |NONE |
|N1 | |IOBS |IO_L35N_M3DQ11_3 |UNUSED | |3 | | | | | | | | |
|N2 | |IOBM |IO_L35P_M3DQ10_3 |UNUSED | |3 | | | | | | | | |
|N3 | |IOBS |IO_L1N_VREF_3 |UNUSED | |3 | | | | | | | | |
|N4 | |IOBM |IO_L1P_3 |UNUSED | |3 | | | | | | | | |
|N5 | |IOBM |IO_L64P_D8_2 |UNUSED | |2 | | | | | | | | |
|N6 | |IOBM |IO_L47P_2 |UNUSED | |2 | | | | | | | | |
|N7 | |IOBM |IO_L44P_2 |UNUSED | |2 | | | | | | | | |
|N8 | |IOBS |IO_L40N_2 |UNUSED | |2 | | | | | | | | |
|N9 | |IOBS |IO_L22N_2 |UNUSED | |2 | | | | | | | | |
|N10 | |IOBM |IO_L20P_2 |UNUSED | |2 | | | | | | | | |
|N11 | |IOBS |IO_L15N_2 |UNUSED | |2 | | | | | | | | |
|N12 | |IOBM |IO_L13P_M1_2 |UNUSED | |2 | | | | | | | | |
|N13 | | |GND | | | | | | | | | | | |
|N14 | |IOBS |IO_L53N_VREF_1 |UNUSED | |1 | | | | | | | | |
|N15 | |IOBM |IO_L50P_M1UDQS_1 |UNUSED | |1 | | | | | | | | |
|N16 | |IOBS |IO_L50N_M1UDQSN_1 |UNUSED | |1 | | | | | | | | |
|N17 |GPIO<0> |IOB |IO_L48P_HDC_M1DQ8_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW | | | |LOCATED |NO |NONE |
|N18 | |IOBS |IO_L48N_M1DQ9_1 |UNUSED | |1 | | | | | | | | |
|P1 | |IOBS |IO_L34N_M3UDQSN_3 |UNUSED | |3 | | | | | | | | |
|P2 | |IOBM |IO_L34P_M3UDQS_3 |UNUSED | |3 | | | | | | | | |
|P3 | |IOBS |IO_L2N_3 |UNUSED | |3 | | | | | | | | |
|P4 |BUT<0> |IOB |IO_L2P_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
|P5 | | |VCCAUX | | | | | | | |2.5 | | | |
|P6 | |IOBS |IO_L64N_D9_2 |UNUSED | |2 | | | | | | | | |
|P7 | |IOBS |IO_L47N_2 |UNUSED | |2 | | | | | | | | |
|P8 | |IOBS |IO_L44N_2 |UNUSED | |2 | | | | | | | | |
|P9 | | |VCCO_2 | | |2 | | | | |any******| | | |
|P10 | | |VCCAUX | | | | | | | |2.5 | | | |
|P11 | |IOBS |IO_L20N_2 |UNUSED | |2 | | | | | | | | |
|P12 |GPIO<7> |IOB |IO_L13N_D10_2 |INPUT |LVCMOS25* |2 | | | |NONE | |LOCATED |NO |NONE |
|P13 | | |CMPCS_B_2 | | | | | | | | | | | |
|P14 | | |VCCAUX | | | | | | | |2.5 | | | |
|P15 | |IOBM |IO_L74P_AWAKE_1 |UNUSED | |1 | | | | | | | | |
|P16 | |IOBS |IO_L74N_DOUT_BUSY_1 |UNUSED | |1 | | | | | | | | |
|P17 | |IOBM |IO_L49P_M1DQ10_1 |UNUSED | |1 | | | | | | | | |
|P18 | |IOBS |IO_L49N_M1DQ11_1 |UNUSED | |1 | | | | | | | | |
|R1 | | |GND | | | | | | | | | | | |
|R2 | | |VCCO_3 | | |3 | | | | |any******| | | |
|R3 | |IOBM |IO_L62P_D5_2 |UNUSED | |2 | | | | | | | | |
|R4 | | |GND | | | | | | | | | | | |
|R5 | |IOBM |IO_L48P_D7_2 |UNUSED | |2 | | | | | | | | |
|R6 | | |VCCO_2 | | |2 | | | | |any******| | | |
|R7 | |IOBM |IO_L46P_2 |UNUSED | |2 | | | | | | | | |
|R8 | |IOBM |IO_L31P_GCLK31_D14_2 |UNUSED | |2 | | | | | | | | |
|R9 | | |GND | | | | | | | | | | | |
|R10 | |IOBM |IO_L29P_GCLK3_2 |UNUSED | |2 | | | | | | | | |
|R11 | |IOBM |IO_L16P_2 |UNUSED | |2 | | | | | | | | |
|R12 | | |VCCO_2 | | |2 | | | | |any******| | | |
|R13 | |IOBM |IO_L3P_D0_DIN_MISO_MISO1_2 |UNUSED | |2 | | | | | | | | |
|R14 | | |GND | | | | | | | | | | | |
|R15 | |IOBM |IO_L1P_CCLK_2 |UNUSED | |2 | | | | | | | | |
|R16 | | |SUSPEND | | | | | | | | | | | |
|R17 | | |VCCO_1 | | |1 | | | | |2.50 | | | |
|R18 | | |GND | | | | | | | | | | | |
|T1 | |IOBS |IO_L33N_M3DQ13_3 |UNUSED | |3 | | | | | | | | |
|T2 | |IOBM |IO_L33P_M3DQ12_3 |UNUSED | |3 | | | | | | | | |
|T3 | |IOBS |IO_L62N_D6_2 |UNUSED | |2 | | | | | | | | |
|T4 | |IOBM |IO_L63P_2 |UNUSED | |2 | | | | | | | | |
|T5 | |IOBS |IO_L48N_RDWR_B_VREF_2 |UNUSED | |2 | | | | | | | | |
|T6 | |IOBM |IO_L45P_2 |UNUSED | |2 | | | | | | | | |
|T7 | |IOBS |IO_L46N_2 |UNUSED | |2 | | | | | | | | |
|T8 | |IOBS |IO_L31N_GCLK30_D15_2 |UNUSED | |2 | | | | | | | | |
|T9 | |IOBM |IO_L32P_GCLK29_2 |UNUSED | |2 | | | | | | | | |
|T10 | |IOBS |IO_L29N_GCLK2_2 |UNUSED | |2 | | | | | | | | |
|T11 | |IOBS |IO_L16N_VREF_2 |UNUSED | |2 | | | | | | | | |
|T12 | |IOBM |IO_L19P_2 |UNUSED | |2 | | | | | | | | |
|T13 | |IOBS |IO_L3N_MOSI_CSI_B_MISO0_2 |UNUSED | |2 | | | | | | | | |
|T14 | |IOBM |IO_L12P_D1_MISO2_2 |UNUSED | |2 | | | | | | | | |
|T15 | |IOBS |IO_L1N_M0_CMPMISO_2 |UNUSED | |2 | | | | | | | | |
|T16 | | |GND | | | | | | | | | | | |
|T17 | |IOBM |IO_L51P_M1DQ12_1 |UNUSED | |1 | | | | | | | | |
|T18 | |IOBS |IO_L51N_M1DQ13_1 |UNUSED | |1 | | | | | | | | |
|U1 | |IOBS |IO_L32N_M3DQ15_3 |UNUSED | |3 | | | | | | | | |
|U2 | |IOBM |IO_L32P_M3DQ14_3 |UNUSED | |3 | | | | | | | | |
|U3 | |IOBM |IO_L65P_INIT_B_2 |UNUSED | |2 | | | | | | | | |
|U4 | | |VCCO_2 | | |2 | | | | |any******| | | |
|U5 | |IOBM |IO_L49P_D3_2 |UNUSED | |2 | | | | | | | | |
|U6 | | |GND | | | | | | | | | | | |
|U7 | |IOBM |IO_L43P_2 |UNUSED | |2 | | | | | | | | |
|U8 | |IOBM |IO_L41P_2 |UNUSED | |2 | | | | | | | | |
|U9 | | |VCCO_2 | | |2 | | | | |any******| | | |
|U10 | |IOBM |IO_L30P_GCLK1_D13_2 |UNUSED | |2 | | | | | | | | |
|U11 | |IOBM |IO_L23P_2 |UNUSED | |2 | | | | | | | | |
|U12 | | |GND | | | | | | | | | | | |
|U13 | |IOBM |IO_L14P_D11_2 |UNUSED | |2 | | | | | | | | |
|U14 | | |VCCO_2 | | |2 | | | | |any******| | | |
|U15 | |IOBM |IO_L5P_2 |UNUSED | |2 | | | | | | | | |
|U16 | |IOBM |IO_L2P_CMPCLK_2 |UNUSED | |2 | | | | | | | | |
|U17 | |IOBM |IO_L52P_M1DQ14_1 |UNUSED | |1 | | | | | | | | |
|U18 | |IOBS |IO_L52N_M1DQ15_1 |UNUSED | |1 | | | | | | | | |
|V1 | | |GND | | | | | | | | | | | |
|V2 | | |PROGRAM_B_2 | | | | | | | | | | | |
|V3 | |IOBS |IO_L65N_CSO_B_2 |UNUSED | |2 | | | | | | | | |
|V4 | |IOBS |IO_L63N_2 |UNUSED | |2 | | | | | | | | |
|V5 | |IOBS |IO_L49N_D4_2 |UNUSED | |2 | | | | | | | | |
|V6 | |IOBS |IO_L45N_2 |UNUSED | |2 | | | | | | | | |
|V7 | |IOBS |IO_L43N_2 |UNUSED | |2 | | | | | | | | |
|V8 | |IOBS |IO_L41N_VREF_2 |UNUSED | |2 | | | | | | | | |
|V9 | |IOBS |IO_L32N_GCLK28_2 |UNUSED | |2 | | | | | | | | |
|V10 |CLK27MHz |IOB |IO_L30N_GCLK0_USERCCLK_2 |INPUT |LVCMOS25* |2 | | | |NONE | |LOCATED |NO |NONE |
|V11 | |IOBS |IO_L23N_2 |UNUSED | |2 | | | | | | | | |
|V12 | |IOBS |IO_L19N_2 |UNUSED | |2 | | | | | | | | |
|V13 |DIPSW<3> |IOB |IO_L14N_D12_2 |INPUT |LVCMOS25* |2 | | | |NONE | |LOCATED |NO |NONE |
|V14 | |IOBS |IO_L12N_D2_MISO3_2 |UNUSED | |2 | | | | | | | | |
|V15 | |IOBS |IO_L5N_2 |UNUSED | |2 | | | | | | | | |
|V16 | |IOBS |IO_L2N_CMPMOSI_2 |UNUSED | |2 | | | | | | | | |
|V17 | | |DONE_2 | | | | | | | | | | | |
|V18 | | |GND | | | | | | | | | | | |
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
* Default value.
** This default Pullup/Pulldown value can be overridden in Bitgen.
****** Special VCCO requirements may apply. Please consult the device
family datasheet for specific guideline on VCCO requirements.

2400
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<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>textovhdl Project Status (06/08/2022 - 11:36:16)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>Aula20220608.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD> No Errors </TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>textovhdl</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>Programming File Generated</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc6slx16-2csg324</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>
No Errors</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/*.xmsgs?&DataKey=Warning'>56 Warnings (56 new)</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
<A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl.unroutes'>All Signals Completely Routed</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>
<A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>
<A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl_envsettings.html'>
System Settings</A>
</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>0 &nbsp;<A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
<TD ALIGN=RIGHT>32</TD>
<TD ALIGN=RIGHT>18,224</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Flip Flops</TD>
<TD ALIGN=RIGHT>32</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latches</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latch-thrus</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as AND/OR logics</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
<TD ALIGN=RIGHT>31</TD>
<TD ALIGN=RIGHT>9,112</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
<TD ALIGN=RIGHT>29</TD>
<TD ALIGN=RIGHT>9,112</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
<TD ALIGN=RIGHT>14</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
<TD ALIGN=RIGHT>11</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
<TD ALIGN=RIGHT>4</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as ROM</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Memory</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>2,176</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used exclusively as route-thrus</TD>
<TD ALIGN=RIGHT>2</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice register load</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice carry load</TD>
<TD ALIGN=RIGHT>2</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with other load</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
<TD ALIGN=RIGHT>11</TD>
<TD ALIGN=RIGHT>2,278</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MUXCYs used</TD>
<TD ALIGN=RIGHT>20</TD>
<TD ALIGN=RIGHT>4,556</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
<TD ALIGN=RIGHT>31</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused Flip Flop</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>31</TD>
<TD ALIGN=RIGHT>3%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused LUT</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>31</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of fully used LUT-FF pairs</TD>
<TD ALIGN=RIGHT>30</TD>
<TD ALIGN=RIGHT>31</TD>
<TD ALIGN=RIGHT>96%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of unique control sets</TD>
<TD ALIGN=RIGHT>2</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of slice register sites lost<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;to control set restrictions</TD>
<TD ALIGN=RIGHT>8</TD>
<TD ALIGN=RIGHT>18,224</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
<TD ALIGN=RIGHT>17</TD>
<TD ALIGN=RIGHT>232</TD>
<TD ALIGN=RIGHT>7%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of LOCed IOBs</TD>
<TD ALIGN=RIGHT>17</TD>
<TD ALIGN=RIGHT>17</TD>
<TD ALIGN=RIGHT>100%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>32</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>64</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>32</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>32</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>16</TD>
<TD ALIGN=RIGHT>12%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGs</TD>
<TD ALIGN=RIGHT>2</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGMUX</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>248</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>248</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>248</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>128</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>8</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>32</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MCBs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
<TD ALIGN=RIGHT>1.88</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
<TD>0 (Setup: 0, Hold: 0)</TD>
<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
<TD COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
<A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl.unroutes'>All Signals Completely Routed</A></TD>
<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
<TD COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
<TD>
<A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
<TD BGCOLOR='#FFFF99'><B>&nbsp;</B></TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Jun 8 11:34:43 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/xst.xmsgs?&DataKey=Warning'>32 Warnings (32 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/xst.xmsgs?&DataKey=Info'>1 Info (1 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl.bld'>Translation Report</A></TD><TD>Current</TD><TD>Wed Jun 8 11:35:33 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>5 Warnings (5 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Wed Jun 8 11:35:43 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/map.xmsgs?&DataKey=Warning'>4 Warnings (4 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/map.xmsgs?&DataKey=Info'>8 Infos (8 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Wed Jun 8 11:35:52 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/par.xmsgs?&DataKey=Warning'>15 Warnings (15 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/par.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Wed Jun 8 11:35:59 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\_xmsgs/trce.xmsgs?&DataKey=Info'>4 Infos (4 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\textovhdl.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Wed Jun 8 11:36:14 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Jun 8 11:36:14 2022</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220608\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Jun 8 11:36:16 2022</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 06/08/2022 - 11:36:16</center>
</BODY></HTML>

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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DesignSummary rev="2">
<CmdHistory>
</CmdHistory>
</DesignSummary>

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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DeviceUsageSummary rev="2">
<DesignStatistics TimeStamp="Wed Jun 08 11:36:13 2022"><group name="NetStatistics">
<item name="NumNets_Active" rev="2">
<attrib name="value" value="69"/></item>
<item name="NumNets_Vcc" rev="2">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Active_BOUNCEACROSS" rev="2">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Active_BOUNCEIN" rev="2">
<attrib name="value" value="6"/></item>
<item name="NumNodesOfType_Active_BUFGOUT" rev="2">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Active_BUFHINP2OUT" rev="2">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Active_CLKPIN" rev="2">
<attrib name="value" value="10"/></item>
<item name="NumNodesOfType_Active_CLKPINFEED" rev="2">
<attrib name="value" value="6"/></item>
<item name="NumNodesOfType_Active_DOUBLE" rev="2">
<attrib name="value" value="8"/></item>
<item name="NumNodesOfType_Active_GENERIC" rev="2">
<attrib name="value" value="4"/></item>
<item name="NumNodesOfType_Active_GLOBAL" rev="2">
<attrib name="value" value="14"/></item>
<item name="NumNodesOfType_Active_INPUT" rev="2">
<attrib name="value" value="5"/></item>
<item name="NumNodesOfType_Active_IOBIN2OUT" rev="2">
<attrib name="value" value="3"/></item>
<item name="NumNodesOfType_Active_IOBOUTPUT" rev="2">
<attrib name="value" value="3"/></item>
<item name="NumNodesOfType_Active_LUTINPUT" rev="2">
<attrib name="value" value="86"/></item>
<item name="NumNodesOfType_Active_OUTBOUND" rev="2">
<attrib name="value" value="33"/></item>
<item name="NumNodesOfType_Active_OUTPUT" rev="2">
<attrib name="value" value="39"/></item>
<item name="NumNodesOfType_Active_PADINPUT" rev="2">
<attrib name="value" value="3"/></item>
<item name="NumNodesOfType_Active_PADOUTPUT" rev="2">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Active_PINBOUNCE" rev="2">
<attrib name="value" value="19"/></item>
<item name="NumNodesOfType_Active_PINFEED" rev="2">
<attrib name="value" value="102"/></item>
<item name="NumNodesOfType_Active_QUAD" rev="2">
<attrib name="value" value="22"/></item>
<item name="NumNodesOfType_Active_SINGLE" rev="2">
<attrib name="value" value="20"/></item>
<item name="NumNodesOfType_Vcc_HVCCOUT" rev="2">
<attrib name="value" value="5"/></item>
<item name="NumNodesOfType_Vcc_LUTINPUT" rev="2">
<attrib name="value" value="15"/></item>
<item name="NumNodesOfType_Vcc_PINFEED" rev="2">
<attrib name="value" value="15"/></item>
</group>
<group name="SiteStatistics">
<item name="BUFG-BUFGMUX" rev="2">
<attrib name="value" value="2"/></item>
<item name="IOB-IOBM" rev="2">
<attrib name="value" value="10"/></item>
<item name="IOB-IOBS" rev="2">
<attrib name="value" value="7"/></item>
<item name="SLICEL-SLICEM" rev="2">
<attrib name="value" value="2"/></item>
<item name="SLICEX-SLICEL" rev="2">
<attrib name="value" value="1"/></item>
<item name="SLICEX-SLICEM" rev="2">
<attrib name="value" value="2"/></item>
</group>
<group name="MiscellaneousStatistics">
<item name="AGG_BONDED_IO" rev="1">
<attrib name="value" value="17"/></item>
<item name="AGG_IO" rev="1">
<attrib name="value" value="17"/></item>
<item name="AGG_LOCED_IO" rev="1">
<attrib name="value" value="17"/></item>
<item name="AGG_SLICE" rev="1">
<attrib name="value" value="11"/></item>
<item name="NUM_BONDED_IOB" rev="1">
<attrib name="value" value="17"/></item>
<item name="NUM_BSFULL" rev="1">
<attrib name="value" value="30"/></item>
<item name="NUM_BSLUTONLY" rev="1">
<attrib name="value" value="1"/></item>
<item name="NUM_BSUSED" rev="1">
<attrib name="value" value="31"/></item>
<item name="NUM_BUFG" rev="1">
<attrib name="value" value="2"/></item>
<item name="NUM_LOCED_IOB" rev="1">
<attrib name="value" value="17"/></item>
<item name="NUM_LOGIC_O5ANDO6" rev="1">
<attrib name="value" value="4"/></item>
<item name="NUM_LOGIC_O5ONLY" rev="1">
<attrib name="value" value="11"/></item>
<item name="NUM_LOGIC_O6ONLY" rev="1">
<attrib name="value" value="14"/></item>
<item name="NUM_LUT_RT_DRIVES_CARRY4" rev="1">
<attrib name="value" value="2"/></item>
<item name="NUM_LUT_RT_EXO6" rev="1">
<attrib name="value" value="2"/></item>
<item name="NUM_LUT_RT_O6" rev="1">
<attrib name="value" value="11"/></item>
<item name="NUM_SLICEL" rev="1">
<attrib name="value" value="5"/></item>
<item name="NUM_SLICEX" rev="1">
<attrib name="value" value="6"/></item>
<item name="NUM_SLICE_CARRY4" rev="1">
<attrib name="value" value="5"/></item>
<item name="NUM_SLICE_CONTROLSET" rev="1">
<attrib name="value" value="2"/></item>
<item name="NUM_SLICE_CYINIT" rev="1">
<attrib name="value" value="48"/></item>
<item name="NUM_SLICE_FF" rev="1">
<attrib name="value" value="32"/></item>
<item name="NUM_SLICE_UNUSEDCTRL" rev="1">
<attrib name="value" value="1"/></item>
<item name="NUM_UNUSABLE_FF_BELS" rev="1">
<attrib name="value" value="8"/></item>
</group>
</DesignStatistics>
<DeviceUsage TimeStamp="Wed Jun 08 11:36:13 2022"><group name="SiteSummary">
<item name="BUFG" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="BUFG_BUFG" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="CARRY4" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="5"/></item>
<item name="FF_SR" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="HARD0" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="IOB" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="17"/></item>
<item name="IOB_IMUX" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="14"/></item>
<item name="IOB_INBUF" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="14"/></item>
<item name="IOB_OUTBUF" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="3"/></item>
<item name="LUT5" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="15"/></item>
<item name="LUT6" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="31"/></item>
<item name="PAD" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="17"/></item>
<item name="REG_SR" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="30"/></item>
<item name="SLICEL" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="5"/></item>
<item name="SLICEX" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="6"/></item>
</group>
</DeviceUsage>
<ReportConfigData TimeStamp="Wed Jun 08 11:36:13 2022"><group name="REG_SR">
<item name="CK" rev="2">
<attrib name="CK" value="6"/><attrib name="CK_INV" value="24"/></item>
<item name="LATCH_OR_FF" rev="2">
<attrib name="FF" value="30"/></item>
<item name="SRINIT" rev="2">
<attrib name="SRINIT0" value="30"/></item>
<item name="SYNC_ATTR" rev="2">
<attrib name="ASYNC" value="30"/></item>
</group>
<group name="SLICEL">
<item name="CLK" rev="2">
<attrib name="CLK" value="2"/><attrib name="CLK_INV" value="3"/></item>
</group>
<group name="IOB_OUTBUF">
<item name="DRIVEATTRBOX" rev="2">
<attrib name="12" value="3"/></item>
<item name="SLEW" rev="2">
<attrib name="SLOW" value="3"/></item>
<item name="SUSPEND" rev="2">
<attrib name="3STATE" value="3"/></item>
</group>
<group name="SLICEX">
<item name="CLK" rev="2">
<attrib name="CLK" value="0"/><attrib name="CLK_INV" value="5"/></item>
</group>
<group name="FF_SR">
<item name="CK" rev="2">
<attrib name="CK" value="0"/><attrib name="CK_INV" value="2"/></item>
<item name="SRINIT" rev="2">
<attrib name="SRINIT0" value="2"/></item>
<item name="SYNC_ATTR" rev="2">
<attrib name="ASYNC" value="2"/></item>
</group>
</ReportConfigData>
<ReportPinData TimeStamp="Wed Jun 08 11:36:13 2022"><group name="REG_SR">
<item name="CK" rev="2">
<attrib name="value" value="30"/></item>
<item name="D" rev="2">
<attrib name="value" value="30"/></item>
<item name="Q" rev="2">
<attrib name="value" value="30"/></item>
</group>
<group name="SLICEL">
<item name="A4" rev="2">
<attrib name="value" value="5"/></item>
<item name="A6" rev="2">
<attrib name="value" value="4"/></item>
<item name="AQ" rev="2">
<attrib name="value" value="5"/></item>
<item name="B4" rev="2">
<attrib name="value" value="4"/></item>
<item name="B6" rev="2">
<attrib name="value" value="3"/></item>
<item name="BQ" rev="2">
<attrib name="value" value="4"/></item>
<item name="C4" rev="2">
<attrib name="value" value="3"/></item>
<item name="C6" rev="2">
<attrib name="value" value="3"/></item>
<item name="CIN" rev="2">
<attrib name="value" value="3"/></item>
<item name="CLK" rev="2">
<attrib name="value" value="5"/></item>
<item name="COUT" rev="2">
<attrib name="value" value="3"/></item>
<item name="CQ" rev="2">
<attrib name="value" value="3"/></item>
<item name="D4" rev="2">
<attrib name="value" value="3"/></item>
<item name="D6" rev="2">
<attrib name="value" value="3"/></item>
<item name="DQ" rev="2">
<attrib name="value" value="3"/></item>
</group>
<group name="IOB_OUTBUF">
<item name="IN" rev="2">
<attrib name="value" value="3"/></item>
<item name="OUT" rev="2">
<attrib name="value" value="3"/></item>
</group>
<group name="SLICEX">
<item name="A" rev="2">
<attrib name="value" value="1"/></item>
<item name="A2" rev="2">
<attrib name="value" value="2"/></item>
<item name="A3" rev="2">
<attrib name="value" value="3"/></item>
<item name="A4" rev="2">
<attrib name="value" value="5"/></item>
<item name="A5" rev="2">
<attrib name="value" value="4"/></item>
<item name="A6" rev="2">
<attrib name="value" value="6"/></item>
<item name="AMUX" rev="2">
<attrib name="value" value="1"/></item>
<item name="AQ" rev="2">
<attrib name="value" value="5"/></item>
<item name="B1" rev="2">
<attrib name="value" value="1"/></item>
<item name="B2" rev="2">
<attrib name="value" value="2"/></item>
<item name="B3" rev="2">
<attrib name="value" value="4"/></item>
<item name="B4" rev="2">
<attrib name="value" value="4"/></item>
<item name="B5" rev="2">
<attrib name="value" value="4"/></item>
<item name="B6" rev="2">
<attrib name="value" value="4"/></item>
<item name="BMUX" rev="2">
<attrib name="value" value="1"/></item>
<item name="BQ" rev="2">
<attrib name="value" value="4"/></item>
<item name="C1" rev="2">
<attrib name="value" value="2"/></item>
<item name="C2" rev="2">
<attrib name="value" value="3"/></item>
<item name="C3" rev="2">
<attrib name="value" value="3"/></item>
<item name="C4" rev="2">
<attrib name="value" value="3"/></item>
<item name="C5" rev="2">
<attrib name="value" value="3"/></item>
<item name="C6" rev="2">
<attrib name="value" value="3"/></item>
<item name="CLK" rev="2">
<attrib name="value" value="5"/></item>
<item name="CQ" rev="2">
<attrib name="value" value="3"/></item>
<item name="D1" rev="2">
<attrib name="value" value="2"/></item>
<item name="D2" rev="2">
<attrib name="value" value="3"/></item>
<item name="D3" rev="2">
<attrib name="value" value="3"/></item>
<item name="D4" rev="2">
<attrib name="value" value="3"/></item>
<item name="D5" rev="2">
<attrib name="value" value="3"/></item>
<item name="D6" rev="2">
<attrib name="value" value="3"/></item>
<item name="DQ" rev="2">
<attrib name="value" value="3"/></item>
</group>
<group name="BUFG_BUFG">
<item name="I0" rev="2">
<attrib name="value" value="2"/></item>
<item name="O" rev="2">
<attrib name="value" value="2"/></item>
</group>
<group name="PAD">
<item name="PAD" rev="2">
<attrib name="value" value="17"/></item>
</group>
<group name="IOB_INBUF">
<item name="OUT" rev="2">
<attrib name="value" value="14"/></item>
<item name="PAD" rev="2">
<attrib name="value" value="14"/></item>
</group>
<group name="CARRY4">
<item name="CIN" rev="2">
<attrib name="value" value="3"/></item>
<item name="CO3" rev="2">
<attrib name="value" value="3"/></item>
<item name="CYINIT" rev="2">
<attrib name="value" value="2"/></item>
<item name="DI0" rev="2">
<attrib name="value" value="4"/></item>
<item name="DI1" rev="2">
<attrib name="value" value="3"/></item>
<item name="DI2" rev="2">
<attrib name="value" value="3"/></item>
<item name="DI3" rev="2">
<attrib name="value" value="3"/></item>
<item name="O0" rev="2">
<attrib name="value" value="5"/></item>
<item name="O1" rev="2">
<attrib name="value" value="4"/></item>
<item name="O2" rev="2">
<attrib name="value" value="3"/></item>
<item name="O3" rev="2">
<attrib name="value" value="3"/></item>
<item name="S0" rev="2">
<attrib name="value" value="5"/></item>
<item name="S1" rev="2">
<attrib name="value" value="4"/></item>
<item name="S2" rev="2">
<attrib name="value" value="3"/></item>
<item name="S3" rev="2">
<attrib name="value" value="3"/></item>
</group>
<group name="LUT5">
<item name="A3" rev="2">
<attrib name="value" value="2"/></item>
<item name="A5" rev="2">
<attrib name="value" value="2"/></item>
<item name="O5" rev="2">
<attrib name="value" value="15"/></item>
</group>
<group name="LUT6">
<item name="A1" rev="2">
<attrib name="value" value="5"/></item>
<item name="A2" rev="2">
<attrib name="value" value="10"/></item>
<item name="A3" rev="2">
<attrib name="value" value="11"/></item>
<item name="A4" rev="2">
<attrib name="value" value="30"/></item>
<item name="A5" rev="2">
<attrib name="value" value="14"/></item>
<item name="A6" rev="2">
<attrib name="value" value="29"/></item>
<item name="O6" rev="2">
<attrib name="value" value="31"/></item>
</group>
<group name="IOB_IMUX">
<item name="I" rev="2">
<attrib name="value" value="14"/></item>
<item name="OUT" rev="2">
<attrib name="value" value="14"/></item>
</group>
<group name="IOB">
<item name="I" rev="2">
<attrib name="value" value="14"/></item>
<item name="O" rev="2">
<attrib name="value" value="3"/></item>
<item name="PAD" rev="2">
<attrib name="value" value="17"/></item>
</group>
<group name="HARD0">
<item name="0" rev="2">
<attrib name="value" value="2"/></item>
</group>
<group name="FF_SR">
<item name="CK" rev="2">
<attrib name="value" value="2"/></item>
<item name="D" rev="2">
<attrib name="value" value="2"/></item>
<item name="Q" rev="2">
<attrib name="value" value="2"/></item>
</group>
<group name="BUFG">
<item name="I0" rev="2">
<attrib name="value" value="2"/></item>
<item name="O" rev="2">
<attrib name="value" value="2"/></item>
</group>
</ReportPinData>
<CmdHistory>
</CmdHistory>
</DeviceUsageSummary>

197
textovhdl_xst.xrpt Normal file
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@@ -0,0 +1,197 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt64" product="ISE" version="14.7">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Wed Jun 08 11:34:37 2022">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\ProgramData\Oracle\Java\javapath;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\Intel\WiFi\bin\;C:\Program Files\Common Files\Intel\WirelessCommon\;C:\Program Files\TortoiseGit\bin;C:\Program Files\Git\cmd;C:\Program Files\Microsoft VS Code\bin;C:\Program Files\MATLAB\R2022a\bin"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\"/>
</row>
<row stringID="row" value="3">
<item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\EDK"/>
</row>
<row stringID="row" value="5">
<item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\PlanAhead"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft Windows 7 , 64-bit"/>
<item stringID="User_EnvOsrelease" value="Service Pack 1 (build 7601)"/>
</item>
<item stringID="User_EnvHost" value="GABRIEL-E5400"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU T9600 @ 2.80GHz"/>
<item stringID="speed" value="2793 MHz"/>
</row>
</table>
</section>
<section stringID="XST_OPTION_SUMMARY">
<item DEFAULT="" label="-ifn" stringID="XST_IFN" value="textovhdl.prj"/>
<item DEFAULT="" label="-ofn" stringID="XST_OFN" value="textovhdl"/>
<item DEFAULT="NGC" label="-ofmt" stringID="XST_OFMT" value="NGC"/>
<item DEFAULT="" label="-p" stringID="XST_P" value="xc6slx16-2-csg324"/>
<item DEFAULT="" label="-top" stringID="XST_TOP" value="textovhdl"/>
<item DEFAULT="Speed" label="-opt_mode" stringID="XST_OPTMODE" value="Speed"/>
<item DEFAULT="1" label="-opt_level" stringID="XST_OPTLEVEL" value="1"/>
<item DEFAULT="No" label="-power" stringID="XST_POWER" value="NO"/>
<item DEFAULT="No" label="-iuc" stringID="XST_IUC" value="NO"/>
<item DEFAULT="No" label="-keep_hierarchy" stringID="XST_KEEPHIERARCHY" value="No"/>
<item DEFAULT="As_Optimized" label="-netlist_hierarchy" stringID="XST_NETLISTHIERARCHY" value="As_Optimized"/>
<item DEFAULT="No" label="-rtlview" stringID="XST_RTLVIEW" value="Yes"/>
<item DEFAULT="AllClockNets" label="-glob_opt" stringID="XST_GLOBOPT" value="AllClockNets"/>
<item DEFAULT="Yes" label="-read_cores" stringID="XST_READCORES" value="YES"/>
<item DEFAULT="No" label="-write_timing_constraints" stringID="XST_WRITETIMINGCONSTRAINTS" value="NO"/>
<item DEFAULT="No" label="-cross_clock_analysis" stringID="XST_CROSSCLOCKANALYSIS" value="NO"/>
<item DEFAULT="/" stringID="XST_HIERARCHYSEPARATOR" value="/"/>
<item DEFAULT="&lt;>" label="-bus_delimiter" stringID="XST_BUSDELIMITER" value="&lt;>"/>
<item DEFAULT="Maintain" stringID="XST_CASE" value="Maintain"/>
<item DEFAULT="100" label="-slice_utilization_ratio" stringID="XST_SLICEUTILIZATIONRATIO" value="100"/>
<item DEFAULT="100" label="-bram_utilization_ratio" stringID="XST_BRAMUTILIZATIONRATIO" value="100"/>
<item DEFAULT="100" label="-dsp_utilization_ratio" stringID="XST_DSPUTILIZATIONRATIO" value="100"/>
<item DEFAULT="Auto" stringID="XST_LC" value="Auto"/>
<item DEFAULT="Auto" label="-reduce_control_sets" stringID="XST_REDUCECONTROLSETS" value="Auto"/>
<item DEFAULT="Yes" label="-fsm_extract" stringID="XST_FSMEXTRACT" value="YES"/>
<item DEFAULT="Auto" label="-fsm_encoding" stringID="XST_FSMENCODING" value="Auto"/>
<item DEFAULT="No" label="-safe_implementation" stringID="XST_SAFEIMPLEMENTATION" value="No"/>
<item DEFAULT="LUT" label="-fsm_style" stringID="XST_FSMSTYLE" value="LUT"/>
<item DEFAULT="Yes" label="-ram_extract" stringID="XST_RAMEXTRACT" value="Yes"/>
<item DEFAULT="Auto" label="-ram_style" stringID="XST_RAMSTYLE" value="Auto"/>
<item DEFAULT="Yes" label="-rom_extract" stringID="XST_ROMEXTRACT" value="Yes"/>
<item DEFAULT="Yes" label="-shreg_extract" stringID="XST_SHREGEXTRACT" value="YES"/>
<item DEFAULT="Auto" label="-rom_style" stringID="XST_ROMSTYLE" value="Auto"/>
<item DEFAULT="No" label="-auto_bram_packing" stringID="XST_AUTOBRAMPACKING" value="NO"/>
<item DEFAULT="Yes" label="-resource_sharing" stringID="XST_RESOURCESHARING" value="YES"/>
<item DEFAULT="No" label="-async_to_sync" stringID="XST_ASYNCTOSYNC" value="NO"/>
<item DEFAULT="2" stringID="XST_SHREGMINSIZE" value="2"/>
<item DEFAULT="Auto" label="-use_dsp48" stringID="XST_USEDSP48" value="Auto"/>
<item DEFAULT="Yes" label="-iobuf" stringID="XST_IOBUF" value="YES"/>
<item DEFAULT="100000" label="-max_fanout" stringID="XST_MAXFANOUT" value="100000"/>
<item DEFAULT="16" label="-bufg" stringID="XST_BUFG" value="16"/>
<item DEFAULT="Yes" label="-register_duplication" stringID="XST_REGISTERDUPLICATION" value="YES"/>
<item DEFAULT="No" label="-register_balancing" stringID="XST_REGISTERBALANCING" value="No"/>
<item DEFAULT="No" label="-optimize_primitives" stringID="XST_OPTIMIZEPRIMITIVES" value="NO"/>
<item DEFAULT="Auto" label="-use_clock_enable" stringID="XST_USECLOCKENABLE" value="Auto"/>
<item DEFAULT="Auto" label="-use_sync_set" stringID="XST_USESYNCSET" value="Auto"/>
<item DEFAULT="Auto" label="-use_sync_reset" stringID="XST_USESYNCRESET" value="Auto"/>
<item DEFAULT="Auto" label="-iob" stringID="XST_IOB" value="Auto"/>
<item DEFAULT="Yes" label="-equivalent_register_removal" stringID="XST_EQUIVALENTREGISTERREMOVAL" value="YES"/>
<item DEFAULT="0" label="-slice_utilization_ratio_maxmargin" stringID="XST_SLICEUTILIZATIONRATIOMAXMARGIN" value="5"/>
</section>
<section stringID="XST_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_RAMS" value="1"></item>
<item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="2"></item>
<item dataType="int" stringID="XST_REGISTERS" value="4">
<item dataType="int" stringID="XST_1BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_16BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_9BIT_REGISTER" value="1"/>
</item>
<item dataType="int" stringID="XST_MULTIPLEXERS" value="4">
<item dataType="int" stringID="XST_16BIT_2TO1_MULTIPLEXER" value="4"/>
</item>
<item dataType="int" stringID="XST_TRISTATES" value="4">
<item dataType="int" stringID="XST_1BIT_TRISTATE_BUFFER" value="4"/>
</item>
</section>
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_RAMS" value="1"></item>
<item dataType="int" stringID="XST_COUNTERS" value="2">
<item dataType="int" stringID="XST_9BIT_UP_COUNTER" value="1"/>
</item>
<item dataType="int" stringID="XST_REGISTERS" value="17">
<item dataType="int" stringID="XST_FLIPFLOPS" value="17"/>
</item>
<item dataType="int" stringID="XST_MULTIPLEXERS" value="4">
<item dataType="int" stringID="XST_16BIT_2TO1_MULTIPLEXER" value="4"/>
</item>
</section>
<section stringID="XST_FINAL_REGISTER_REPORT">
<item dataType="int" stringID="XST_REGISTERS" value="32">
<item dataType="int" stringID="XST_FLIPFLOPS" value="32"/>
</item>
</section>
<section stringID="XST_PARTITION_REPORT">
<section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
</section>
</section>
<section stringID="XST_DESIGN_SUMMARY">
<section stringID="XST_">
<item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="textovhdl.ngc"/>
</section>
<section stringID="XST_PRIMITIVE_AND_BLACK_BOX_USAGE">
<item dataType="int" stringID="XST_BELS" value="64">
<item dataType="int" stringID="XST_GND" value="1"/>
<item dataType="int" stringID="XST_INV" value="4"/>
<item dataType="int" stringID="XST_LUT1" value="13"/>
<item dataType="int" stringID="XST_LUT2" value="5"/>
<item dataType="int" stringID="XST_LUT3" value="1"/>
<item dataType="int" stringID="XST_LUT4" value="1"/>
<item dataType="int" stringID="XST_LUT5" value="5"/>
<item dataType="int" stringID="XST_LUT6" value="5"/>
<item dataType="int" stringID="XST_MUXCY" value="13"/>
<item dataType="int" stringID="XST_VCC" value="1"/>
<item dataType="int" stringID="XST_XORCY" value="15"/>
</item>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="32">
<item dataType="int" stringID="XST_FD" value="15"/>
<item dataType="int" stringID="XST_FD1" value="17"/>
</item>
<item dataType="int" stringID="XST_CLOCK_BUFFERS" value="2">
<item dataType="int" label="-bufg" stringID="XST_BUFG" value="1"/>
<item dataType="int" stringID="XST_BUFGP" value="1"/>
</item>
<item dataType="int" stringID="XST_IO_BUFFERS" value="7">
<item dataType="int" stringID="XST_OBUF" value="3"/>
<item dataType="int" stringID="XST_OBUFT" value="4"/>
</item>
</section>
</section>
<section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
<item stringID="XST_SELECTED_DEVICE" value="6slx16csg324-2"/>
<item AVAILABLE="18224" dataType="int" label="Number of Slice Registers" stringID="XST_NUMBER_OF_SLICE_REGISTERS" value="32"/>
<item AVAILABLE="9112" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="34"/>
<item AVAILABLE="9112" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="34"/>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="34"/>
<item AVAILABLE="34" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="2"/>
<item AVAILABLE="34" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="0"/>
<item AVAILABLE="34" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="32"/>
<item dataType="int" label="Number of unique control sets" stringID="XST_NUMBER_OF_UNIQUE_CONTROL_SETS" value="3"/>
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="21"/>
<item AVAILABLE="232" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="8"/>
<item AVAILABLE="16" dataType="int" label="Number of BUFG/BUFGCTRLs" stringID="XST_NUMBER_OF_BUFGBUFGCTRLS" value="2"/>
</section>
<section stringID="XST_PARTITION_RESOURCE_SUMMARY">
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
</section>
<section stringID="XST_ERRORS_STATISTICS">
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="32"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="1"/>
</section>
</application>
</document>

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<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR>&nbsp;<BR><HR>&nbsp;<BR>
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='4'><B>Software Version and Target Device</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD>
<TD><xtag-property name="ProductVersion">ISE:14.7</xtag-property><xtag-property name="ProductConfiguration"> (WebPack)</xtag-property><xtag-property name="BuildVersion"> - P.20131013</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Family:</B></TD>
<TD><xtag-property name="TargetFamily">Spartan6</xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>OS Platform:</B></TD>
<TD><xtag-property name="OSPlatform">NT64</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD><xtag-property name="TargetDevice">xc6slx16</xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project ID (random number)</B></TD>
<TD><xtag-property name="RandomID">bd16c3ee05c44948bef10dae3c70184a</xtag-property>.<xtag-property name="ProjectID">047E6D81914F4B9E9C732FAABBF95C82</xtag-property>.<xtag-property name="ProjectIteration">1</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Package:</B></TD>
<TD><xtag-property name="TargetPackage">csg324</xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Registration ID</B></TD>
<TD><xtag-property name="RegistrationID">212425623_0_0_843</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Speed:</B></TD>
<TD><xtag-property name="TargetSpeed">-2</xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Date Generated</B></TD>
<TD><xtag-property name="Date Generated">2022-06-08T11:36:14</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Tool Flow</B></TD>
<TD><xtag-property name="ToolFlow">ISE</xtag-property></TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="UserEnvironment">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>User Environment</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Name</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Name</xtag-env-param-name>"><xtag-env-param-value>Microsoft Windows 7 , 64-bit</xtag-env-param-value></xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Release</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Release</xtag-env-param-name>"><xtag-env-param-value>Service Pack 1 (build 7601)</xtag-env-param-value></xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Name</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Name</xtag-env-param-name>"><xtag-env-param-value>Intel(R) Core(TM)2 Duo CPU T9600 @ 2.80GHz</xtag-env-param-value></xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Speed</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Speed</xtag-env-param-name>"><xtag-env-param-value>2793 MHz</xtag-env-param-value></xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Name</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Name</xtag-env-param-name>"><xtag-env-param-value>Microsoft Windows 7 , 64-bit</xtag-env-param-value></xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Release</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Release</xtag-env-param-name>"><xtag-env-param-value>Service Pack 1 (build 7601)</xtag-env-param-value></xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Name</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Name</xtag-env-param-name>"><xtag-env-param-value>Intel(R) Core(TM)2 Duo CPU T9600 @ 2.80GHz</xtag-env-param-value></xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Speed</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Speed</xtag-env-param-name>"><xtag-env-param-value>2793 MHz</xtag-env-param-value></xtag-property></TD>
</TR>
</xtag-section></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Device Usage Statistics</B></TD></TR>
<TR ALIGN=CENTER BGCOLOR='#FFFF99'><TD><B>Macro Statistics</B></TD><TD><B>Miscellaneous Statistics</B></TD><TD><B>Net Statistics</B></TD><TD><B>Site Usage</B></TD></TR><TR VALIGN=TOP>
<xtag-section name="MacroStatistics">
<TD>
<xtag-group><xtag-group-name name="Counters=2">Counters=2</xtag-group-name>
<UL>
<LI><xtag-item1>24-bit up counter=1</xtag-item1></LI>
<LI><xtag-item1>9-bit up counter=1</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="Multiplexers=4">Multiplexers=4</xtag-group-name>
<UL>
<LI><xtag-item1>16-bit 2-to-1 multiplexer=4</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="RAMs=1">RAMs=1</xtag-group-name>
<UL>
<LI><xtag-item1>8x4-bit single-port distributed Read Only RAM=1</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="Registers=17">Registers=17</xtag-group-name>
<UL>
<LI><xtag-item1>Flip-Flops=17</xtag-item1></LI>
</UL>
</xtag-group>
</TD>
</xtag-section>
<xtag-section name="DesignStatistics">
<TD>
<xtag-group><xtag-group-name name="MiscellaneousStatistics">MiscellaneousStatistics</xtag-group-name>
<UL>
<LI><xtag-item1>AGG_BONDED_IO=17</xtag-item1></LI>
<LI><xtag-item1>AGG_IO=17</xtag-item1></LI>
<LI><xtag-item1>AGG_LOCED_IO=17</xtag-item1></LI>
<LI><xtag-item1>AGG_SLICE=11</xtag-item1></LI>
<LI><xtag-item1>NUM_BONDED_IOB=17</xtag-item1></LI>
<LI><xtag-item1>NUM_BSFULL=30</xtag-item1></LI>
<LI><xtag-item1>NUM_BSLUTONLY=1</xtag-item1></LI>
<LI><xtag-item1>NUM_BSUSED=31</xtag-item1></LI>
<LI><xtag-item1>NUM_BUFG=2</xtag-item1></LI>
<LI><xtag-item1>NUM_LOCED_IOB=17</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O5ANDO6=4</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O5ONLY=11</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O6ONLY=14</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_DRIVES_CARRY4=2</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_EXO6=2</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_O6=11</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEL=5</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEX=6</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CARRY4=5</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CONTROLSET=2</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CYINIT=48</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_FF=32</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_UNUSEDCTRL=1</xtag-item1></LI>
<LI><xtag-item1>NUM_UNUSABLE_FF_BELS=8</xtag-item1></LI>
</UL>
</xtag-group>
</TD>
<TD>
<xtag-group><xtag-group-name name="NetStatistics">NetStatistics</xtag-group-name>
<UL>
<LI><xtag-item1>NumNets_Active=69</xtag-item1></LI>
<LI><xtag-item1>NumNets_Vcc=1</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEACROSS=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEIN=6</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BUFGOUT=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BUFHINP2OUT=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=10</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPINFEED=6</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=8</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GENERIC=4</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=14</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_INPUT=5</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBIN2OUT=3</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBOUTPUT=3</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_LUTINPUT=86</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTBOUND=33</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=39</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PADINPUT=3</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PADOUTPUT=1</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINBOUNCE=19</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINFEED=102</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_QUAD=22</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_SINGLE=20</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_HVCCOUT=5</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_LUTINPUT=15</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PINFEED=15</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SiteStatistics">SiteStatistics</xtag-group-name>
<UL>
<LI><xtag-item1>BUFG-BUFGMUX=2</xtag-item1></LI>
<LI><xtag-item1>IOB-IOBM=10</xtag-item1></LI>
<LI><xtag-item1>IOB-IOBS=7</xtag-item1></LI>
<LI><xtag-item1>SLICEL-SLICEM=2</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEL=1</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEM=2</xtag-item1></LI>
</UL>
</xtag-group>
</TD>
</xtag-section>
<xtag-section name="DeviceUsage">
<TD>
<xtag-group><xtag-group-name name="SiteSummary">SiteSummary</xtag-group-name>
<UL>
<LI><xtag-item2>BUFG=2</xtag-item2></LI>
<LI><xtag-item2>BUFG_BUFG=2</xtag-item2></LI>
<LI><xtag-item2>CARRY4=5</xtag-item2></LI>
<LI><xtag-item2>FF_SR=2</xtag-item2></LI>
<LI><xtag-item2>HARD0=2</xtag-item2></LI>
<LI><xtag-item2>IOB=17</xtag-item2></LI>
<LI><xtag-item2>IOB_IMUX=14</xtag-item2></LI>
<LI><xtag-item2>IOB_INBUF=14</xtag-item2></LI>
<LI><xtag-item2>IOB_OUTBUF=3</xtag-item2></LI>
<LI><xtag-item2>LUT5=15</xtag-item2></LI>
<LI><xtag-item2>LUT6=31</xtag-item2></LI>
<LI><xtag-item2>PAD=17</xtag-item2></LI>
<LI><xtag-item2>REG_SR=30</xtag-item2></LI>
<LI><xtag-item2>SLICEL=5</xtag-item2></LI>
<LI><xtag-item2>SLICEX=6</xtag-item2></LI>
</UL>
</xtag-group>
</TD>
</xtag-section>
</TR></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Configuration Data</B></TD></TR><TR VALIGN=TOP>
<xtag-section name="ReportConfigData">
<TD>
<xtag-group><xtag-group-name name="FF_SR">FF_SR</xtag-group-name>
<UL>
<LI><xtag-item3>CK=[CK:0] [CK_INV:2]</xtag-item3></LI>
<LI><xtag-item3>SRINIT=[SRINIT0:2]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:2]</xtag-item3></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="IOB_OUTBUF">IOB_OUTBUF</xtag-group-name>
<UL>
<LI><xtag-item3>DRIVEATTRBOX=[12:3]</xtag-item3></LI>
<LI><xtag-item3>SLEW=[SLOW:3]</xtag-item3></LI>
<LI><xtag-item3>SUSPEND=[3STATE:3]</xtag-item3></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name>
<UL>
<LI><xtag-item3>CK=[CK:6] [CK_INV:24]</xtag-item3></LI>
<LI><xtag-item3>LATCH_OR_FF=[FF:30]</xtag-item3></LI>
<LI><xtag-item3>SRINIT=[SRINIT0:30]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:30]</xtag-item3></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name>
<UL>
<LI><xtag-item3>CLK=[CLK:2] [CLK_INV:3]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name>
<UL>
<LI><xtag-item3>CLK=[CLK:0] [CLK_INV:5]</xtag-item3></LI>
</UL>
</xtag-group>
</TD>
</xtag-section>
</TR></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Pin Data</B></TD></TR><TR VALIGN=TOP>
<xtag-section name="ReportConfigData">
<TD>
<xtag-group><xtag-group-name name="BUFG">BUFG</xtag-group-name>
<UL>
<LI><xtag-item1>I0=2</xtag-item1></LI>
<LI><xtag-item1>O=2</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="BUFG_BUFG">BUFG_BUFG</xtag-group-name>
<UL>
<LI><xtag-item1>I0=2</xtag-item1></LI>
<LI><xtag-item1>O=2</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="CARRY4">CARRY4</xtag-group-name>
<UL>
<LI><xtag-item1>CIN=3</xtag-item1></LI>
<LI><xtag-item1>CO3=3</xtag-item1></LI>
<LI><xtag-item1>CYINIT=2</xtag-item1></LI>
<LI><xtag-item1>DI0=4</xtag-item1></LI>
<LI><xtag-item1>DI1=3</xtag-item1></LI>
<LI><xtag-item1>DI2=3</xtag-item1></LI>
<LI><xtag-item1>DI3=3</xtag-item1></LI>
<LI><xtag-item1>O0=5</xtag-item1></LI>
<LI><xtag-item1>O1=4</xtag-item1></LI>
<LI><xtag-item1>O2=3</xtag-item1></LI>
<LI><xtag-item1>O3=3</xtag-item1></LI>
<LI><xtag-item1>S0=5</xtag-item1></LI>
<LI><xtag-item1>S1=4</xtag-item1></LI>
<LI><xtag-item1>S2=3</xtag-item1></LI>
<LI><xtag-item1>S3=3</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="FF_SR">FF_SR</xtag-group-name>
<UL>
<LI><xtag-item1>CK=2</xtag-item1></LI>
<LI><xtag-item1>D=2</xtag-item1></LI>
<LI><xtag-item1>Q=2</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="HARD0">HARD0</xtag-group-name>
<UL>
<LI><xtag-item1>0=2</xtag-item1></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="IOB">IOB</xtag-group-name>
<UL>
<LI><xtag-item1>I=14</xtag-item1></LI>
<LI><xtag-item1>O=3</xtag-item1></LI>
<LI><xtag-item1>PAD=17</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOB_IMUX">IOB_IMUX</xtag-group-name>
<UL>
<LI><xtag-item1>I=14</xtag-item1></LI>
<LI><xtag-item1>OUT=14</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOB_INBUF">IOB_INBUF</xtag-group-name>
<UL>
<LI><xtag-item1>OUT=14</xtag-item1></LI>
<LI><xtag-item1>PAD=14</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOB_OUTBUF">IOB_OUTBUF</xtag-group-name>
<UL>
<LI><xtag-item1>IN=3</xtag-item1></LI>
<LI><xtag-item1>OUT=3</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="LUT5">LUT5</xtag-group-name>
<UL>
<LI><xtag-item1>A3=2</xtag-item1></LI>
<LI><xtag-item1>A5=2</xtag-item1></LI>
<LI><xtag-item1>O5=15</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="LUT6">LUT6</xtag-group-name>
<UL>
<LI><xtag-item1>A1=5</xtag-item1></LI>
<LI><xtag-item1>A2=10</xtag-item1></LI>
<LI><xtag-item1>A3=11</xtag-item1></LI>
<LI><xtag-item1>A4=30</xtag-item1></LI>
<LI><xtag-item1>A5=14</xtag-item1></LI>
<LI><xtag-item1>A6=29</xtag-item1></LI>
<LI><xtag-item1>O6=31</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="PAD">PAD</xtag-group-name>
<UL>
<LI><xtag-item1>PAD=17</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name>
<UL>
<LI><xtag-item1>CK=30</xtag-item1></LI>
<LI><xtag-item1>D=30</xtag-item1></LI>
<LI><xtag-item1>Q=30</xtag-item1></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name>
<UL>
<LI><xtag-item1>A4=5</xtag-item1></LI>
<LI><xtag-item1>A6=4</xtag-item1></LI>
<LI><xtag-item1>AQ=5</xtag-item1></LI>
<LI><xtag-item1>B4=4</xtag-item1></LI>
<LI><xtag-item1>B6=3</xtag-item1></LI>
<LI><xtag-item1>BQ=4</xtag-item1></LI>
<LI><xtag-item1>C4=3</xtag-item1></LI>
<LI><xtag-item1>C6=3</xtag-item1></LI>
<LI><xtag-item1>CIN=3</xtag-item1></LI>
<LI><xtag-item1>CLK=5</xtag-item1></LI>
<LI><xtag-item1>COUT=3</xtag-item1></LI>
<LI><xtag-item1>CQ=3</xtag-item1></LI>
<LI><xtag-item1>D4=3</xtag-item1></LI>
<LI><xtag-item1>D6=3</xtag-item1></LI>
<LI><xtag-item1>DQ=3</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name>
<UL>
<LI><xtag-item1>A=1</xtag-item1></LI>
<LI><xtag-item1>A2=2</xtag-item1></LI>
<LI><xtag-item1>A3=3</xtag-item1></LI>
<LI><xtag-item1>A4=5</xtag-item1></LI>
<LI><xtag-item1>A5=4</xtag-item1></LI>
<LI><xtag-item1>A6=6</xtag-item1></LI>
<LI><xtag-item1>AMUX=1</xtag-item1></LI>
<LI><xtag-item1>AQ=5</xtag-item1></LI>
<LI><xtag-item1>B1=1</xtag-item1></LI>
<LI><xtag-item1>B2=2</xtag-item1></LI>
<LI><xtag-item1>B3=4</xtag-item1></LI>
<LI><xtag-item1>B4=4</xtag-item1></LI>
<LI><xtag-item1>B5=4</xtag-item1></LI>
<LI><xtag-item1>B6=4</xtag-item1></LI>
<LI><xtag-item1>BMUX=1</xtag-item1></LI>
<LI><xtag-item1>BQ=4</xtag-item1></LI>
<LI><xtag-item1>C1=2</xtag-item1></LI>
<LI><xtag-item1>C2=3</xtag-item1></LI>
<LI><xtag-item1>C3=3</xtag-item1></LI>
<LI><xtag-item1>C4=3</xtag-item1></LI>
<LI><xtag-item1>C5=3</xtag-item1></LI>
<LI><xtag-item1>C6=3</xtag-item1></LI>
<LI><xtag-item1>CLK=5</xtag-item1></LI>
<LI><xtag-item1>CQ=3</xtag-item1></LI>
<LI><xtag-item1>D1=2</xtag-item1></LI>
<LI><xtag-item1>D2=3</xtag-item1></LI>
<LI><xtag-item1>D3=3</xtag-item1></LI>
<LI><xtag-item1>D4=3</xtag-item1></LI>
<LI><xtag-item1>D5=3</xtag-item1></LI>
<LI><xtag-item1>D6=3</xtag-item1></LI>
<LI><xtag-item1>DQ=3</xtag-item1></LI>
</UL>
</TD>
<TD>
</xtag-group>
</TD>
</xtag-section>
</TR></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD><B>Tool Usage</B></TD></TR>
<TR VALIGN=TOP><TD ALIGN=LEFT>Command Line History<xtag-section name="CommandLineLog"><UL>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx16-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
</xtag-section></UL></TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'><xtag-section name="RunStatistics"><TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=8><B>Software Quality</B></TD></TR><TR ALIGN=LEFT><TD COLSPAN=8><B>Run Statistics</B></TD></TR><TR ALIGN=CENTER BGCOLOR='#FFFF99'><TD><B>Program Name</B></TD><TD><B>Runs Started</B></TD><TD><B>Runs Finished</B></TD><TD><B>Errors</B></TD><TD><B>Fatal Errors</B></TD><TD><B>Internal Errors</B></TD><TD><B>Exceptions</B></TD><TD><B>Core Dumps</B></TD></TR>
<tr>
<td><xtag-program-name>_impact</xtag-program-name></td>
<td><xtag-total-run-started>23</xtag-total-run-started></td>
<td><xtag-total-run-finished>21</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>bitgen</xtag-program-name></td>
<td><xtag-total-run-started>34</xtag-total-run-started></td>
<td><xtag-total-run-finished>34</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>map</xtag-program-name></td>
<td><xtag-total-run-started>38</xtag-total-run-started></td>
<td><xtag-total-run-finished>33</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>ngdbuild</xtag-program-name></td>
<td><xtag-total-run-started>38</xtag-total-run-started></td>
<td><xtag-total-run-finished>38</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>par</xtag-program-name></td>
<td><xtag-total-run-started>33</xtag-total-run-started></td>
<td><xtag-total-run-finished>33</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>trce</xtag-program-name></td>
<td><xtag-total-run-started>33</xtag-total-run-started></td>
<td><xtag-total-run-finished>33</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>xst</xtag-program-name></td>
<td><xtag-total-run-started>68</xtag-total-run-started></td>
<td><xtag-total-run-finished>68</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
</xtag-section></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="Project Statistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=2><B>Project Statistics</B></TD></TR>
<TR>
<TD><xtag-process-property-name>PROP_Board</xtag-process-property-name>=<xtag-process-property-value>Spartan-6 SP601 Evaluation Platform</xtag-process-property-value></TD>
<TD><xtag-design-property-name>PROP_Enable_Message_Filtering</xtag-design-property-name>=<xtag-design-property-value>false</xtag-design-property-value></TD>
</TR><TR><TD><xtag-process-property-name>PROP_FitterReportFormat</xtag-process-property-name>=<xtag-process-property-value>HTML</xtag-process-property-value></TD>
<TD><xtag-design-property-name>PROP_LastAppliedGoal</xtag-design-property-name>=<xtag-design-property-value>Balanced</xtag-design-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_LastAppliedStrategy</xtag-design-property-name>=<xtag-design-property-value>Xilinx Default (unlocked)</xtag-design-property-value></TD>
<TD><xtag-design-property-name>PROP_ManualCompileOrderImp</xtag-design-property-name>=<xtag-design-property-value>false</xtag-design-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_PropSpecInProjFile</xtag-design-property-name>=<xtag-design-property-value>Store all values</xtag-design-property-value></TD>
<TD><xtag-design-property-name>PROP_Simulator</xtag-design-property-name>=<xtag-design-property-value>ISim (VHDL/Verilog)</xtag-design-property-value></TD>
</TR><TR><TD><xtag-process-property-name>PROP_SynthTopFile</xtag-process-property-name>=<xtag-process-property-value>changed</xtag-process-property-value></TD>
<TD><xtag-design-property-name>PROP_Top_Level_Module_Type</xtag-design-property-name>=<xtag-design-property-value>HDL</xtag-design-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_UseSmartGuide</xtag-design-property-name>=<xtag-design-property-value>false</xtag-design-property-value></TD>
<TD><xtag-process-property-name>PROP_UserConstraintEditorPreference</xtag-process-property-name>=<xtag-process-property-value>Text Editor</xtag-process-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_intProjectCreationTimestamp</xtag-design-property-name>=<xtag-design-property-value>2022-06-08T11:31:57</xtag-design-property-value></TD>
<TD><xtag-design-property-name>PROP_intWbtProjectID</xtag-design-property-name>=<xtag-design-property-value>047E6D81914F4B9E9C732FAABBF95C82</xtag-design-property-value></TD>
</TR><TR><TD><xtag-process-property-name>PROP_intWbtProjectIteration</xtag-process-property-name>=<xtag-process-property-value>1</xtag-process-property-value></TD>
<TD><xtag-design-property-name>PROP_intWorkingDirLocWRTProjDir</xtag-design-property-name>=<xtag-design-property-value>Same</xtag-design-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_intWorkingDirUsed</xtag-design-property-name>=<xtag-design-property-value>No</xtag-design-property-value></TD>
<TD><xtag-design-property-name>PROP_AutoTop</xtag-design-property-name>=<xtag-design-property-value>true</xtag-design-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_DevFamily</xtag-design-property-name>=<xtag-design-property-value>Spartan6</xtag-design-property-value></TD>
<TD><xtag-design-property-name>PROP_DevDevice</xtag-design-property-name>=<xtag-design-property-value>xc6slx16</xtag-design-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_DevFamilyPMName</xtag-design-property-name>=<xtag-design-property-value>spartan6</xtag-design-property-value></TD>
<TD><xtag-design-property-name>PROP_DevPackage</xtag-design-property-name>=<xtag-design-property-value>csg324</xtag-design-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_Synthesis_Tool</xtag-design-property-name>=<xtag-design-property-value>XST (VHDL/Verilog)</xtag-design-property-value></TD>
<TD><xtag-design-property-name>PROP_DevSpeed</xtag-design-property-name>=<xtag-design-property-value>-2</xtag-design-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_PreferredLanguage</xtag-design-property-name>=<xtag-design-property-value>VHDL</xtag-design-property-value></TD>
<TD><xtag-source-property-name>FILE_UCF</xtag-source-property-name>=<xtag-source-property-value>1</xtag-source-property-value></TD>
</TR><TR><TD><xtag-source-property-name>FILE_VHDL</xtag-source-property-name>=<xtag-source-property-value>1</xtag-source-property-value></TD>
</TR></xtag-section></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="UnisimStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Unisim Statistics</B></TD></TR>
<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_PRE_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFG</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFGP</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FD</xtag-preunisim-param-name>=<xtag-preunisim-param-value>15</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FD_1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>17</xtag-preunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_GND</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_INV</xtag-preunisim-param-name>=<xtag-preunisim-param-value>4</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>13</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT2</xtag-preunisim-param-name>=<xtag-preunisim-param-value>5</xtag-preunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT3</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT4</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT5</xtag-preunisim-param-name>=<xtag-preunisim-param-value>5</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT6</xtag-preunisim-param-name>=<xtag-preunisim-param-value>5</xtag-preunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>13</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>3</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUFT</xtag-preunisim-param-name>=<xtag-preunisim-param-value>4</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_VCC</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_XORCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>15</xtag-preunisim-param-value></TD>
<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_POST_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_BUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>2</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FD</xtag-postunisim-param-name>=<xtag-postunisim-param-value>15</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FD_1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>17</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_GND</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>13</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_INV</xtag-postunisim-param-name>=<xtag-postunisim-param-value>4</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>13</xtag-postunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT2</xtag-postunisim-param-name>=<xtag-postunisim-param-value>5</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT3</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT4</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT5</xtag-postunisim-param-name>=<xtag-postunisim-param-value>5</xtag-postunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT6</xtag-postunisim-param-name>=<xtag-postunisim-param-value>5</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>13</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>3</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUFT</xtag-postunisim-param-name>=<xtag-postunisim-param-value>4</xtag-postunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_VCC</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_XORCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>15</xtag-postunisim-param-value></TD>
</xtag-section></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="XstCommandLineOptions">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>XST Command Line Options</B></TD></TR>
<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-xstoption-type-name>XST_OPTION_SUMMARY</xtag-xstoption-type-name></B></TD></TR><TR>
<TD><xtag-xstoptions-param-name>-ifn</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>&lt;fname&gt;.prj</xtag-xstoptions-param-value></TD>
<TD><xtag-xstoptions-param-name>-ofn</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>&lt;design_top&gt;</xtag-xstoptions-param-value></TD>
<TD><xtag-xstoptions-param-name>-ofmt</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>NGC</xtag-xstoptions-param-value></TD>
<TD><xtag-xstoptions-param-name>-p</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>xc6slx16-2-csg324</xtag-xstoptions-param-value></TD>
</TR>
<TR>
<TD><xtag-xstoptions-param-name>-top</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>&lt;design_top&gt;</xtag-xstoptions-param-value></TD>
<TD><xtag-xstoptions-param-name>-opt_mode</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>Speed</xtag-xstoptions-param-value></TD>
<TD><xtag-xstoptions-param-name>-opt_level</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>1</xtag-xstoptions-param-value></TD>
<TD><xtag-xstoptions-param-name>-power</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>NO</xtag-xstoptions-param-value></TD>
</TR>
<TR>
<TD><xtag-xstoptions-param-name>-iuc</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>NO</xtag-xstoptions-param-value></TD>
<TD><xtag-xstoptions-param-name>-keep_hierarchy</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>No</xtag-xstoptions-param-value></TD>
<TD><xtag-xstoptions-param-name>-netlist_hierarchy</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>As_Optimized</xtag-xstoptions-param-value></TD>
<TD><xtag-xstoptions-param-name>-rtlview</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>Yes</xtag-xstoptions-param-value></TD>
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<TD><xtag-xstoptions-param-name>-async_to_sync</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>NO</xtag-xstoptions-param-value></TD>
<TD><xtag-xstoptions-param-name>-use_dsp48</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>Auto</xtag-xstoptions-param-value></TD>
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<TR>
<TD><xtag-xstoptions-param-name>-bufg</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>16</xtag-xstoptions-param-value></TD>
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<TD><xtag-xstoptions-param-name>-equivalent_register_removal</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>YES</xtag-xstoptions-param-value></TD>
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Release 14.7 - WebTalk (P.20131013)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Project Information
--------------------
ProjectID=047E6D81914F4B9E9C732FAABBF95C82
ProjectIteration=1
WebTalk Summary
----------------
INFO:WebTalk:2 - WebTalk is enabled.
INFO:WebTalk:8 - WebTalk Install setting is ON.
INFO:WebTalk:6 - WebTalk User setting is ON.
INFO:WebTalk:5 - C:/Users/Gabriel/Xilinx/Aula20220608/usage_statistics_webtalk.html WebTalk report has not been sent to Xilinx. Please check your network and proxy settings. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/14.7/ISE_DS/ISE/data/reports/webtalk_introduction.html

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The structure and the elements are likely to change over the next few releases.
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