26 lines
498 B
Plaintext
26 lines
498 B
Plaintext
Release 14.7 - par P.20131013 (nt64)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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Wed Jun 08 11:35:52 2022
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All signals are completely routed.
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WARNING:ParHelpers:361 - There are 13 loadless signals in this design. This design will cause Bitgen to issue DRC
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warnings.
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BUT<0>_IBUF
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BUT<1>_IBUF
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BUT<2>_IBUF
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BUT<3>_IBUF
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DIPSW<0>_IBUF
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DIPSW<1>_IBUF
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DIPSW<2>_IBUF
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DIPSW<3>_IBUF
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GPIO<3>_IBUF
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GPIO<4>_IBUF
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GPIO<5>_IBUF
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GPIO<6>_IBUF
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GPIO<7>_IBUF
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