diff --git a/Aula20220608.gise b/Aula20220608.gise new file mode 100644 index 0000000..57a5a03 --- /dev/null +++ b/Aula20220608.gise @@ -0,0 +1,186 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Aula20220608.xise b/Aula20220608.xise index cf64db1..b04d100 100644 --- a/Aula20220608.xise +++ b/Aula20220608.xise @@ -9,30 +9,393 @@ - + - + + + + + + + + - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/_ngo/netlist.lst b/_ngo/netlist.lst new file mode 100644 index 0000000..0137122 --- /dev/null +++ b/_ngo/netlist.lst @@ -0,0 +1,2 @@ +C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.ngc 1654698883 +OK diff --git a/_xmsgs/bitgen.xmsgs b/_xmsgs/bitgen.xmsgs new file mode 100644 index 0000000..c42b14a --- /dev/null +++ b/_xmsgs/bitgen.xmsgs @@ -0,0 +1,9 @@ + + + + + diff --git a/_xmsgs/map.xmsgs b/_xmsgs/map.xmsgs new file mode 100644 index 0000000..e79f356 --- /dev/null +++ b/_xmsgs/map.xmsgs @@ -0,0 +1,51 @@ + + + +Logical network BUT<3>_IBUF has no load. + + +The above info message is repeated 12 more times for the following (max. 5 shown): +BUT<2>_IBUF, +BUT<1>_IBUF, +BUT<0>_IBUF, +DIPSW<3>_IBUF, +DIPSW<2>_IBUF +To see the details of these info messages, please use the -detail switch. + + +No environment variables are currently set. + + +Signal LEDS<3> connected to top level port LEDS<3> has been removed. + + +Signal LEDS<2> connected to top level port LEDS<2> has been removed. + + +Signal LEDS<1> connected to top level port LEDS<1> has been removed. + + +Signal LEDS<0> connected to top level port LEDS<0> has been removed. + + +All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. + + +Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) + + +Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) + + +The Interim Design Summary has been generated in the MAP Report (.mrp). + + +Map created a placed design. + + + + diff --git a/_xmsgs/ngdbuild.xmsgs b/_xmsgs/ngdbuild.xmsgs new file mode 100644 index 0000000..0516b33 --- /dev/null +++ b/_xmsgs/ngdbuild.xmsgs @@ -0,0 +1,24 @@ + + + +bidirect pad net 'GPIO<7>' has no legal driver + + +bidirect pad net 'GPIO<6>' has no legal driver + + +bidirect pad net 'GPIO<5>' has no legal driver + + +bidirect pad net 'GPIO<4>' has no legal driver + + +bidirect pad net 'GPIO<3>' has no legal driver + + + + diff --git a/_xmsgs/par.xmsgs b/_xmsgs/par.xmsgs new file mode 100644 index 0000000..096bb45 --- /dev/null +++ b/_xmsgs/par.xmsgs @@ -0,0 +1,64 @@ + + + +No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". + + +The signal BUT<2>_IBUF has no load. PAR will not attempt to route this signal. + + +The signal BUT<3>_IBUF has no load. PAR will not attempt to route this signal. + + +The signal GPIO<3>_IBUF has no load. PAR will not attempt to route this signal. + + +The signal GPIO<4>_IBUF has no load. PAR will not attempt to route this signal. + + +The signal GPIO<5>_IBUF has no load. PAR will not attempt to route this signal. + + +The signal GPIO<6>_IBUF has no load. PAR will not attempt to route this signal. + + +The signal GPIO<7>_IBUF has no load. PAR will not attempt to route this signal. + + +The signal DIPSW<0>_IBUF has no load. PAR will not attempt to route this signal. + + +The signal DIPSW<1>_IBUF has no load. PAR will not attempt to route this signal. + + +The signal DIPSW<2>_IBUF has no load. PAR will not attempt to route this signal. + + +The signal DIPSW<3>_IBUF has no load. PAR will not attempt to route this signal. + + +The signal BUT<0>_IBUF has no load. PAR will not attempt to route this signal. + + +The signal BUT<1>_IBUF has no load. PAR will not attempt to route this signal. + + +The Clock Report is not displayed in the non timing-driven mode. + + +N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI. + +There are 13 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. + + + +There are 13 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. + + + + + diff --git a/_xmsgs/pn_parser.xmsgs b/_xmsgs/pn_parser.xmsgs index 6d46583..a31e8ca 100644 --- a/_xmsgs/pn_parser.xmsgs +++ b/_xmsgs/pn_parser.xmsgs @@ -8,5 +8,8 @@ +Parsing VHDL file "C:/Users/Gabriel/Xilinx/Aula20220608/textovhdl.vhd" into library work + + diff --git a/_xmsgs/trce.xmsgs b/_xmsgs/trce.xmsgs new file mode 100644 index 0000000..cf1a072 --- /dev/null +++ b/_xmsgs/trce.xmsgs @@ -0,0 +1,17 @@ + + + +No timing constraints found, doing default enumeration. + +To improve timing, see the Timing Closure User Guide (UG612). + +To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. + +The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. + + + diff --git a/_xmsgs/xst.xmsgs b/_xmsgs/xst.xmsgs new file mode 100644 index 0000000..f09cf90 --- /dev/null +++ b/_xmsgs/xst.xmsgs @@ -0,0 +1,108 @@ + + + +"C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 64: Assignment to clk100k ignored, since the identifier is never used + + +"C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 65: Assignment to clk25k ignored, since the identifier is never used + + +"C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 66: Assignment to clk621ms ignored, since the identifier is never used + + +"C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 20: Net <num7[3]> does not have a driver. + + +Input <BUT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <DIPSW> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal <num7> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <num6> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <num5> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <num4> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <num3> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <num2> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <num1> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <num0> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +HDL ADVISOR - The RAM <Mram_proxdisplay> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + + +Node <contaux_6> of sequential type is unconnected in block <textovhdl>. + + +Node <contaux_7> of sequential type is unconnected in block <textovhdl>. + + +Node <contaux_8> of sequential type is unconnected in block <textovhdl>. + + +Node <contaux_9> of sequential type is unconnected in block <textovhdl>. + + +Node <contaux_10> of sequential type is unconnected in block <textovhdl>. + + +Node <contaux_11> of sequential type is unconnected in block <textovhdl>. + + +Node <contaux_12> of sequential type is unconnected in block <textovhdl>. + + +Node <contaux_13> of sequential type is unconnected in block <textovhdl>. + + +Node <contaux_14> of sequential type is unconnected in block <textovhdl>. + + +Node <contaux_15> of sequential type is unconnected in block <textovhdl>. + + +Node <contaux_16> of sequential type is unconnected in block <textovhdl>. + + +Node <contaux_17> of sequential type is unconnected in block <textovhdl>. + + +Node <contaux_18> of sequential type is unconnected in block <textovhdl>. + + +Node <contaux_19> of sequential type is unconnected in block <textovhdl>. + + +Node <contaux_20> of sequential type is unconnected in block <textovhdl>. + + +Node <contaux_21> of sequential type is unconnected in block <textovhdl>. + + +Node <contaux_22> of sequential type is unconnected in block <textovhdl>. + + +Node <contaux_23> of sequential type is unconnected in block <textovhdl>. + + + + diff --git a/iseconfig/textovhdl.xreport b/iseconfig/textovhdl.xreport new file mode 100644 index 0000000..5d8e211 --- /dev/null +++ b/iseconfig/textovhdl.xreport @@ -0,0 +1,215 @@ + + +
+ 2022-06-08T11:32:41 + textovhdl + Unknown + C:/Users/Gabriel/Xilinx/Aula20220608/iseconfig/textovhdl.xreport + C:/Users/Gabriel/Xilinx/Aula20220608 + 2022-06-08T11:32:41 + false +
+ + + + + + + + + + + + + + + + + + + + + + + + diff --git a/par_usage_statistics.html b/par_usage_statistics.html new file mode 100644 index 0000000..f083ecd --- /dev/null +++ b/par_usage_statistics.html @@ -0,0 +1,32 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Par Statistics
Total Non-vccgnd Signals=39
Total Non-vccgnd Design Pins=104
Total Non-vccgnd Conns=104
Total Non-vccgnd Timing Constrained Conns=100
Phase 1 CPU=4.4 sec
Phase 2 CPU=4.7 sec
Phase 3 CPU=4.9 sec
Phase 4 CPU=5.6 sec
Phase 5 CPU=5.7 sec
Phase 6 CPU=5.7 sec
Phase 7 CPU=5.7 sec
Phase 8 CPU=5.7 sec
Phase 9 CPU=5.8 sec
Phase 10 CPU=5.8 sec
AvgWirelenPerPin Fanout 1=2.0
AvgWirelenPerPin Fanout 2=2.0
AvgWirelenPerPin Fanout 3=9.7
AvgWirelenPerPin Fanout 4=0.0
AvgWirelenPerPin Fanout 10=4.1
AvgWirelenPerPin Fanout 50=0.6
AvgWirelenPerPin Fanout 100=0.0
AvgWirelenPerPin Fanout 500=0.0
AvgWirelenPerPin Fanout 5000=0.0
AvgWirelenPerPin Fanout 20000=0.0
AvgWirelenPerPin Fanout 50000=0.0
AvgWirelenPerPin Fanout 100000=0.0
IRR Gamma=1.0050
diff --git a/textovhdl.bgn b/textovhdl.bgn new file mode 100644 index 0000000..5c2e1e9 --- /dev/null +++ b/textovhdl.bgn @@ -0,0 +1,134 @@ +Release 14.7 - Bitgen P.20131013 (nt64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +Loading device for application Rf_Device from file '6slx16.nph' in environment +C:\Xilinx\14.7\ISE_DS\ISE\. + "textovhdl" is an NCD, version 3.2, device xc6slx16, package csg324, speed -2 +Opened constraints file textovhdl.pcf. + +Wed Jun 08 11:36:09 2022 + +C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 textovhdl.ncd + +Summary of Bitgen Options: ++----------------------+----------------------+ +| Option Name | Current Setting | ++----------------------+----------------------+ +| Compress | (Not Specified)* | ++----------------------+----------------------+ +| Readback | (Not Specified)* | ++----------------------+----------------------+ +| CRC | Enable** | ++----------------------+----------------------+ +| DebugBitstream | No** | ++----------------------+----------------------+ +| ConfigRate | 2** | ++----------------------+----------------------+ +| StartupClk | Cclk** | ++----------------------+----------------------+ +| DonePin | Pullup* | ++----------------------+----------------------+ +| ProgPin | Pullup** | ++----------------------+----------------------+ +| TckPin | Pullup** | ++----------------------+----------------------+ +| TdiPin | Pullup** | ++----------------------+----------------------+ +| TdoPin | Pullup** | ++----------------------+----------------------+ +| TmsPin | Pullup** | ++----------------------+----------------------+ +| UnusedPin | Pulldown** | ++----------------------+----------------------+ +| GWE_cycle | 6** | ++----------------------+----------------------+ +| GTS_cycle | 5** | ++----------------------+----------------------+ +| LCK_cycle | NoWait** | ++----------------------+----------------------+ +| DONE_cycle | 4** | ++----------------------+----------------------+ +| Persist | No* | ++----------------------+----------------------+ +| DriveDone | No** | ++----------------------+----------------------+ +| DonePipe | No** | ++----------------------+----------------------+ +| Security | None** | ++----------------------+----------------------+ +| UserID | 0xFFFFFFFF** | ++----------------------+----------------------+ +| ActiveReconfig | No* | ++----------------------+----------------------+ +| Partial | (Not Specified)* | ++----------------------+----------------------+ +| Encrypt | No* | ++----------------------+----------------------+ +| Key0 | pick* | ++----------------------+----------------------+ +| StartCBC | pick* | ++----------------------+----------------------+ +| KeyFile | (Not Specified)* | ++----------------------+----------------------+ +| drive_awake | No** | ++----------------------+----------------------+ +| Reset_on_err | No** | ++----------------------+----------------------+ +| suspend_filter | Yes* | ++----------------------+----------------------+ +| en_sw_gsr | No** | ++----------------------+----------------------+ +| en_suspend | No* | ++----------------------+----------------------+ +| sw_clk | Startupclk** | ++----------------------+----------------------+ +| sw_gwe_cycle | 5** | ++----------------------+----------------------+ +| sw_gts_cycle | 4** | ++----------------------+----------------------+ +| multipin_wakeup | No** | ++----------------------+----------------------+ +| wakeup_mask | 0x00* | ++----------------------+----------------------+ +| ExtMasterCclk_en | No** | ++----------------------+----------------------+ +| ExtMasterCclk_divide | 1* | ++----------------------+----------------------+ +| CrcCoverage | No* | ++----------------------+----------------------+ +| glutmask | Yes* | ++----------------------+----------------------+ +| next_config_addr | 0x00000000* | ++----------------------+----------------------+ +| next_config_new_mode | No* | ++----------------------+----------------------+ +| next_config_boot_mode | 001* | ++----------------------+----------------------+ +| next_config_register_write | Enable* | ++----------------------+----------------------+ +| next_config_reboot | Enable* | ++----------------------+----------------------+ +| golden_config_addr | 0x00000000* | ++----------------------+----------------------+ +| failsafe_user | 0x0000* | ++----------------------+----------------------+ +| TIMER_CFG | 0xFFFF | ++----------------------+----------------------+ +| spi_buswidth | 1** | ++----------------------+----------------------+ +| TimeStamp | Default* | ++----------------------+----------------------+ +| IEEE1532 | No* | ++----------------------+----------------------+ +| Binary | No** | ++----------------------+----------------------+ + * Default setting. + ** The specified setting matches the default setting. + +There were 0 CONFIG constraint(s) processed from textovhdl.pcf. + + +Running DRC. +DRC detected 0 errors and 0 warnings. +Creating bit map... +Saving bit stream in "textovhdl.bit". +Bitstream generation is complete. diff --git a/textovhdl.bit b/textovhdl.bit new file mode 100644 index 0000000..c1cad21 Binary files /dev/null and b/textovhdl.bit differ diff --git a/textovhdl.bld b/textovhdl.bld new file mode 100644 index 0000000..904fa82 --- /dev/null +++ b/textovhdl.bld @@ -0,0 +1,41 @@ +Release 14.7 ngdbuild P.20131013 (nt64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe +-intstyle ise -dd _ngo -nt timestamp -uc restricoes.ucf -p xc6slx16-csg324-2 +textovhdl.ngc textovhdl.ngd + +Reading NGO file "C:/Users/Gabriel/Xilinx/Aula20220608/textovhdl.ngc" ... +Gathering constraint information from source properties... +Done. + +Annotating constraints to design from ucf file "restricoes.ucf" ... +Resolving constraint associations... +Checking Constraint Associations... +Done... + +Checking expanded design ... +WARNING:NgdBuild:470 - bidirect pad net 'GPIO<7>' has no legal driver +WARNING:NgdBuild:470 - bidirect pad net 'GPIO<6>' has no legal driver +WARNING:NgdBuild:470 - bidirect pad net 'GPIO<5>' has no legal driver +WARNING:NgdBuild:470 - bidirect pad net 'GPIO<4>' has no legal driver +WARNING:NgdBuild:470 - bidirect pad net 'GPIO<3>' has no legal driver + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +NGDBUILD Design Results Summary: + Number of errors: 0 + Number of warnings: 5 + +Total memory usage is 161712 kilobytes + +Writing NGD file "textovhdl.ngd" ... +Total REAL time to NGDBUILD completion: 3 sec +Total CPU time to NGDBUILD completion: 3 sec + +Writing NGDBUILD log file "textovhdl.bld"... diff --git a/textovhdl.cmd_log b/textovhdl.cmd_log new file mode 100644 index 0000000..6cf510c --- /dev/null +++ b/textovhdl.cmd_log @@ -0,0 +1,6 @@ +xst -intstyle ise -ifn "C:/Users/Gabriel/Xilinx/Aula20220608/textovhdl.xst" -ofn "C:/Users/Gabriel/Xilinx/Aula20220608/textovhdl.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc restricoes.ucf -p xc6slx16-csg324-2 textovhdl.ngc textovhdl.ngd +map -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o textovhdl_map.ncd textovhdl.ngd textovhdl.pcf +par -w -intstyle ise -ol high -mt off textovhdl_map.ncd textovhdl.ncd textovhdl.pcf +trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml textovhdl.twx textovhdl.ncd -o textovhdl.twr textovhdl.pcf -ucf restricoes.ucf +bitgen -intstyle ise -f textovhdl.ut textovhdl.ncd diff --git a/textovhdl.drc b/textovhdl.drc new file mode 100644 index 0000000..529ed9e --- /dev/null +++ b/textovhdl.drc @@ -0,0 +1,8 @@ +Release 14.7 Drc P.20131013 (nt64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +Wed Jun 08 11:36:09 2022 + +drc -z textovhdl.ncd textovhdl.pcf + +DRC detected 0 errors and 0 warnings. diff --git a/textovhdl.lso b/textovhdl.lso new file mode 100644 index 0000000..22de730 --- /dev/null +++ b/textovhdl.lso @@ -0,0 +1 @@ +work diff --git a/textovhdl.ncd b/textovhdl.ncd new file mode 100644 index 0000000..4d2f837 --- /dev/null +++ b/textovhdl.ncd @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6 +###6340:XlxV32DM 3fff 18aceNq1Wmlz20aT/iust/TBcSIZc+Cc2BWQgGSUKZIhKUd6t9YoXJS5K4taik6cleTfvj0HMDgdZSuOI07P08909zRmpgeUjrCNHpDBjpbF79v77e7WG6ETOjrC7Bin7Pj6ZpcmN/Hu7uCy4+3t4f7w502RUy2PtvfF6Phu9CWz7m++IOs4u78mmB7j0fEfo+Ob3fU246NHu81mdLy7GX3cXn8cHR9GaHT85TAyRsf74np7fyj2cf757mabJQeIQbL3IzqqBSDBT6rd7mV7p9qbTPV3fxQK2o0OxZfD7veP+U38Kbk7uc1yjZzcXtd7d9lmRGBWe/i4yRKmIwfgE//Y3VhMWofO3R6ZrDd0yNvBNBiffDNF1dzVDL4ZW9aOLWevxhenZ+cXl/ElviJFrUuuELHZq4UfIMMqBVsJpESIowSzRFwkBUxcJdASodgSgmmq1lKtK1uLqNY2RevIRmldE6JdTaNJGF8iekWcZtetdc2m1mxqrStiNbt2s1sfaze6GF/hVrdmmVhX2EAM/keEoRODMHKC+AeGnUC9aLa4WHvji/XPxDPeIFxBQbRY/abB+cWao9MwWAkwZeZPxk/IMH/ClNY7Ttmxf8ImRog5YBBGe2eLaP6zze0xn2TMH2XJfv/nKPuYbG9H94dkf9jeXo/+2B4+Ks2nz19G/zrPdp9vD3G2uz0kn7/E2Z8/G2/+RfLnDr8IotXilTISztR4zHyYlI/hh8APhR8TfizKfFhmIP2K2RgYY2CMgTEGxhgYY8tk4+l88s6WzeUV5HB8fraM/fV6GUEWwxWjgHAj419dxheuWL2cdxFNg3jtL89C+Ji8dQBZxdHsdG4xnn+eU9nGYOlUgkiBqA5iBWIJOqx8fFJNlJpIdcbGxc39yDghcBAtCtHzeEwx/0hlf+Ivl1c0kZ3T03i1VPJbfxkYuZSj+TiOYG5FrTsDIxvdhwcNgCuB6cXa1KLlSBF2jXK6DM/AEWYTSPUEUj2BVE8g1RNI9cSClE38IH4fhb/F78PlKprPTCbiJGwSzYDyjvPfPU799eRtPF/Gp6cQurdaRrNorRrDW13NJuLxeD4XHx8x4YP+igWk6TuHf2D7/O3/FpUksrZApAXIp0zbKH8AZ8CdExc+zs+j9ToMEhBXa1gK42kIIyBnMI9fbTZZhj6oLTa54lHlbLL7dFc9uUR2xaNzlQwpz5Qotvu00btELMAsgOwGkN0AshVAdgPILpxqLIgM/oH4B+YfxGFy0xtv8kpSK0x2UaVATQWuFGpNJkyfHyWJVCS1MiGOXzMWnp7Ol+t4Gr4Ppzk7m87H/jSezs+iCYIl0OifIKML9bBwFyJdiHYhswtZmxaC2wBpA7QNmG2gY9RuA04bgMIlTlDjjRJQKeBSIG+yUhD5VTAtYdqAzRI2G7BVwpaEXVYd3IphlwxbMlLRi414rjuo3sGig1iEWWTAz8xhsHBf8aPEldJMLBkuygPEFjKcFFAoolW4js/D83G4jMWpG4+jWRDNzl5V14ZXEWynt1G45OfqVexPz+aT+WwVY0wZV1Wnc7zgB8lqHc7W8WI5X8QrUMz46cxpym68vlqEyGFDRmE/NVWCbwkwmq3D5Qye2mIaL/3ZWQhnJ8dn8yCUPDl4GZ6Gy3AGBZqfbzYTdZVnWAioFPAbl1UlV2HkDdzHuBQTkdd1jIwT34QTtoOjk6AXxyeTXpycjAVOm/gATJWVFmwqpy3YUjG2YLuf7fTbdmUkFpvO/SAMICNQYl75uBSoEKxXPioFXAqkFCqOWQoWnIHn/iKenAfTaBbG88Uais0qEeD5PLiYhrmQ19F5uFr754tUdFVVgsHJHUTad1XphVE/jPth0g9Tvgxa8M3nA/eZ9uOwON/HRnfUl92ej+rF0QCOB3AygNMB3IRVPQvXv82X7xCbYzaH82EOe2QOBWsOBWsOxWoOxQqOhYQtTuAmCwc5gmK6ILDF/EkI9/9KLh+cxRb+5F0YECbeBuBz2X62EM0C1pU8T85mQbn3kduP8w3LLVU64fAczpFNDbxY+Wdhw/T7yaTXdA0XpttjuGu4V8Kj5Hgwh/NK3g7ii9nFKgziRTRbSdeQvngJ+QFTWQXwoyaRvbMgjgJJXQTn5aKFHAskmsX+ahWdzWJY0SoMDoaXcEjCFpOHljQsrmL1pLwPJyJ6pNXcHb9B1YfUJ1sOMWtqGVHMD1OV4wa+hNLAQ4LrchRcpqU888/5FN/FcK9arH24yQp5tlrLgwN6QShmNjs7j1fzi+UklPDp0j9bxet5PA6hvMJxnHEU6uyCB7nc8B6Mqe12APiSWr9dXkBhgLN9DA/jHb+/xeJGGot3Jv6Euyr55sQntt8ddvx6huRReDI3m+i4F52UKG2g4ooIDwMKTx98YjStBD22cW8cuDcOrONooH12aa9d2muX9s6P9s+PDs2P9sZhVnFsNGid8HsHX7JNBC6SuIsZfWAvE/eBpMcP7sH6eLQHM3swqwezezCnB3Pr6VIYrNc60znhLxwnc8TgfXZZ3H++4bWkEpEWsRaJFqkWzTeYreCAX0GqVnDAr+Acl68tUIwzLcIz0wpLK6wprwJl7/S0Io31aLHGdK8xZFwbMtFDJo0hEz4kr3rqvbjsnp5CvSk75VqsjAbaaNAwGjTiCKo4LuGmokWiRapFM9Xi6WmmOzpNlzpNl400XdbSdPlqrH2NsRa127F2O9Zux3W344bbsXY7brgd19xOtNuJdjvRbifa7cTUorY9adie1GwH2nagbQfadqBtB9p2oG0HDdvwaGy2+pjcFbFRCqhg66o483K4EX1VXER9pG0ErgLhEpa5hN/zb+J4AYHrwaaJLWGt1YFzWF+1/moRiivOWpXl6HwBgUZraWXdqOfrsnCKAKbRGC4I8vuvyQrJy1+qgHD2s/her9aL75Lsv2NUY6AGAykGLhrY/lAbgRsjsBpBigbWGEEaI4gaQYsG1hhBGyNoGTccZF0Q96KkzwDuA3uZtA+0+0CnaGCNaZiNaZh906hAoxdFfQZwH0j6QLMPtPtAt2hgjWlYjWlYfQ6tvryVoNMH1h1aLYd2w6Hdlze7N292b97svrzZfRGXoFU0sEZwTiM4p/RYNLD9obbJ/sP5T/4+tNlef97zrzBJvIOb87e0SaWNjZpcx3FNJjWZ1mSzJls12a7JDtzSe79A78fRAI4HcDKA0wHcHMCtARyWitXB1StyNqBQ78jdceoluV+BhhR4SEGGFHRIYQ4prCGFPaRw3pSFobrPtQDUBnAbIG2AtgGzDVhtwG4Dzptyq5Srvnqy1TZQm9gawIcUeMDSEE4HcHMAtwdwF4q3xO+Sm+T3fcJXkdOBVJT8zt9UIaC7XUzxzS4f1mIHw12XCFcnX4dOeuikOto7dNpD18WyQ4eF3E4J6rGgp9hm98ymnAyyOmzSddcTcO1y0GabXbapn1ebbXXZ1vBU7G5wTteAMxyc22W7VXCbpgbONaeNxNc3n4v4vji0uajtipdTtwNV47t01KWjb9AxsjtQvL8/3O16yKRLJoNk2iXTQbLZJZsl2WprlKKdO9xh4gEm6TDJAJN2mHSAaXaY5gDT6jCtAabdYdoDTKfDdAaYbofplolmlwm7DN7KV66VI2R4uZpIdPXWX4QK5a86qZDK96CcXUbTaHZ5fBmMR8YJGq3WF1LwV5MosthlnsZRDoPyT/F4e5tvb69hGfDeefJfu/37Ys//NKiEtrcaYlcmS7f5dm+z7FN+s70tEqa+zOanOqp11BbUelTXV+9SeR3aHzQd1+nVi1Reh+p0UqdXb1F5HarTaZ1eHX15HarTzTrd7MYuXgrcshsbWkRaxFokWqRaNAstit+eW0z+fRVl/I+JCNveFxDH7edPBs/W9vZ39RslUsdi9aUmYbvNhrC7ZO+we/g8JLeWy6rfGIKh1h8lXX9yWPmHXZDox2AZvQ/5Lw7H80sPYW81DX+Djzl8XMBb+SzwyGrtr8PHxzm0s8BfBt70/eR8vsImMdjf/asE8Pg4N1+/8MlL3/zh0ZZdoxTQY2ZwyXr94sVXH73knxg+oSEv4YP++MKnfOQPP/yobPzw8qtviS5+qXkvX/imVEjiCxj3C7AVJmFtv2be/LE2quyV5rV97llxhGHoKcuP1qZnClVcX6vAlNE2WkbWHPe1nDRu9MWQx8Tu8diy20nQ13aGKrs/+nQ4USWllfOORmTmR+6lTAyPlNZyoxOqUihGfe080wGOmjtJGxZ7FkBn6rXRONej26uksXAUv6T7Fk/SI9w0qj4fI+jC/iPs15ZKDKBt9KuATQU3n8yjMu/TR1dKAEvyY9TZjk+//HJHNwn75Zcv2Ey9U8/00MPKzr3C9jaFhwh1kszwMDFS8nCLieXBMYOJ7VnsCBMKCsKeVrbbw7fZKk88bLqe0cAzxvldfNOPw+bOeWgAengoNHaEHNtDjsOOTIDgDf62MD0LJ6BLASyoAI8KC4YCGaXQz9jva7i5efKf+03jhQcH168IUUjPE7SYt0fI2HgEsSMr52qgpdINcvjEcy7wGQkLGc8cQkUZVcr+hDcyjxQOF0whTJEBPh+OXD6Ksls7gUFPbzcbNi2Ilz5AyhOPQuZBDbMi0JjgXfZs2ZiyyWSTyCaVjTR7lHu4ALP8m6F/I2cDHu2NBykGyEh5EMQj0ldRjXGEhaeUPwpIFyyTwqPWw/8gKGnwYTIYm7B/m8ijDwR7BExQjzje01Y8UEi544EByIDtGUB2cvYZ7sEeNhjbmlabgjoU2qbgDgW3KaRNcStHrjkQi0valE4sLmpTOrFAVluUTiw2n1ET22VFOSzLy/gAzdoo4mjaRjFHkzZKwFdazTvtnzfoYFXA7QO4pM1Fw1zU5uJBbrJpc8kwN29z6RB3l2RtrjnMTdtca5ibtLn2EDdFfMd6BfxD6QNwXQ84wMZwOCADNqjFjwDLczDbEpUHONBoAXOlPIdsR3naoWdXWpM/OepKbSG0VqK1Nmit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SWM4fDL1iyDDY+AyModv9JDipGY/fhxomA8oaa7rl01IMLz2sOTrGe3jJqpPXE/QdB9jGhYZSvmws345FIRBWYx8/2LmGmaQFiMaGLIafC1DPrQBzV/o7pN8YYLPgZ+LCwBrhe/BIzoBvgIPzeImzSZ5zvKs+RkMJz/P8mzkWYZNMmyQ9728H+T9IO/XCy783Qvfc5EbbdhMug3SbSjSGJFGy/MizzM/s/vdvmg18SpSoiNKdESRjtAq22WVWVllQvey0mkN4SpDnfoPxUs8Rg==###2632:XlxV32DM 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0000000..1c75c28 --- /dev/null +++ b/textovhdl.pad @@ -0,0 +1,354 @@ +Release 14.7 - par P.20131013 (nt64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +Wed Jun 08 11:35:52 2022 + + +# NOTE: This file is designed to be imported into a spreadsheet program +# such as Microsoft Excel for viewing, printing and sorting. The | +# character is used as the data field separator. This file is also designed +# to support parsing. +# +INPUT FILE: textovhdl_map.ncd +OUTPUT FILE: textovhdl.pad +PART TYPE: xc6slx16 +SPEED GRADE: -2 +PACKAGE: csg324 + +Pinout by Pin Number: + +-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----| +Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|IO Register|Signal Integrity| +A1|||GND|||||||||||| +A2||IOBS|IO_L2N_0|UNUSED||0||||||||| +A3|GPIO<2>|IOB|IO_L4N_0|OUTPUT|LVCMOS25*|0|12|SLOW||||LOCATED|NO|NONE| +A4||IOBS|IO_L5N_0|UNUSED||0||||||||| +A5||IOBS|IO_L6N_0|UNUSED||0||||||||| +A6||IOBS|IO_L8N_VREF_0|UNUSED||0||||||||| +A7||IOBS|IO_L10N_0|UNUSED||0||||||||| +A8||IOBS|IO_L33N_0|UNUSED||0||||||||| +A9||IOBS|IO_L35N_GCLK16_0|UNUSED||0||||||||| +A10||IOBS|IO_L37N_GCLK12_0|UNUSED||0||||||||| +A11||IOBS|IO_L39N_0|UNUSED||0||||||||| +A12||IOBS|IO_L41N_0|UNUSED||0||||||||| +A13||IOBS|IO_L50N_0|UNUSED||0||||||||| +A14||IOBS|IO_L62N_VREF_0|UNUSED||0||||||||| +A15||IOBS|IO_L64N_SCP4_0|UNUSED||0||||||||| +A16||IOBS|IO_L66N_SCP0_0|UNUSED||0||||||||| +A17|||TCK|||||||||||| +A18|||GND|||||||||||| +B1|||VCCAUX||||||||2.5|||| +B2||IOBM|IO_L2P_0|UNUSED||0||||||||| +B3||IOBM|IO_L4P_0|UNUSED||0||||||||| +B4|GPIO<5>|IOB|IO_L5P_0|INPUT|LVCMOS25*|0||||NONE||LOCATED|NO|NONE| +B5|||VCCO_0|||0|||||2.50|||| +B6||IOBM|IO_L8P_0|UNUSED||0||||||||| +B7|||GND|||||||||||| +B8||IOBM|IO_L33P_0|UNUSED||0||||||||| +B9||IOBM|IO_L35P_GCLK17_0|UNUSED||0||||||||| +B10|||VCCO_0|||0|||||2.50|||| +B11||IOBM|IO_L39P_0|UNUSED||0||||||||| +B12||IOBM|IO_L41P_0|UNUSED||0||||||||| +B13|||GND|||||||||||| +B14||IOBM|IO_L62P_0|UNUSED||0||||||||| +B15|||VCCO_0|||0|||||2.50|||| +B16||IOBM|IO_L66P_SCP1_0|UNUSED||0||||||||| +B17|||VCCAUX||||||||2.5|||| +B18|||TMS|||||||||||| +C1||IOBS|IO_L83N_VREF_3|UNUSED||3||||||||| +C2||IOBM|IO_L83P_3|UNUSED||3||||||||| +C3|||GND|||||||||||| +C4||IOBS|IO_L1N_VREF_0|UNUSED||0||||||||| +C5||IOBM|IO_L6P_0|UNUSED||0||||||||| +C6||IOBS|IO_L3N_0|UNUSED||0||||||||| +C7||IOBM|IO_L10P_0|UNUSED||0||||||||| +C8||IOBS|IO_L11N_0|UNUSED||0||||||||| +C9||IOBS|IO_L34N_GCLK18_0|UNUSED||0||||||||| +C10||IOBM|IO_L37P_GCLK13_0|UNUSED||0||||||||| +C11||IOBS|IO_L36N_GCLK14_0|UNUSED||0||||||||| +C12||IOBS|IO_L47N_0|UNUSED||0||||||||| +C13||IOBM|IO_L50P_0|UNUSED||0||||||||| +C14||IOBS|IO_L65N_SCP2_0|UNUSED||0||||||||| +C15||IOBM|IO_L64P_SCP5_0|UNUSED||0||||||||| +C16|||GND|||||||||||| +C17||IOBM|IO_L29P_A23_M1A13_1|UNUSED||1||||||||| +C18||IOBS|IO_L29N_A22_M1A14_1|UNUSED||1||||||||| +D1||IOBS|IO_L52N_M3A9_3|UNUSED||3||||||||| +D2||IOBM|IO_L52P_M3A8_3|UNUSED||3||||||||| +D3||IOBS|IO_L54N_M3A11_3|UNUSED||3||||||||| +D4||IOBM|IO_L1P_HSWAPEN_0|UNUSED||0||||||||| +D5|||GND|||||||||||| +D6||IOBM|IO_L3P_0|UNUSED||0||||||||| +D7|||VCCO_0|||0|||||2.50|||| +D8||IOBM|IO_L11P_0|UNUSED||0||||||||| +D9||IOBM|IO_L34P_GCLK19_0|UNUSED||0||||||||| +D10|||GND|||||||||||| +D11||IOBM|IO_L36P_GCLK15_0|UNUSED||0||||||||| +D12||IOBM|IO_L47P_0|UNUSED||0||||||||| +D13|||VCCO_0|||0|||||2.50|||| +D14|DIPSW<0>|IOB|IO_L65P_SCP3_0|INPUT|LVCMOS25*|0||||NONE||LOCATED|NO|NONE| +D15|||TDI|||||||||||| +D16|||TDO|||||||||||| +D17||IOBM|IO_L31P_A19_M1CKE_1|UNUSED||1||||||||| +D18||IOBS|IO_L31N_A18_M1A12_1|UNUSED||1||||||||| +E1||IOBS|IO_L50N_M3BA2_3|UNUSED||3||||||||| +E2|||VCCO_3|||3|||||any******|||| +E3||IOBM|IO_L50P_M3WE_3|UNUSED||3||||||||| +E4|BUT<2>|IOB|IO_L54P_M3RESET_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE| +E5|||VCCAUX||||||||2.5|||| +E6||IOBS|IO_L7N_0|UNUSED||0||||||||| +E7||IOBM|IO_L9P_0|UNUSED||0||||||||| +E8||IOBS|IO_L9N_0|UNUSED||0||||||||| +E9|||VCCAUX||||||||2.5|||| +E10|||VCCO_0|||0|||||2.50|||| +E11||IOBS|IO_L42N_0|UNUSED||0||||||||| +E12|DIPSW<1>|IOB|IO_L51N_0|INPUT|LVCMOS25*|0||||NONE||LOCATED|NO|NONE| +E13||IOBS|IO_L63N_SCP6_0|UNUSED||0||||||||| +E14|||VCCAUX||||||||2.5|||| +E15|||GND|||||||||||| +E16||IOBM|IO_L33P_A15_M1A10_1|UNUSED||1||||||||| +E17|||VCCO_1|||1|||||2.50|||| +E18||IOBS|IO_L33N_A14_M1A4_1|UNUSED||1||||||||| +F1||IOBS|IO_L48N_M3BA1_3|UNUSED||3||||||||| +F2||IOBM|IO_L48P_M3BA0_3|UNUSED||3||||||||| +F3||IOBS|IO_L51N_M3A4_3|UNUSED||3||||||||| +F4||IOBM|IO_L51P_M3A10_3|UNUSED||3||||||||| +F5|BUT<3>|IOB|IO_L55N_M3A14_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE| +F6|BUT<1>|IOB|IO_L55P_M3A13_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE| +F7||IOBM|IO_L7P_0|UNUSED||0||||||||| +F8||IOBS|IO_L32N_0|UNUSED||0||||||||| +F9||IOBS|IO_L38N_VREF_0|UNUSED||0||||||||| +F10||IOBS|IO_L40N_0|UNUSED||0||||||||| +F11||IOBM|IO_L42P_0|UNUSED||0||||||||| +F12|DIPSW<2>|IOB|IO_L51P_0|INPUT|LVCMOS25*|0||||NONE||LOCATED|NO|NONE| +F13|GPIO<6>|IOB|IO_L63P_SCP7_0|INPUT|LVCMOS25*|0||||NONE||LOCATED|NO|NONE| +F14||IOBM|IO_L30P_A21_M1RESET_1|UNUSED||1||||||||| +F15|GPIO<4>|IOB|IO_L1P_A25_1|INPUT|LVCMOS25*|1||||NONE||LOCATED|NO|NONE| +F16||IOBS|IO_L1N_A24_VREF_1|UNUSED||1||||||||| +F17||IOBM|IO_L35P_A11_M1A7_1|UNUSED||1||||||||| +F18||IOBS|IO_L35N_A10_M1A2_1|UNUSED||1||||||||| +G1||IOBS|IO_L46N_M3CLKN_3|UNUSED||3||||||||| +G2|||GND|||||||||||| +G3||IOBM|IO_L46P_M3CLK_3|UNUSED||3||||||||| +G4|||VCCO_3|||3|||||any******|||| +G5|||GND|||||||||||| +G6||IOBS|IO_L53N_M3A12_3|UNUSED||3||||||||| +G7|||VCCINT||||||||1.2|||| +G8||IOBM|IO_L32P_0|UNUSED||0||||||||| +G9||IOBM|IO_L38P_0|UNUSED||0||||||||| +G10|||VCCAUX||||||||2.5|||| +G11||IOBM|IO_L40P_0|UNUSED||0||||||||| +G12|||GND|||||||||||| +G13||IOBS|IO_L32N_A16_M1A9_1|UNUSED||1||||||||| +G14||IOBS|IO_L30N_A20_M1A11_1|UNUSED||1||||||||| +G15|||VCCO_1|||1|||||2.50|||| +G16||IOBM|IO_L38P_A5_M1CLK_1|UNUSED||1||||||||| +G17|||GND|||||||||||| +G18||IOBS|IO_L38N_A4_M1CLKN_1|UNUSED||1||||||||| +H1||IOBS|IO_L41N_GCLK26_M3DQ5_3|UNUSED||3||||||||| +H2||IOBM|IO_L41P_GCLK27_M3DQ4_3|UNUSED||3||||||||| +H3||IOBS|IO_L44N_GCLK20_M3A6_3|UNUSED||3||||||||| +H4||IOBM|IO_L44P_GCLK21_M3A5_3|UNUSED||3||||||||| +H5||IOBS|IO_L49N_M3A2_3|UNUSED||3||||||||| +H6||IOBM|IO_L49P_M3A7_3|UNUSED||3||||||||| +H7||IOBM|IO_L53P_M3CKE_3|UNUSED||3||||||||| +H8|||GND|||||||||||| +H9|||VCCINT||||||||1.2|||| +H10|||GND|||||||||||| +H11|||VCCINT||||||||1.2|||| +H12||IOBM|IO_L32P_A17_M1A8_1|UNUSED||1||||||||| +H13||IOBM|IO_L36P_A9_M1BA0_1|UNUSED||1||||||||| +H14||IOBS|IO_L36N_A8_M1BA1_1|UNUSED||1||||||||| +H15||IOBM|IO_L37P_A7_M1A0_1|UNUSED||1||||||||| +H16||IOBS|IO_L37N_A6_M1A1_1|UNUSED||1||||||||| +H17||IOBM|IO_L43P_GCLK5_M1DQ4_1|UNUSED||1||||||||| +H18||IOBS|IO_L43N_GCLK4_M1DQ5_1|UNUSED||1||||||||| +J1||IOBS|IO_L40N_M3DQ7_3|UNUSED||3||||||||| +J2|||VCCO_3|||3|||||any******|||| +J3||IOBM|IO_L40P_M3DQ6_3|UNUSED||3||||||||| +J4|||GND|||||||||||| +J5|||VCCO_3|||3|||||any******|||| +J6||IOBS|IO_L47N_M3A1_3|UNUSED||3||||||||| +J7||IOBM|IO_L47P_M3A0_3|UNUSED||3||||||||| +J8|||VCCINT||||||||1.2|||| +J9|||GND|||||||||||| +J10|||VCCINT||||||||1.2|||| +J11|||GND|||||||||||| +J12|||VCCAUX||||||||2.5|||| +J13||IOBM|IO_L39P_M1A3_1|UNUSED||1||||||||| +J14|||VCCO_1|||1|||||2.50|||| +J15|||GND|||||||||||| +J16||IOBM|IO_L44P_A3_M1DQ6_1|UNUSED||1||||||||| +J17|||VCCO_1|||1|||||2.50|||| +J18||IOBS|IO_L44N_A2_M1DQ7_1|UNUSED||1||||||||| +K1||IOBS|IO_L38N_M3DQ3_3|UNUSED||3||||||||| +K2||IOBM|IO_L38P_M3DQ2_3|UNUSED||3||||||||| +K3||IOBS|IO_L42N_GCLK24_M3LDM_3|UNUSED||3||||||||| +K4||IOBM|IO_L42P_GCLK25_TRDY2_M3UDM_3|UNUSED||3||||||||| +K5||IOBS|IO_L43N_GCLK22_IRDY2_M3CASN_3|UNUSED||3||||||||| +K6||IOBS|IO_L45N_M3ODT_3|UNUSED||3||||||||| +K7|||VCCAUX||||||||2.5|||| +K8|||GND|||||||||||| +K9|||VCCINT||||||||1.2|||| +K10|||GND|||||||||||| +K11|||VCCINT||||||||1.2|||| +K12||IOBM|IO_L34P_A13_M1WE_1|UNUSED||1||||||||| +K13||IOBS|IO_L34N_A12_M1BA2_1|UNUSED||1||||||||| +K14||IOBS|IO_L39N_M1ODT_1|UNUSED||1||||||||| +K15||IOBM|IO_L41P_GCLK9_IRDY1_M1RASN_1|UNUSED||1||||||||| +K16||IOBS|IO_L41N_GCLK8_M1CASN_1|UNUSED||1||||||||| +K17||IOBM|IO_L45P_A1_M1LDQS_1|UNUSED||1||||||||| +K18||IOBS|IO_L45N_A0_M1LDQSN_1|UNUSED||1||||||||| +L1||IOBS|IO_L37N_M3DQ1_3|UNUSED||3||||||||| +L2||IOBM|IO_L37P_M3DQ0_3|UNUSED||3||||||||| +L3||IOBS|IO_L39N_M3LDQSN_3|UNUSED||3||||||||| +L4||IOBM|IO_L39P_M3LDQS_3|UNUSED||3||||||||| +L5||IOBM|IO_L43P_GCLK23_M3RASN_3|UNUSED||3||||||||| +L6||IOBM|IO_L31P_3|UNUSED||3||||||||| +L7||IOBM|IO_L45P_M3A3_3|UNUSED||3||||||||| +L8|||VCCINT||||||||1.2|||| +L9|||GND|||||||||||| +L10|||VCCINT||||||||1.2|||| +L11|||GND|||||||||||| +L12||IOBM|IO_L40P_GCLK11_M1A5_1|UNUSED||1||||||||| +L13||IOBS|IO_L40N_GCLK10_M1A6_1|UNUSED||1||||||||| +L14||IOBM|IO_L61P_1|UNUSED||1||||||||| +L15|GPIO<3>|IOB|IO_L42P_GCLK7_M1UDM_1|INPUT|LVCMOS25*|1||||NONE||LOCATED|NO|NONE| +L16||IOBS|IO_L42N_GCLK6_TRDY1_M1LDM_1|UNUSED||1||||||||| +L17||IOBM|IO_L46P_FCS_B_M1DQ2_1|UNUSED||1||||||||| +L18||IOBS|IO_L46N_FOE_B_M1DQ3_1|UNUSED||1||||||||| +M1||IOBS|IO_L36N_M3DQ9_3|UNUSED||3||||||||| +M2|||GND|||||||||||| +M3||IOBM|IO_L36P_M3DQ8_3|UNUSED||3||||||||| +M4|||VCCO_3|||3|||||any******|||| +M5||IOBS|IO_L31N_VREF_3|UNUSED||3||||||||| +M6|||GND|||||||||||| +M7|||VCCINT||||||||1.2|||| +M8||IOBM|IO_L40P_2|UNUSED||2||||||||| +M9|||VCCAUX||||||||2.5|||| +M10||IOBM|IO_L22P_2|UNUSED||2||||||||| +M11||IOBM|IO_L15P_2|UNUSED||2||||||||| +M12|||VCCINT||||||||1.2|||| +M13||IOBS|IO_L61N_1|UNUSED||1||||||||| +M14||IOBM|IO_L53P_1|UNUSED||1||||||||| +M15|||VCCO_1|||1|||||2.50|||| +M16||IOBM|IO_L47P_FWE_B_M1DQ0_1|UNUSED||1||||||||| +M17|||GND|||||||||||| +M18|GPIO<1>|IOB|IO_L47N_LDC_M1DQ1_1|OUTPUT|LVCMOS25*|1|12|SLOW||||LOCATED|NO|NONE| +N1||IOBS|IO_L35N_M3DQ11_3|UNUSED||3||||||||| +N2||IOBM|IO_L35P_M3DQ10_3|UNUSED||3||||||||| +N3||IOBS|IO_L1N_VREF_3|UNUSED||3||||||||| +N4||IOBM|IO_L1P_3|UNUSED||3||||||||| +N5||IOBM|IO_L64P_D8_2|UNUSED||2||||||||| +N6||IOBM|IO_L47P_2|UNUSED||2||||||||| +N7||IOBM|IO_L44P_2|UNUSED||2||||||||| +N8||IOBS|IO_L40N_2|UNUSED||2||||||||| +N9||IOBS|IO_L22N_2|UNUSED||2||||||||| +N10||IOBM|IO_L20P_2|UNUSED||2||||||||| +N11||IOBS|IO_L15N_2|UNUSED||2||||||||| +N12||IOBM|IO_L13P_M1_2|UNUSED||2||||||||| +N13|||GND|||||||||||| +N14||IOBS|IO_L53N_VREF_1|UNUSED||1||||||||| +N15||IOBM|IO_L50P_M1UDQS_1|UNUSED||1||||||||| +N16||IOBS|IO_L50N_M1UDQSN_1|UNUSED||1||||||||| +N17|GPIO<0>|IOB|IO_L48P_HDC_M1DQ8_1|OUTPUT|LVCMOS25*|1|12|SLOW||||LOCATED|NO|NONE| +N18||IOBS|IO_L48N_M1DQ9_1|UNUSED||1||||||||| +P1||IOBS|IO_L34N_M3UDQSN_3|UNUSED||3||||||||| +P2||IOBM|IO_L34P_M3UDQS_3|UNUSED||3||||||||| +P3||IOBS|IO_L2N_3|UNUSED||3||||||||| +P4|BUT<0>|IOB|IO_L2P_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE| +P5|||VCCAUX||||||||2.5|||| +P6||IOBS|IO_L64N_D9_2|UNUSED||2||||||||| +P7||IOBS|IO_L47N_2|UNUSED||2||||||||| +P8||IOBS|IO_L44N_2|UNUSED||2||||||||| +P9|||VCCO_2|||2|||||any******|||| +P10|||VCCAUX||||||||2.5|||| +P11||IOBS|IO_L20N_2|UNUSED||2||||||||| +P12|GPIO<7>|IOB|IO_L13N_D10_2|INPUT|LVCMOS25*|2||||NONE||LOCATED|NO|NONE| +P13|||CMPCS_B_2|||||||||||| +P14|||VCCAUX||||||||2.5|||| +P15||IOBM|IO_L74P_AWAKE_1|UNUSED||1||||||||| +P16||IOBS|IO_L74N_DOUT_BUSY_1|UNUSED||1||||||||| +P17||IOBM|IO_L49P_M1DQ10_1|UNUSED||1||||||||| +P18||IOBS|IO_L49N_M1DQ11_1|UNUSED||1||||||||| +R1|||GND|||||||||||| +R2|||VCCO_3|||3|||||any******|||| +R3||IOBM|IO_L62P_D5_2|UNUSED||2||||||||| +R4|||GND|||||||||||| +R5||IOBM|IO_L48P_D7_2|UNUSED||2||||||||| +R6|||VCCO_2|||2|||||any******|||| +R7||IOBM|IO_L46P_2|UNUSED||2||||||||| +R8||IOBM|IO_L31P_GCLK31_D14_2|UNUSED||2||||||||| +R9|||GND|||||||||||| +R10||IOBM|IO_L29P_GCLK3_2|UNUSED||2||||||||| +R11||IOBM|IO_L16P_2|UNUSED||2||||||||| +R12|||VCCO_2|||2|||||any******|||| +R13||IOBM|IO_L3P_D0_DIN_MISO_MISO1_2|UNUSED||2||||||||| +R14|||GND|||||||||||| +R15||IOBM|IO_L1P_CCLK_2|UNUSED||2||||||||| +R16|||SUSPEND|||||||||||| +R17|||VCCO_1|||1|||||2.50|||| +R18|||GND|||||||||||| +T1||IOBS|IO_L33N_M3DQ13_3|UNUSED||3||||||||| +T2||IOBM|IO_L33P_M3DQ12_3|UNUSED||3||||||||| +T3||IOBS|IO_L62N_D6_2|UNUSED||2||||||||| +T4||IOBM|IO_L63P_2|UNUSED||2||||||||| +T5||IOBS|IO_L48N_RDWR_B_VREF_2|UNUSED||2||||||||| +T6||IOBM|IO_L45P_2|UNUSED||2||||||||| +T7||IOBS|IO_L46N_2|UNUSED||2||||||||| +T8||IOBS|IO_L31N_GCLK30_D15_2|UNUSED||2||||||||| +T9||IOBM|IO_L32P_GCLK29_2|UNUSED||2||||||||| +T10||IOBS|IO_L29N_GCLK2_2|UNUSED||2||||||||| +T11||IOBS|IO_L16N_VREF_2|UNUSED||2||||||||| +T12||IOBM|IO_L19P_2|UNUSED||2||||||||| +T13||IOBS|IO_L3N_MOSI_CSI_B_MISO0_2|UNUSED||2||||||||| +T14||IOBM|IO_L12P_D1_MISO2_2|UNUSED||2||||||||| +T15||IOBS|IO_L1N_M0_CMPMISO_2|UNUSED||2||||||||| +T16|||GND|||||||||||| +T17||IOBM|IO_L51P_M1DQ12_1|UNUSED||1||||||||| +T18||IOBS|IO_L51N_M1DQ13_1|UNUSED||1||||||||| +U1||IOBS|IO_L32N_M3DQ15_3|UNUSED||3||||||||| +U2||IOBM|IO_L32P_M3DQ14_3|UNUSED||3||||||||| +U3||IOBM|IO_L65P_INIT_B_2|UNUSED||2||||||||| +U4|||VCCO_2|||2|||||any******|||| +U5||IOBM|IO_L49P_D3_2|UNUSED||2||||||||| +U6|||GND|||||||||||| +U7||IOBM|IO_L43P_2|UNUSED||2||||||||| +U8||IOBM|IO_L41P_2|UNUSED||2||||||||| +U9|||VCCO_2|||2|||||any******|||| +U10||IOBM|IO_L30P_GCLK1_D13_2|UNUSED||2||||||||| +U11||IOBM|IO_L23P_2|UNUSED||2||||||||| +U12|||GND|||||||||||| +U13||IOBM|IO_L14P_D11_2|UNUSED||2||||||||| +U14|||VCCO_2|||2|||||any******|||| +U15||IOBM|IO_L5P_2|UNUSED||2||||||||| +U16||IOBM|IO_L2P_CMPCLK_2|UNUSED||2||||||||| +U17||IOBM|IO_L52P_M1DQ14_1|UNUSED||1||||||||| +U18||IOBS|IO_L52N_M1DQ15_1|UNUSED||1||||||||| +V1|||GND|||||||||||| +V2|||PROGRAM_B_2|||||||||||| +V3||IOBS|IO_L65N_CSO_B_2|UNUSED||2||||||||| +V4||IOBS|IO_L63N_2|UNUSED||2||||||||| +V5||IOBS|IO_L49N_D4_2|UNUSED||2||||||||| +V6||IOBS|IO_L45N_2|UNUSED||2||||||||| +V7||IOBS|IO_L43N_2|UNUSED||2||||||||| +V8||IOBS|IO_L41N_VREF_2|UNUSED||2||||||||| +V9||IOBS|IO_L32N_GCLK28_2|UNUSED||2||||||||| +V10|CLK27MHz|IOB|IO_L30N_GCLK0_USERCCLK_2|INPUT|LVCMOS25*|2||||NONE||LOCATED|NO|NONE| +V11||IOBS|IO_L23N_2|UNUSED||2||||||||| +V12||IOBS|IO_L19N_2|UNUSED||2||||||||| +V13|DIPSW<3>|IOB|IO_L14N_D12_2|INPUT|LVCMOS25*|2||||NONE||LOCATED|NO|NONE| +V14||IOBS|IO_L12N_D2_MISO3_2|UNUSED||2||||||||| +V15||IOBS|IO_L5N_2|UNUSED||2||||||||| +V16||IOBS|IO_L2N_CMPMOSI_2|UNUSED||2||||||||| +V17|||DONE_2|||||||||||| +V18|||GND|||||||||||| + +-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----| + +* Default value. +** This default Pullup/Pulldown value can be overridden in Bitgen. +****** Special VCCO requirements may apply. Please consult the device + family datasheet for specific guideline on VCCO requirements. + + diff --git a/textovhdl.par b/textovhdl.par new file mode 100644 index 0000000..6f64ebc --- /dev/null +++ b/textovhdl.par @@ -0,0 +1,195 @@ +Release 14.7 par P.20131013 (nt64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +GABRIEL-E5400:: Wed Jun 08 11:35:46 2022 + +par -w -intstyle ise -ol high -mt off textovhdl_map.ncd textovhdl.ncd +textovhdl.pcf + + +Constraints file: textovhdl.pcf. +Loading device for application Rf_Device from file '6slx16.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\. + "textovhdl" is an NCD, version 3.2, device xc6slx16, package csg324, speed -2 + +Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) +Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) + +INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par + -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all + internal clocks in this design. Because there are not defined timing requirements, a timing score will not be + reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. + Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". + +Device speed data version: "PRODUCTION 1.23 2013-10-13". + + + +Device Utilization Summary: + +Slice Logic Utilization: + Number of Slice Registers: 32 out of 18,224 1% + Number used as Flip Flops: 32 + Number used as Latches: 0 + Number used as Latch-thrus: 0 + Number used as AND/OR logics: 0 + Number of Slice LUTs: 31 out of 9,112 1% + Number used as logic: 29 out of 9,112 1% + Number using O6 output only: 14 + Number using O5 output only: 11 + Number using O5 and O6: 4 + Number used as ROM: 0 + Number used as Memory: 0 out of 2,176 0% + Number used exclusively as route-thrus: 2 + Number with same-slice register load: 0 + Number with same-slice carry load: 2 + Number with other load: 0 + +Slice Logic Distribution: + Number of occupied Slices: 11 out of 2,278 1% + Number of MUXCYs used: 20 out of 4,556 1% + Number of LUT Flip Flop pairs used: 31 + Number with an unused Flip Flop: 1 out of 31 3% + Number with an unused LUT: 0 out of 31 0% + Number of fully used LUT-FF pairs: 30 out of 31 96% + Number of slice register sites lost + to control set restrictions: 0 out of 18,224 0% + + A LUT Flip Flop pair for this architecture represents one LUT paired with + one Flip Flop within a slice. A control set is a unique combination of + clock, reset, set, and enable signals for a registered element. + The Slice Logic Distribution report is not meaningful if the design is + over-mapped for a non-slice resource or if Placement fails. + +IO Utilization: + Number of bonded IOBs: 17 out of 232 7% + Number of LOCed IOBs: 17 out of 17 100% + +Specific Feature Utilization: + Number of RAMB16BWERs: 0 out of 32 0% + Number of RAMB8BWERs: 0 out of 64 0% + Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0% + Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0% + Number of BUFG/BUFGMUXs: 2 out of 16 12% + Number used as BUFGs: 2 + Number used as BUFGMUX: 0 + Number of DCM/DCM_CLKGENs: 0 out of 4 0% + Number of ILOGIC2/ISERDES2s: 0 out of 248 0% + Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 248 0% + Number of OLOGIC2/OSERDES2s: 0 out of 248 0% + Number of BSCANs: 0 out of 4 0% + Number of BUFHs: 0 out of 128 0% + Number of BUFPLLs: 0 out of 8 0% + Number of BUFPLL_MCBs: 0 out of 4 0% + Number of DSP48A1s: 0 out of 32 0% + Number of ICAPs: 0 out of 1 0% + Number of MCBs: 0 out of 2 0% + Number of PCILOGICSEs: 0 out of 2 0% + Number of PLL_ADVs: 0 out of 2 0% + Number of PMVs: 0 out of 1 0% + Number of STARTUPs: 0 out of 1 0% + Number of SUSPEND_SYNCs: 0 out of 1 0% + + +Overall effort level (-ol): High +Router effort level (-rl): High + +Starting initial Timing Analysis. REAL time: 4 secs +Finished initial Timing Analysis. REAL time: 4 secs + +WARNING:Par:288 - The signal BUT<2>_IBUF has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal BUT<3>_IBUF has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal GPIO<3>_IBUF has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal GPIO<4>_IBUF has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal GPIO<5>_IBUF has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal GPIO<6>_IBUF has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal GPIO<7>_IBUF has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal DIPSW<0>_IBUF has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal DIPSW<1>_IBUF has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal DIPSW<2>_IBUF has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal DIPSW<3>_IBUF has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal BUT<0>_IBUF has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal BUT<1>_IBUF has no load. PAR will not attempt to route this signal. +Starting Router + + +Phase 1 : 119 unrouted; REAL time: 4 secs + +Phase 2 : 93 unrouted; REAL time: 4 secs + +Phase 3 : 4 unrouted; REAL time: 4 secs + +Phase 4 : 4 unrouted; (Par is working to improve performance) REAL time: 5 secs + +Updating file: textovhdl.ncd with current fully routed design. + +Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 5 secs + +Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 5 secs + +Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 5 secs + +Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 5 secs + +Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 5 secs + +Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 5 secs +Total REAL time to Router completion: 5 secs +Total CPU time to Router completion: 5 secs + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +Generating "PAR" statistics. +INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode. +Timing Score: 0 (Setup: 0, Hold: 0) + +Asterisk (*) preceding a constraint indicates it was not met. + This may be due to a setup or hold violation. + +---------------------------------------------------------------------------------------------------------- + Constraint | Check | Worst Case | Best Case | Timing | Timing + | | Slack | Achievable | Errors | Score +---------------------------------------------------------------------------------------------------------- + Autotimespec constraint for clock net con | SETUP | N/A| 1.993ns| N/A| 0 + taux_5_BUFG | HOLD | 0.463ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + Autotimespec constraint for clock net CLK | SETUP | N/A| 1.805ns| N/A| 0 + 27MHz_BUFGP | HOLD | 0.530ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + + +All constraints were met. +INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the + constraint is not analyzed due to the following: No paths covered by this + constraint; Other constraints intersect with this constraint; or This + constraint was disabled by a Path Tracing Control. Please run the Timespec + Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI. + + +Generating Pad Report. + +All signals are completely routed. + +WARNING:Par:283 - There are 13 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. + +Total REAL time to PAR completion: 6 secs +Total CPU time to PAR completion: 6 secs + +Peak Memory Usage: 305 MB + +Placer: Placement generated during map. +Routing: Completed - No errors found. + +Number of error messages: 0 +Number of warning messages: 15 +Number of info messages: 2 + +Writing design to file textovhdl.ncd + + + +PAR done! diff --git a/textovhdl.pcf b/textovhdl.pcf new file mode 100644 index 0000000..dc801f5 --- /dev/null +++ b/textovhdl.pcf @@ -0,0 +1,28 @@ +//! ************************************************************************** +// Written by: Map P.20131013 on Wed Jun 08 11:35:43 2022 +//! ************************************************************************** + +SCHEMATIC START; +COMP "BUT<2>" LOCATE = SITE "E4" LEVEL 1; +COMP "BUT<3>" LOCATE = SITE "F5" LEVEL 1; +COMP "GPIO<0>" LOCATE = SITE "N17" LEVEL 1; +COMP "GPIO<1>" LOCATE = SITE "M18" LEVEL 1; +COMP "GPIO<2>" LOCATE = SITE "A3" LEVEL 1; +COMP "GPIO<3>" LOCATE = SITE "L15" LEVEL 1; +COMP "GPIO<4>" LOCATE = SITE "F15" LEVEL 1; +PIN GPIO<4>_pin<0> = BEL "GPIO<4>" PINNAME PAD; +PIN "GPIO<4>_pin<0>" CLOCK_DEDICATED_ROUTE = FALSE; +COMP "GPIO<5>" LOCATE = SITE "B4" LEVEL 1; +COMP "GPIO<6>" LOCATE = SITE "F13" LEVEL 1; +PIN GPIO<6>_pin<0> = BEL "GPIO<6>" PINNAME PAD; +PIN "GPIO<6>_pin<0>" CLOCK_DEDICATED_ROUTE = FALSE; +COMP "GPIO<7>" LOCATE = SITE "P12" LEVEL 1; +COMP "DIPSW<0>" LOCATE = SITE "D14" LEVEL 1; +COMP "DIPSW<1>" LOCATE = SITE "E12" LEVEL 1; +COMP "CLK27MHz" LOCATE = SITE "V10" LEVEL 1; +COMP "DIPSW<2>" LOCATE = SITE "F12" LEVEL 1; +COMP "DIPSW<3>" LOCATE = SITE "V13" LEVEL 1; +COMP "BUT<0>" LOCATE = SITE "P4" LEVEL 1; +COMP "BUT<1>" LOCATE = SITE "F6" LEVEL 1; +SCHEMATIC END; + diff --git a/textovhdl.prj b/textovhdl.prj new file mode 100644 index 0000000..e936010 --- /dev/null +++ b/textovhdl.prj @@ -0,0 +1 @@ +vhdl work "textovhdl.vhd" diff --git a/textovhdl.ptwx b/textovhdl.ptwx new file mode 100644 index 0000000..920341b --- /dev/null +++ b/textovhdl.ptwx @@ -0,0 +1,332 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +]> +Autotimespec constraint for clock net contaux_5_BUFGAutotimespec constraint for clock net CLK27MHz_BUFGP0INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI. diff --git a/textovhdl.stx b/textovhdl.stx new file mode 100644 index 0000000..e69de29 diff --git a/textovhdl.syr b/textovhdl.syr new file mode 100644 index 0000000..11bc1f3 --- /dev/null +++ b/textovhdl.syr @@ -0,0 +1,516 @@ +Release 14.7 - xst P.20131013 (nt64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +--> Parameter TMPDIR set to xst/projnav.tmp + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.13 secs + +--> Parameter xsthdpdir set to xst + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.13 secs + +--> Reading design: textovhdl.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Parsing + 3) HDL Elaboration + 4) HDL Synthesis + 4.1) HDL Synthesis Report + 5) Advanced HDL Synthesis + 5.1) Advanced HDL Synthesis Report + 6) Low Level Synthesis + 7) Partition Report + 8) Design Summary + 8.1) Primitive and Black Box Usage + 8.2) Device utilization summary + 8.3) Partition Resource Summary + 8.4) Timing Report + 8.4.1) Clock Information + 8.4.2) Asynchronous Control Signals Information + 8.4.3) Timing Summary + 8.4.4) Timing Details + 8.4.5) Cross Clock Domains Report + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "textovhdl.prj" +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "textovhdl" +Output Format : NGC +Target Device : xc6slx16-2-csg324 + +---- Source Options +Top Module Name : textovhdl +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +Safe Implementation : No +FSM Style : LUT +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +Shift Register Extraction : YES +ROM Style : Auto +Resource Sharing : YES +Asynchronous To Synchronous : NO +Shift Register Minimum Size : 2 +Use DSP Block : Auto +Automatic Register Balancing : No + +---- Target Options +LUT Combining : Auto +Reduce Control Sets : Auto +Add IO Buffers : YES +Global Maximum Fanout : 100000 +Add Generic Clock Buffer(BUFG) : 16 +Register Duplication : YES +Optimize Instantiated Primitives : NO +Use Clock Enable : Auto +Use Synchronous Set : Auto +Use Synchronous Reset : Auto +Pack IO Registers into IOBs : Auto +Equivalent register Removal : YES + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Power Reduction : NO +Keep Hierarchy : No +Netlist Hierarchy : As_Optimized +RTL Output : Yes +Global Optimization : AllClockNets +Read Cores : YES +Write Timing Constraints : NO +Cross Clock Analysis : NO +Hierarchy Separator : / +Bus Delimiter : <> +Case Specifier : Maintain +Slice Utilization Ratio : 100 +BRAM Utilization Ratio : 100 +DSP48 Utilization Ratio : 100 +Auto BRAM Packing : NO +Slice Utilization Ratio Delta : 5 + +========================================================================= + + +========================================================================= +* HDL Parsing * +========================================================================= +Parsing VHDL file "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" into library work +Parsing entity . +Parsing architecture of entity . +Parsing entity . +Parsing architecture of entity . +Parsing entity . +Parsing architecture of entity . + +========================================================================= +* HDL Elaboration * +========================================================================= + +Elaborating entity (architecture ) from library . + +Elaborating entity (architecture ) from library . +WARNING:HDLCompiler:1127 - "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 64: Assignment to clk100k ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 65: Assignment to clk25k ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 66: Assignment to clk621ms ignored, since the identifier is never used +WARNING:HDLCompiler:634 - "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 20: Net does not have a driver. + +========================================================================= +* HDL Synthesis * +========================================================================= + +Synthesizing Unit . + Related source file is "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +Always blocking tristate driving signal > is removed. +Always blocking tristate driving signal > is removed. +Always blocking tristate driving signal > is removed. +Always blocking tristate driving signal > is removed. +Always blocking tristate driving signal > is removed. +Always blocking tristate driving signal > is removed. +Always blocking tristate driving signal > is removed. +Always blocking tristate driving signal > is removed. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Found 24-bit register for signal . + Found 24-bit adder for signal created at line 60. + Found 1-bit tristate buffer for signal > created at line 37 + Found 1-bit tristate buffer for signal > created at line 37 + Found 1-bit tristate buffer for signal > created at line 37 + Found 1-bit tristate buffer for signal > created at line 37 + Summary: + inferred 1 Adder/Subtractor(s). + inferred 24 D-type flip-flop(s). + inferred 4 Tristate(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd". + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 9-bit register for signal . + Found 9-bit adder for signal created at line 179. + Found 8x4-bit Read Only RAM for signal + Summary: + inferred 1 RAM(s). + inferred 1 Adder/Subtractor(s). + inferred 26 D-type flip-flop(s). + inferred 4 Multiplexer(s). +Unit synthesized. + +========================================================================= +HDL Synthesis Report + +Macro Statistics +# RAMs : 1 + 8x4-bit single-port Read Only RAM : 1 +# Adders/Subtractors : 2 + 24-bit adder : 1 + 9-bit adder : 1 +# Registers : 4 + 1-bit register : 1 + 16-bit register : 1 + 24-bit register : 1 + 9-bit register : 1 +# Multiplexers : 4 + 16-bit 2-to-1 multiplexer : 4 +# Tristates : 4 + 1-bit tristate buffer : 4 + +========================================================================= + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 8-word x 4-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +========================================================================= +Advanced HDL Synthesis Report + +Macro Statistics +# RAMs : 1 + 8x4-bit single-port distributed Read Only RAM : 1 +# Counters : 2 + 24-bit up counter : 1 + 9-bit up counter : 1 +# Registers : 17 + Flip-Flops : 17 +# Multiplexers : 4 + 16-bit 2-to-1 multiplexer : 4 + +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . + +Optimizing unit ... + +Optimizing unit ... + +Mapping all equations... +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block textovhdl, actual ratio is 0. + +Final Macro Processing ... + +========================================================================= +Final Register Report + +Macro Statistics +# Registers : 32 + Flip-Flops : 32 + +========================================================================= + +========================================================================= +* Partition Report * +========================================================================= + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +========================================================================= +* Design Summary * +========================================================================= + +Top Level Output File Name : textovhdl.ngc + +Primitive and Black Box Usage: +------------------------------ +# BELS : 64 +# GND : 1 +# INV : 4 +# LUT1 : 13 +# LUT2 : 5 +# LUT3 : 1 +# LUT4 : 1 +# LUT5 : 5 +# LUT6 : 5 +# MUXCY : 13 +# VCC : 1 +# XORCY : 15 +# FlipFlops/Latches : 32 +# FD : 15 +# FD_1 : 17 +# Clock Buffers : 2 +# BUFG : 1 +# BUFGP : 1 +# IO Buffers : 7 +# OBUF : 3 +# OBUFT : 4 + +Device utilization summary: +--------------------------- + +Selected Device : 6slx16csg324-2 + + +Slice Logic Utilization: + Number of Slice Registers: 32 out of 18224 0% + Number of Slice LUTs: 34 out of 9112 0% + Number used as Logic: 34 out of 9112 0% + +Slice Logic Distribution: + Number of LUT Flip Flop pairs used: 34 + Number with an unused Flip Flop: 2 out of 34 5% + Number with an unused LUT: 0 out of 34 0% + Number of fully used LUT-FF pairs: 32 out of 34 94% + Number of unique control sets: 3 + +IO Utilization: + Number of IOs: 21 + Number of bonded IOBs: 8 out of 232 3% + +Specific Feature Utilization: + Number of BUFG/BUFGCTRLs: 2 out of 16 12% + +--------------------------- +Partition Resource Summary: +--------------------------- + + No Partitions were found in this design. + +--------------------------- + + +========================================================================= +Timing Report + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +-----------------------------------+------------------------+-------+ +Clock Signal | Clock buffer(FF name) | Load | +-----------------------------------+------------------------+-------+ +CLK27MHz | BUFGP | 6 | +contaux_5 | BUFG | 26 | +-----------------------------------+------------------------+-------+ + +Asynchronous Control Signals Information: +---------------------------------------- +No asynchronous control signals found in this design + +Timing Summary: +--------------- +Speed Grade: -2 + + Minimum period: 2.579ns (Maximum Frequency: 387.785MHz) + Minimum input arrival time before clock: No path found + Maximum output required time after clock: 5.607ns + Maximum combinational path delay: No path found + +Timing Details: +--------------- +All values displayed in nanoseconds (ns) + +========================================================================= +Timing constraint: Default period analysis for Clock 'CLK27MHz' + Clock period: 2.049ns (frequency: 488.043MHz) + Total number of paths / destination ports: 21 / 6 +------------------------------------------------------------------------- +Delay: 2.049ns (Levels of Logic = 7) + Source: contaux_0 (FF) + Destination: contaux_5 (FF) + Source Clock: CLK27MHz rising + Destination Clock: CLK27MHz rising + + Data Path: contaux_0 to contaux_5 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 1 0.525 0.681 contaux_0 (contaux_0) + INV:I->O 1 0.255 0.000 Mcount_contaux_lut<0>_INV_0 (Mcount_contaux_lut<0>) + MUXCY:S->O 1 0.215 0.000 Mcount_contaux_cy<0> (Mcount_contaux_cy<0>) + MUXCY:CI->O 1 0.023 0.000 Mcount_contaux_cy<1> (Mcount_contaux_cy<1>) + MUXCY:CI->O 1 0.023 0.000 Mcount_contaux_cy<2> (Mcount_contaux_cy<2>) + MUXCY:CI->O 1 0.023 0.000 Mcount_contaux_cy<3> (Mcount_contaux_cy<3>) + MUXCY:CI->O 0 0.023 0.000 Mcount_contaux_cy<4> (Mcount_contaux_cy<4>) + XORCY:CI->O 1 0.206 0.000 Mcount_contaux_xor<5> (Result<5>) + FD:D 0.074 contaux_5 + ---------------------------------------- + Total 2.049ns (1.368ns logic, 0.681ns route) + (66.8% logic, 33.2% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'contaux_5' + Clock period: 2.579ns (frequency: 387.785MHz) + Total number of paths / destination ports: 117 / 26 +------------------------------------------------------------------------- +Delay: 2.579ns (Levels of Logic = 6) + Source: UDISP/EN_4 (FF) + Destination: UDISP/EN_8 (FF) + Source Clock: contaux_5 falling + Destination Clock: contaux_5 falling + + Data Path: UDISP/EN_4 to UDISP/EN_8 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 18 0.525 1.235 UDISP/EN_4 (UDISP/EN_4) + LUT1:I0->O 1 0.254 0.000 UDISP/Mcount_EN_cy<4>_rt (UDISP/Mcount_EN_cy<4>_rt) + MUXCY:S->O 1 0.215 0.000 UDISP/Mcount_EN_cy<4> (UDISP/Mcount_EN_cy<4>) + MUXCY:CI->O 1 0.023 0.000 UDISP/Mcount_EN_cy<5> (UDISP/Mcount_EN_cy<5>) + MUXCY:CI->O 1 0.023 0.000 UDISP/Mcount_EN_cy<6> (UDISP/Mcount_EN_cy<6>) + MUXCY:CI->O 0 0.023 0.000 UDISP/Mcount_EN_cy<7> (UDISP/Mcount_EN_cy<7>) + XORCY:CI->O 1 0.206 0.000 UDISP/Mcount_EN_xor<8> (UDISP/Result<8>) + FD:D 0.074 UDISP/EN_8 + ---------------------------------------- + Total 2.579ns (1.344ns logic, 1.235ns route) + (52.1% logic, 47.9% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'contaux_5' + Total number of paths / destination ports: 2 / 2 +------------------------------------------------------------------------- +Offset: 5.607ns (Levels of Logic = 2) + Source: UDISP/EN_4 (FF) + Destination: GPIO<1> (PAD) + Source Clock: contaux_5 falling + + Data Path: UDISP/EN_4 to GPIO<1> + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 18 0.525 1.234 UDISP/EN_4 (UDISP/EN_4) + INV:I->O 1 0.255 0.681 UDISP/CS1_INV_0 (GPIO_1_OBUF) + OBUF:I->O 2.912 GPIO_1_OBUF (GPIO<1>) + ---------------------------------------- + Total 5.607ns (3.692ns logic, 1.915ns route) + (65.8% logic, 34.2% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK27MHz' + Total number of paths / destination ports: 1 / 1 +------------------------------------------------------------------------- +Offset: 4.162ns (Levels of Logic = 1) + Source: contaux_5 (FF) + Destination: GPIO<0> (PAD) + Source Clock: CLK27MHz rising + + Data Path: contaux_5 to GPIO<0> + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 2 0.525 0.725 contaux_5 (contaux_5) + OBUF:I->O 2.912 GPIO_0_OBUF (GPIO<0>) + ---------------------------------------- + Total 4.162ns (3.437ns logic, 0.725ns route) + (82.6% logic, 17.4% route) + +========================================================================= + +Cross Clock Domains Report: +-------------------------- + +Clock to Setup on destination clock CLK27MHz +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +CLK27MHz | 2.049| | | | +---------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock contaux_5 +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +contaux_5 | | | 2.579| | +---------------+---------+---------+---------+---------+ + +========================================================================= + + +Total REAL time to Xst completion: 6.00 secs +Total CPU time to Xst completion: 6.79 secs + +--> + +Total memory usage is 258824 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 32 ( 0 filtered) +Number of infos : 1 ( 0 filtered) + diff --git a/textovhdl.twr b/textovhdl.twr new file mode 100644 index 0000000..902cd6c --- /dev/null +++ b/textovhdl.twr @@ -0,0 +1,62 @@ +-------------------------------------------------------------------------------- +Release 14.7 Trace (nt64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 2 +-n 3 -fastpaths -xml textovhdl.twx textovhdl.ncd -o textovhdl.twr textovhdl.pcf +-ucf restricoes.ucf + +Design file: textovhdl.ncd +Physical constraint file: textovhdl.pcf +Device,package,speed: xc6slx16,csg324,C,-2 (PRODUCTION 1.23 2013-10-13) +Report level: verbose report + +Environment Variable Effect +-------------------- ------ +NONE No environment variables were set +-------------------------------------------------------------------------------- + +INFO:Timing:2698 - No timing constraints found, doing default enumeration. +INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612). +INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths + option. All paths that are not constrained will be reported in the + unconstrained paths section(s) of the report. +INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on + a 50 Ohm transmission line loading model. For the details of this model, + and for more information on accounting for different loading conditions, + please see the device datasheet. + + + +Data Sheet report: +----------------- +All values displayed in nanoseconds (ns) + +Clock CLK27MHz to Pad +------------+-----------------+------------+-----------------+------------+------------------+--------+ + |Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock | +Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase | +------------+-----------------+------------+-----------------+------------+------------------+--------+ +GPIO<0> | 9.967(R)| SLOW | 4.260(R)| FAST |CLK27MHz_BUFGP | 0.000| +------------+-----------------+------------+-----------------+------------+------------------+--------+ + +Clock to Setup on destination clock CLK27MHz +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +CLK27MHz | 1.805| | | | +---------------+---------+---------+---------+---------+ + + +Analysis completed Wed Jun 08 11:35:59 2022 +-------------------------------------------------------------------------------- + +Trace Settings: +------------------------- +Trace Settings + +Peak Memory Usage: 218 MB + + + diff --git a/textovhdl.twx b/textovhdl.twx new file mode 100644 index 0000000..acb8d4e --- /dev/null +++ b/textovhdl.twx @@ -0,0 +1,339 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +]> +Release 14.7 Trace (nt64)Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 2 +-n 3 -fastpaths -xml textovhdl.twx textovhdl.ncd -o textovhdl.twr textovhdl.pcf +-ucf restricoes.ucf + +textovhdl.ncdtextovhdl.ncdtextovhdl.pcftextovhdl.pcfxc6slx16C-2PRODUCTION 1.23 2013-10-1313INFO:Timing:2698 - No timing constraints found, doing default enumeration.INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.CLK27MHzCLK27MHzCLK27MHz1.805Wed Jun 08 11:35:59 2022 TraceTrace Settings + +Peak Memory Usage: 218 MB + diff --git a/textovhdl.unroutes b/textovhdl.unroutes new file mode 100644 index 0000000..5bf816c --- /dev/null +++ b/textovhdl.unroutes @@ -0,0 +1,25 @@ +Release 14.7 - par P.20131013 (nt64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +Wed Jun 08 11:35:52 2022 + +All signals are completely routed. + +WARNING:ParHelpers:361 - There are 13 loadless signals in this design. This design will cause Bitgen to issue DRC + warnings. + + BUT<0>_IBUF + BUT<1>_IBUF + BUT<2>_IBUF + BUT<3>_IBUF + DIPSW<0>_IBUF + DIPSW<1>_IBUF + DIPSW<2>_IBUF + DIPSW<3>_IBUF + GPIO<3>_IBUF + GPIO<4>_IBUF + GPIO<5>_IBUF + GPIO<6>_IBUF + GPIO<7>_IBUF + + diff --git a/textovhdl.ut b/textovhdl.ut new file mode 100644 index 0000000..be56902 --- /dev/null +++ b/textovhdl.ut @@ -0,0 +1,30 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g CRC:Enable +-g Reset_on_err:No +-g ConfigRate:2 +-g ProgPin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g ExtMasterCclk_en:No +-g SPI_buswidth:1 +-g TIMER_CFG:0xFFFF +-g multipin_wakeup:No +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No +-g en_sw_gsr:No +-g drive_awake:No +-g sw_clk:Startupclk +-g sw_gwe_cycle:5 +-g sw_gts_cycle:4 diff --git a/textovhdl.vhd b/textovhdl.vhd index 350b16d..e711cc6 100644 --- a/textovhdl.vhd +++ b/textovhdl.vhd @@ -18,24 +18,6 @@ signal cont100k,contaux: std_logic_vector(23 downto 0); signal CLK100k,clk621ms,clk25k: std_logic; signal clkdisp,cs,din: std_logic; signal num7,num6,num5,num4,num3,num2,num1,num0: std_logic_vector(3 downto 0); -signal EO: std_logic_vector (7 downto 0); -signal S_IR, CLR_cont_S: std_logic; -signal prox_S, atual_S: std_logic_vector(1 downto 0); -signal Q1ms, Q4ms, Q8ms: std_logic; -signal proxshift, atualshift, codigo32: std_logic_vector(31 downto 0); -signal SIshift, ENshift: std_logic; -signal proxnum7: std_logic_vector( 3 downto 0); - -signal cont32TXIR: std_logic_vector(7 downto 0); -signal conttimeTXIR: std_logic_vector(11 downto 0); -signal clkcontbits, clrcontbits, contbitsigual32: std_logic; -signal EOTX8: std_logic_vector (1 downto 0); -signal EOTX12: std_logic_vector (2 downto 0); -signal clr12bits, Q900, Q450, Q55, Q165: std_logic; -signal loadshift, clkshift, Q0, outir, clk37915: std_logic; -signal proxTX, atualTX: std_logic_vector(3 downto 0); -signal proxshift32, atualshift32: std_logic_vector (31 downto 0); -signal cont37915: std_logic_vector(23 downto 0); component display port( NUM7, NUM6, NUM5, NUM4, NUM3, NUM2, NUM1, NUM0: in std_logic_vector(3 downto 0); CLK: in std_logic; @@ -54,56 +36,6 @@ begin GPIO <= "ZZZZZZZZ"; LEDS <= "ZZZZ"; ---contador 8 bits de transmissão, conta até 32 -UT0: CONTBCD_C port map(CLK => clkcontbits, CLR => clrcontbits, UP => '1', EN => '1', ENOUT => EOTX8(0), Q => cont32TXIR(3 downto 0)); -UT1: CONTBCD_C port map(CLK => clkcontbits, CLR => clrcontbits, UP => '1', EN => EOTX8(0), ENOUT => EOTX8(1), Q => cont32TXIR(7 downto 4)); -contbitsigual32 <= '1' when cont32TXIR="00110010" else '0'; - ---contador de 12 bits transmissão, conta até 900 x 10us -UT2: CONTBCD_C port map(CLK => clk100k, CLR => clr12bits, UP => '1', EN => '1', ENOUT => EOTX12(0), Q => conttimeTXIR(3 downto 0)); -UT3: CONTBCD_C port map(CLK => clk100k, CLR => clr12bits, UP => '1', EN => EOTX12(0), ENOUT => EOTX12(1), Q => conttimeTXIR(7 downto 4)); -UT4: CONTBCD_C port map(CLK => clk100k, CLR => clr12bits, UP => '1', EN => EOTX12(1), ENOUT => EOTX12(2), Q => conttimeTXIR(11 downto 8)); -Q900 <= '1' when conttimeTXIR(11 downto 8)="1001" else '0'; -Q450 <= '1' when conttimeTXIR(11 downto 4)="01000101" else '0'; -Q55 <= '1' when conttimeTXIR(7 downto 0)="01010101" else '0'; -Q165 <= '1' when conttimeTXIR="000101100101" else '0'; - ---shift register -proxshift32 <= codigo32 when loadshift='1' else '0'&atualshift32(31 downto 1); -Q0 <= atualshift32(0); - -process (clkshift) -begin - if (clkshift'event and clkshift='1') then - atualshift32 <=proxshift32; - end if; -end process; - - ---gera 37915Hz -process(CLK27MHz) -begin - if(CLK27MHz'event and CLK27MHz = '1') then - if (cont37915 = "000000000000000000000000") then cont37915 <= "0000_0000_0000_0001_0110_0011"; - else cont37915 <= cont37915-"000000000000000000000001"; - end if; - end if; -end process; -process(cont37915(8)) -begin - if(cont37915(8)'event and cont37915(8) = '1') then - clk37915 <= not clk37915; - end if; -end process; - -proxTX <= "000"&BUT(0) when atualTX="0000" else - "00"&(not BUT(0))&'1' when atualTX="0001" else - "001"&Q900 when atualTX="0011" else - "0110" when atualTX="0010" else - "011"&(not Q450) when atualTX="0110" else - - - @@ -119,60 +51,6 @@ proxTX <= "000"&BUT(0) when atualTX="0000" else UDISP: display port map(num7=>num7, num6=>num6, num5=>num5, num4=>num4, num3=>num3, num2=>num2, num1=>num1, num0=>num0, clk=>clkdisp, cs=>cs, dout=>din); -CLR_cont_S <= atual_S(1) and atual_S(0); -prox_S <= '0'&(not S_IR) when atual_S="00" else - "11" when atual_S="01" else - "10" when atual_S="11" else - (not S_IR & '0'); - -proxshift <= atualshift when ENshift = '0' else - SIshift & atualshift (31 downto 1); - -process (S_IR) -begin - if (S_IR'event and S_IR='0') then - atualshift <= proxshift; - end if; -end process; - -process (Q8ms) -begin - if (Q8ms'event and Q8ms='1') then - codigo32 <= atualshift; - end if; -end process; - -process (CLK100k) -begin - if (CLK100k'event and CLK100k='1') then - atual_S <= prox_S; - num7 <= proxnum7; - end if; -end process; - -UC0: CONTBCD_C port map(CLK => CLK100k, CLR => CLR_cont_S, UP => '1', EN => (S_IR and not Q8ms), ENOUT => EO(0), Q => num0); -UC1: CONTBCD_C port map(CLK => CLK100k, CLR => CLR_cont_S, UP => '1', EN => EO(0), ENOUT => EO(1), Q => num1); -UC2: CONTBCD_C port map(CLK => CLK100k, CLR => CLR_cont_S, UP => '1', EN => EO(1), ENOUT => EO(2), Q => num2); - -Q1ms <= num2(0); -Q4ms <= num2(2); -Q8ms <= num2(3); - -ENshift <= not Q8ms and not Q4ms; -SIshift <= Q1ms; - -proxnum7 <= "0000" when codigo32(31 downto 24)="11101001" else -- 0 = E9 - "0001" when codigo32(31 downto 24)="11110011" else -- 1 = F3 - "0010" when codigo32(31 downto 24)="11100111" else -- 2 = E7 - "0011" when codigo32(31 downto 24)="10100001" else -- 3 = A1 - "0100" when codigo32(31 downto 24)="11110111" else -- 4 = F7 - "0101" when codigo32(31 downto 24)="11100011" else -- 5 = E3 - "0110" when codigo32(31 downto 24)="10100101" else -- 6 = A5 - "0111" when codigo32(31 downto 24)="10111101" else -- 7 = BD - "1000" when codigo32(31 downto 24)="10101101" else -- 8 = AD - "1001" when codigo32(31 downto 24)="10110101" else -- 9 = B5 - num7; - process(CLK27MHz) begin if(CLK27MHz'event and CLK27MHz = '1') then @@ -190,9 +68,6 @@ clkdisp <= contaux(5); -- 421875 Hz GPIO(0) <= clkdisp; GPIO(1) <= cs; GPIO(2) <= din; -S_IR <= GPIO(4); -LEDS <= num7; -GPIO(5) <= CLK37915 and OUTIR; end comportamento; diff --git a/textovhdl.xpi b/textovhdl.xpi new file mode 100644 index 0000000..fe58c93 --- /dev/null +++ b/textovhdl.xpi @@ -0,0 +1,3 @@ +PROGRAM=PAR +STATE=ROUTED +TIMESPECS_MET=OFF diff --git a/textovhdl.xst b/textovhdl.xst new file mode 100644 index 0000000..88501c7 --- /dev/null +++ b/textovhdl.xst @@ -0,0 +1,52 @@ +set -tmpdir "xst/projnav.tmp" +set -xsthdpdir "xst" +run +-ifn textovhdl.prj +-ofn textovhdl +-ofmt NGC +-p xc6slx16-2-csg324 +-top textovhdl +-opt_mode Speed +-opt_level 1 +-power NO +-iuc NO +-keep_hierarchy No +-netlist_hierarchy As_Optimized +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case Maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-dsp_utilization_ratio 100 +-lc Auto +-reduce_control_sets Auto +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style LUT +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-shreg_extract YES +-rom_style Auto +-auto_bram_packing NO +-resource_sharing YES +-async_to_sync NO +-shreg_min_size 2 +-use_dsp48 Auto +-iobuf YES +-max_fanout 100000 +-bufg 16 +-register_duplication YES +-register_balancing No +-optimize_primitives NO +-use_clock_enable Auto +-use_sync_set Auto +-use_sync_reset Auto +-iob Auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/textovhdl_bitgen.xwbt b/textovhdl_bitgen.xwbt new file mode 100644 index 0000000..d18a913 --- /dev/null +++ b/textovhdl_bitgen.xwbt @@ -0,0 +1,8 @@ +INTSTYLE=ise +INFILE=C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.ncd +OUTFILE=C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.bit +FAMILY=Spartan6 +PART=xc6slx16-2csg324 +WORKINGDIR=C:\Users\Gabriel\Xilinx\Aula20220608 +LICENSE=WebPack +USER_INFO=212425623_0_0_843 diff --git a/textovhdl_envsettings.html b/textovhdl_envsettings.html new file mode 100644 index 0000000..df278f6 --- /dev/null +++ b/textovhdl_envsettings.html @@ -0,0 +1,538 @@ +Xilinx System Settings Report + +
System Settings

+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Environment Settings
Environment Variablexstngdbuildmappar
PATHEXT.COM;
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.MSC		.COM;
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PathC:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;
C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;
C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;
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C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;
C:\Xilinx\14.7\ISE_DS\common\bin\nt64;
C:\Xilinx\14.7\ISE_DS\common\lib\nt64;
C:\ProgramData\Oracle\Java\javapath;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Program Files\Intel\WiFi\bin\;
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C:\Program Files\TortoiseGit\bin;
C:\Program Files\Git\cmd;
C:\Program Files\Microsoft VS Code\bin;
C:\Program Files\MATLAB\R2022a\bin		C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;
C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;
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C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;
C:\Xilinx\14.7\ISE_DS\common\bin\nt64;
C:\Xilinx\14.7\ISE_DS\common\lib\nt64;
C:\ProgramData\Oracle\Java\javapath;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
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C:\Program Files\Intel\WiFi\bin\;
C:\Program Files\Common Files\Intel\WirelessCommon\;
C:\Program Files\TortoiseGit\bin;
C:\Program Files\Git\cmd;
C:\Program Files\Microsoft VS Code\bin;
C:\Program Files\MATLAB\R2022a\bin		C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;
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C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;
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C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;
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C:\ProgramData\Oracle\Java\javapath;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Program Files\Intel\WiFi\bin\;
C:\Program Files\Common Files\Intel\WirelessCommon\;
C:\Program Files\TortoiseGit\bin;
C:\Program Files\Git\cmd;
C:\Program Files\Microsoft VS Code\bin;
C:\Program Files\MATLAB\R2022a\bin		C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;
C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;
C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;
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C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;
C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;
C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;
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C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;
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C:\Xilinx\14.7\ISE_DS\common\bin\nt64;
C:\Xilinx\14.7\ISE_DS\common\lib\nt64;
C:\ProgramData\Oracle\Java\javapath;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Program Files\Intel\WiFi\bin\;
C:\Program Files\Common Files\Intel\WirelessCommon\;
C:\Program Files\TortoiseGit\bin;
C:\Program Files\Git\cmd;
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XILINXC:\Xilinx\14.7\ISE_DS\ISE\C:\Xilinx\14.7\ISE_DS\ISE\C:\Xilinx\14.7\ISE_DS\ISE\C:\Xilinx\14.7\ISE_DS\ISE\
XILINX_DSPC:\Xilinx\14.7\ISE_DS\ISEC:\Xilinx\14.7\ISE_DS\ISEC:\Xilinx\14.7\ISE_DS\ISEC:\Xilinx\14.7\ISE_DS\ISE
XILINX_EDKC:\Xilinx\14.7\ISE_DS\EDKC:\Xilinx\14.7\ISE_DS\EDKC:\Xilinx\14.7\ISE_DS\EDKC:\Xilinx\14.7\ISE_DS\EDK
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Synthesis Property Settings
Switch NameProperty NameValueDefault Value
-ifn textovhdl.prj 
-ofn textovhdl 
-ofmt NGCNGC
-p xc6slx16-2-csg324 
-top textovhdl 
-opt_modeOptimization GoalSpeedSpeed
-opt_levelOptimization Effort11
-powerPower ReductionNONo
-iucUse synthesis Constraints FileNONo
-keep_hierarchyKeep HierarchyNoNo
-netlist_hierarchyNetlist HierarchyAs_OptimizedAs_Optimized
-rtlviewGenerate RTL SchematicYesNo
-glob_optGlobal Optimization GoalAllClockNetsAllClockNets
-read_coresRead CoresYESYes
-write_timing_constraintsWrite Timing ConstraintsNONo
-cross_clock_analysisCross Clock AnalysisNONo
-bus_delimiterBus Delimiter<><>
-slice_utilization_ratioSlice Utilization Ratio100100
-bram_utilization_ratioBRAM Utilization Ratio100100
-dsp_utilization_ratioDSP Utilization Ratio100100
-reduce_control_sets AutoAuto
-fsm_extract YESYes
-fsm_encoding AutoAuto
-safe_implementation NoNo
-fsm_style LUTLUT
-ram_extract YesYes
-ram_style AutoAuto
-rom_extract YesYes
-shreg_extract YESYes
-rom_style AutoAuto
-auto_bram_packing NONo
-resource_sharing YESYes
-async_to_sync NONo
-use_dsp48 AutoAuto
-iobuf YESYes
-max_fanout 100000100000
-bufg 1616
-register_duplication YESYes
-register_balancing NoNo
-optimize_primitives NONo
-use_clock_enable AutoAuto
-use_sync_set AutoAuto
-use_sync_reset AutoAuto
-iob AutoAuto
-equivalent_register_removal YESYes
-slice_utilization_ratio_maxmargin 50
+ + 
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Translation Property Settings
Switch NameProperty NameValueDefault Value
-intstyle iseNone
-dd _ngoNone
-p xc6slx16-csg324-2None
-uc restricoes.ucfNone
+ + 
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Map Property Settings
Switch NameProperty NameValueDefault Value
-olPlace & Route Effort Level (Overall)highhigh
-xtExtra Cost Tables00
-irUse RLOC ConstraintsOFFOFF
-tStarting Placer Cost Table (1-100) Map10
-rRegister Ordering44
-intstyle iseNone
-lcLUT Combiningoffoff
-o textovhdl_map.ncdNone
-w truefalse
-prPack I/O Registers/Latches into IOBsoffoff
-p xc6slx16-csg324-2None
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Place and Route Property Settings
Switch NameProperty NameValueDefault Value
-intstyle ise 
-mtEnable Multi-Threadingoffoff
-olPlace & Route Effort Level (Overall)highstd
-w truefalse
+ + 
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Operating System Information
Operating System Informationxstngdbuildmappar
CPU Architecture/SpeedIntel(R) Core(TM)2 Duo CPU T9600 @ 2.80GHz/2793 MHzIntel(R) Core(TM)2 Duo CPU T9600 @ 2.80GHz/2793 MHzIntel(R) Core(TM)2 Duo CPU T9600 @ 2.80GHz/2793 MHzIntel(R) Core(TM)2 Duo CPU T9600 @ 2.80GHz/2793 MHz
HostGABRIEL-E5400GABRIEL-E5400GABRIEL-E5400GABRIEL-E5400
OS NameMicrosoft Windows 7 , 64-bitMicrosoft Windows 7 , 64-bitMicrosoft Windows 7 , 64-bitMicrosoft Windows 7 , 64-bit
OS ReleaseService Pack 1 (build 7601)Service Pack 1 (build 7601)Service Pack 1 (build 7601)Service Pack 1 (build 7601)
+ \ No newline at end of file diff --git a/textovhdl_guide.ncd b/textovhdl_guide.ncd new file mode 100644 index 0000000..4d2f837 --- /dev/null +++ b/textovhdl_guide.ncd @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6 +###6340:XlxV32DM 3fff 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SWM4fDL1iyDDY+AyModv9JDipGY/fhxomA8oaa7rl01IMLz2sOTrGe3jJqpPXE/QdB9jGhYZSvmws345FIRBWYx8/2LmGmaQFiMaGLIafC1DPrQBzV/o7pN8YYLPgZ+LCwBrhe/BIzoBvgIPzeImzSZ5zvKs+RkMJz/P8mzkWYZNMmyQ9728H+T9IO/XCy783Qvfc5EbbdhMug3SbSjSGJFGy/MizzM/s/vdvmg18SpSoiNKdESRjtAq22WVWVllQvey0mkN4SpDnfoPxUs8Rg==###2632:XlxV32DM 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\ No newline at end of file diff --git a/textovhdl_map.map b/textovhdl_map.map new file mode 100644 index 0000000..c135181 --- /dev/null +++ b/textovhdl_map.map @@ -0,0 +1,158 @@ +Release 14.7 Map P.20131013 (nt64) +Xilinx Map Application Log File for Design 'textovhdl' + +Design Information +------------------ +Command Line : map -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol +high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off +-pr off -lc off -power off -o textovhdl_map.ncd textovhdl.ngd textovhdl.pcf +Target Device : xc6slx16 +Target Package : csg324 +Target Speed : -2 +Mapper Version : spartan6 -- $Revision: 1.55 $ +Mapped Date : Wed Jun 08 11:35:36 2022 + +Mapping design into LUTs... +WARNING:MapLib:701 - Signal LEDS<3> connected to top level port LEDS<3> has been + removed. +WARNING:MapLib:701 - Signal LEDS<2> connected to top level port LEDS<2> has been + removed. +WARNING:MapLib:701 - Signal LEDS<1> connected to top level port LEDS<1> has been + removed. +WARNING:MapLib:701 - Signal LEDS<0> connected to top level port LEDS<0> has been + removed. +Running directed packing... +Running delay-based LUT packing... +Updating timing models... +INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report + (.mrp). +Running timing-driven placement... +Total REAL time at the beginning of Placer: 5 secs +Total CPU time at the beginning of Placer: 5 secs + +Phase 1.1 Initial Placement Analysis +Phase 1.1 Initial Placement Analysis (Checksum:3fba7d2c) REAL time: 5 secs + +Phase 2.7 Design Feasibility Check +Phase 2.7 Design Feasibility Check (Checksum:3fba7d2c) REAL time: 5 secs + +Phase 3.31 Local Placement Optimization +Phase 3.31 Local Placement Optimization (Checksum:3fba7d2c) REAL time: 5 secs + +Phase 4.2 Initial Placement for Architecture Specific Features + +Phase 4.2 Initial Placement for Architecture Specific Features +(Checksum:a88cf486) REAL time: 6 secs + +Phase 5.36 Local Placement Optimization +Phase 5.36 Local Placement Optimization (Checksum:a88cf486) REAL time: 6 secs + +Phase 6.30 Global Clock Region Assignment +Phase 6.30 Global Clock Region Assignment (Checksum:a88cf486) REAL time: 6 secs + +Phase 7.3 Local Placement Optimization +Phase 7.3 Local Placement Optimization (Checksum:a88cf486) REAL time: 6 secs + +Phase 8.5 Local Placement Optimization +Phase 8.5 Local Placement Optimization (Checksum:a88cf486) REAL time: 6 secs + +Phase 9.8 Global Placement +.... +.... +Phase 9.8 Global Placement (Checksum:74c7df35) REAL time: 6 secs + +Phase 10.5 Local Placement Optimization +Phase 10.5 Local Placement Optimization (Checksum:74c7df35) REAL time: 6 secs + +Phase 11.18 Placement Optimization +Phase 11.18 Placement Optimization (Checksum:b8849b8d) REAL time: 6 secs + +Phase 12.5 Local Placement Optimization +Phase 12.5 Local Placement Optimization (Checksum:b8849b8d) REAL time: 6 secs + +Phase 13.34 Placement Validation +Phase 13.34 Placement Validation (Checksum:b8849b8d) REAL time: 6 secs + +Total REAL time to Placer completion: 6 secs +Total CPU time to Placer completion: 6 secs +Running post-placement packing... +Writing output files... + +Design Summary +-------------- + +Design Summary: +Number of errors: 0 +Number of warnings: 4 +Slice Logic Utilization: + Number of Slice Registers: 32 out of 18,224 1% + Number used as Flip Flops: 32 + Number used as Latches: 0 + Number used as Latch-thrus: 0 + Number used as AND/OR logics: 0 + Number of Slice LUTs: 31 out of 9,112 1% + Number used as logic: 29 out of 9,112 1% + Number using O6 output only: 14 + Number using O5 output only: 11 + Number using O5 and O6: 4 + Number used as ROM: 0 + Number used as Memory: 0 out of 2,176 0% + Number used exclusively as route-thrus: 2 + Number with same-slice register load: 0 + Number with same-slice carry load: 2 + Number with other load: 0 + +Slice Logic Distribution: + Number of occupied Slices: 11 out of 2,278 1% + Number of MUXCYs used: 20 out of 4,556 1% + Number of LUT Flip Flop pairs used: 31 + Number with an unused Flip Flop: 1 out of 31 3% + Number with an unused LUT: 0 out of 31 0% + Number of fully used LUT-FF pairs: 30 out of 31 96% + Number of unique control sets: 2 + Number of slice register sites lost + to control set restrictions: 8 out of 18,224 1% + + A LUT Flip Flop pair for this architecture represents one LUT paired with + one Flip Flop within a slice. A control set is a unique combination of + clock, reset, set, and enable signals for a registered element. + The Slice Logic Distribution report is not meaningful if the design is + over-mapped for a non-slice resource or if Placement fails. + +IO Utilization: + Number of bonded IOBs: 17 out of 232 7% + Number of LOCed IOBs: 17 out of 17 100% + +Specific Feature Utilization: + Number of RAMB16BWERs: 0 out of 32 0% + Number of RAMB8BWERs: 0 out of 64 0% + Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0% + Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0% + Number of BUFG/BUFGMUXs: 2 out of 16 12% + Number used as BUFGs: 2 + Number used as BUFGMUX: 0 + Number of DCM/DCM_CLKGENs: 0 out of 4 0% + Number of ILOGIC2/ISERDES2s: 0 out of 248 0% + Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 248 0% + Number of OLOGIC2/OSERDES2s: 0 out of 248 0% + Number of BSCANs: 0 out of 4 0% + Number of BUFHs: 0 out of 128 0% + Number of BUFPLLs: 0 out of 8 0% + Number of BUFPLL_MCBs: 0 out of 4 0% + Number of DSP48A1s: 0 out of 32 0% + Number of ICAPs: 0 out of 1 0% + Number of MCBs: 0 out of 2 0% + Number of PCILOGICSEs: 0 out of 2 0% + Number of PLL_ADVs: 0 out of 2 0% + Number of PMVs: 0 out of 1 0% + Number of STARTUPs: 0 out of 1 0% + Number of SUSPEND_SYNCs: 0 out of 1 0% + +Average Fanout of Non-Clock Nets: 1.88 + +Peak Memory Usage: 346 MB +Total REAL time to MAP completion: 7 secs +Total CPU time to MAP completion: 6 secs + +Mapping completed. +See MAP report file "textovhdl_map.mrp" for details. diff --git a/textovhdl_map.mrp b/textovhdl_map.mrp new file mode 100644 index 0000000..c855f35 --- /dev/null +++ b/textovhdl_map.mrp @@ -0,0 +1,249 @@ +Release 14.7 Map P.20131013 (nt64) +Xilinx Mapping Report File for Design 'textovhdl' + +Design Information +------------------ +Command Line : map -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol +high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off +-pr off -lc off -power off -o textovhdl_map.ncd textovhdl.ngd textovhdl.pcf +Target Device : xc6slx16 +Target Package : csg324 +Target Speed : -2 +Mapper Version : spartan6 -- $Revision: 1.55 $ +Mapped Date : Wed Jun 08 11:35:36 2022 + +Design Summary +-------------- +Number of errors: 0 +Number of warnings: 4 +Slice Logic Utilization: + Number of Slice Registers: 32 out of 18,224 1% + Number used as Flip Flops: 32 + Number used as Latches: 0 + Number used as Latch-thrus: 0 + Number used as AND/OR logics: 0 + Number of Slice LUTs: 31 out of 9,112 1% + Number used as logic: 29 out of 9,112 1% + Number using O6 output only: 14 + Number using O5 output only: 11 + Number using O5 and O6: 4 + Number used as ROM: 0 + Number used as Memory: 0 out of 2,176 0% + Number used exclusively as route-thrus: 2 + Number with same-slice register load: 0 + Number with same-slice carry load: 2 + Number with other load: 0 + +Slice Logic Distribution: + Number of occupied Slices: 11 out of 2,278 1% + Number of MUXCYs used: 20 out of 4,556 1% + Number of LUT Flip Flop pairs used: 31 + Number with an unused Flip Flop: 1 out of 31 3% + Number with an unused LUT: 0 out of 31 0% + Number of fully used LUT-FF pairs: 30 out of 31 96% + Number of unique control sets: 2 + Number of slice register sites lost + to control set restrictions: 8 out of 18,224 1% + + A LUT Flip Flop pair for this architecture represents one LUT paired with + one Flip Flop within a slice. A control set is a unique combination of + clock, reset, set, and enable signals for a registered element. + The Slice Logic Distribution report is not meaningful if the design is + over-mapped for a non-slice resource or if Placement fails. + +IO Utilization: + Number of bonded IOBs: 17 out of 232 7% + Number of LOCed IOBs: 17 out of 17 100% + +Specific Feature Utilization: + Number of RAMB16BWERs: 0 out of 32 0% + Number of RAMB8BWERs: 0 out of 64 0% + Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0% + Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0% + Number of BUFG/BUFGMUXs: 2 out of 16 12% + Number used as BUFGs: 2 + Number used as BUFGMUX: 0 + Number of DCM/DCM_CLKGENs: 0 out of 4 0% + Number of ILOGIC2/ISERDES2s: 0 out of 248 0% + Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 248 0% + Number of OLOGIC2/OSERDES2s: 0 out of 248 0% + Number of BSCANs: 0 out of 4 0% + Number of BUFHs: 0 out of 128 0% + Number of BUFPLLs: 0 out of 8 0% + Number of BUFPLL_MCBs: 0 out of 4 0% + Number of DSP48A1s: 0 out of 32 0% + Number of ICAPs: 0 out of 1 0% + Number of MCBs: 0 out of 2 0% + Number of PCILOGICSEs: 0 out of 2 0% + Number of PLL_ADVs: 0 out of 2 0% + Number of PMVs: 0 out of 1 0% + Number of STARTUPs: 0 out of 1 0% + Number of SUSPEND_SYNCs: 0 out of 1 0% + +Average Fanout of Non-Clock Nets: 1.88 + +Peak Memory Usage: 346 MB +Total REAL time to MAP completion: 7 secs +Total CPU time to MAP completion: 6 secs + +Table of Contents +----------------- +Section 1 - Errors +Section 2 - Warnings +Section 3 - Informational +Section 4 - Removed Logic Summary +Section 5 - Removed Logic +Section 6 - IOB Properties +Section 7 - RPMs +Section 8 - Guide Report +Section 9 - Area Group and Partition Summary +Section 10 - Timing Report +Section 11 - Configuration String Information +Section 12 - Control Set Information +Section 13 - Utilization by Hierarchy + +Section 1 - Errors +------------------ + +Section 2 - Warnings +-------------------- +WARNING:MapLib:701 - Signal LEDS<3> connected to top level port LEDS<3> has been + removed. +WARNING:MapLib:701 - Signal LEDS<2> connected to top level port LEDS<2> has been + removed. +WARNING:MapLib:701 - Signal LEDS<1> connected to top level port LEDS<1> has been + removed. +WARNING:MapLib:701 - Signal LEDS<0> connected to top level port LEDS<0> has been + removed. + +Section 3 - Informational +------------------------- +INFO:LIT:243 - Logical network BUT<3>_IBUF has no load. +INFO:LIT:395 - The above info message is repeated 12 more times for the + following (max. 5 shown): + BUT<2>_IBUF, + BUT<1>_IBUF, + BUT<0>_IBUF, + DIPSW<3>_IBUF, + DIPSW<2>_IBUF + To see the details of these info messages, please use the -detail switch. +INFO:MapLib:562 - No environment variables are currently set. +INFO:LIT:244 - All of the single ended outputs in this design are using slew + rate limited output drivers. The delay on speed critical single ended outputs + can be dramatically reduced by designating them as fast outputs. +INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range: + 0.000 to 85.000 Celsius) +INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to + 1.260 Volts) +INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report + (.mrp). +INFO:Pack:1650 - Map created a placed design. + +Section 4 - Removed Logic Summary +--------------------------------- + 8 block(s) removed + 2 block(s) optimized away + 4 signal(s) removed + +Section 5 - Removed Logic +------------------------- + +The trimmed logic reported below is either: + 1. part of a cycle + 2. part of disabled logic + 3. a side-effect of other trimmed logic + +The signal "LEDS<3>" is unused and has been removed. + Unused block "LEDS_3_OBUFT" (TRI) removed. +The signal "LEDS<2>" is unused and has been removed. + Unused block "LEDS_2_OBUFT" (TRI) removed. +The signal "LEDS<1>" is unused and has been removed. + Unused block "LEDS_1_OBUFT" (TRI) removed. +The signal "LEDS<0>" is unused and has been removed. + Unused block "LEDS_0_OBUFT" (TRI) removed. +Unused block "LEDS<0>" (PAD) removed. +Unused block "LEDS<1>" (PAD) removed. +Unused block "LEDS<2>" (PAD) removed. +Unused block "LEDS<3>" (PAD) removed. + +Optimized Block(s): +TYPE BLOCK +GND XST_GND +VCC XST_VCC + +To enable printing of redundant blocks removed and signals merged, set the +detailed map report option and rerun map. + +Section 6 - IOB Properties +-------------------------- + ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB | +| | | | | Term | Strength | Rate | | | Delay | ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +| BUT<0> | IOB | INPUT | LVCMOS25 | | | | | | | +| BUT<1> | IOB | INPUT | LVCMOS25 | | | | | | | +| BUT<2> | IOB | INPUT | LVCMOS25 | | | | | | | +| BUT<3> | IOB | INPUT | LVCMOS25 | | | | | | | +| CLK27MHz | IOB | INPUT | LVCMOS25 | | | | | | | +| DIPSW<0> | IOB | INPUT | LVCMOS25 | | | | | | | +| DIPSW<1> | IOB | INPUT | LVCMOS25 | | | | | | | +| DIPSW<2> | IOB | INPUT | LVCMOS25 | | | | | | | +| DIPSW<3> | IOB | INPUT | LVCMOS25 | | | | | | | +| GPIO<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| GPIO<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| GPIO<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| GPIO<3> | IOB | INPUT | LVCMOS25 | | | | | | | +| GPIO<4> | IOB | INPUT | LVCMOS25 | | | | | | | +| GPIO<5> | IOB | INPUT | LVCMOS25 | | | | | | | +| GPIO<6> | IOB | INPUT | LVCMOS25 | | | | | | | +| GPIO<7> | IOB | INPUT | LVCMOS25 | | | | | | | ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ + +Section 7 - RPMs +---------------- + +Section 8 - Guide Report +------------------------ +Guide not run on this design. + +Section 9 - Area Group and Partition Summary +-------------------------------------------- + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +Area Group Information +---------------------- + + No area groups were found in this design. + +---------------------- + +Section 10 - Timing Report +-------------------------- +A logic-level (pre-route) timing report can be generated by using Xilinx static +timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the +mapped NCD and PCF files. Please note that this timing report will be generated +using estimated delay information. For accurate numbers, please generate a +timing report with the post Place and Route NCD file. + +For more information about the Timing Analyzer, consult the Xilinx Timing +Analyzer Reference Manual; for more information about TRCE, consult the Xilinx +Command Line Tools User Guide "TRACE" chapter. + +Section 11 - Configuration String Details +----------------------------------------- +Use the "-detail" map option to print out Configuration Strings + +Section 12 - Control Set Information +------------------------------------ +Use the "-detail" map option to print out Control Set Information. + +Section 13 - Utilization by Hierarchy +------------------------------------- +Use the "-detail" map option to print out the Utilization by Hierarchy section. diff --git a/textovhdl_map.ncd b/textovhdl_map.ncd new file mode 100644 index 0000000..71a028c --- /dev/null +++ b/textovhdl_map.ncd @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6 +###6160:XlxV32DM 3fff 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+ + + diff --git a/textovhdl_ngdbuild.xrpt b/textovhdl_ngdbuild.xrpt new file mode 100644 index 0000000..85c7aee --- /dev/null +++ b/textovhdl_ngdbuild.xrpt @@ -0,0 +1,113 @@ + + + + + + +
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+ + + + diff --git a/textovhdl_pad.csv b/textovhdl_pad.csv new file mode 100644 index 0000000..bb39f37 --- /dev/null +++ b/textovhdl_pad.csv @@ -0,0 +1,355 @@ +#Release 14.7 - par P.20131013 (nt64) +#Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +#Wed Jun 08 11:35:52 2022 + +# +## NOTE: This file is designed to be imported into a spreadsheet program +# such as Microsoft Excel for viewing, printing and sorting. The | +# character is used as the data field separator. This file is also designed +# to support parsing. +# +#INPUT FILE: textovhdl_map.ncd +#OUTPUT FILE: textovhdl_pad.csv +#PART TYPE: xc6slx16 +#SPEED GRADE: -2 +#PACKAGE: csg324 +# +# Pinout by Pin Number: +# +# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----, +Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,Drive (mA),Slew Rate,Termination,IOB Delay,Voltage,Constraint,IO Register,Signal Integrity, +A1,,,GND,,,,,,,,,,,, +A2,,IOBS,IO_L2N_0,UNUSED,,0,,,,,,,,, +A3,GPIO<2>,IOB,IO_L4N_0,OUTPUT,LVCMOS25*,0,12,SLOW,,,,LOCATED,NO,NONE, +A4,,IOBS,IO_L5N_0,UNUSED,,0,,,,,,,,, +A5,,IOBS,IO_L6N_0,UNUSED,,0,,,,,,,,, +A6,,IOBS,IO_L8N_VREF_0,UNUSED,,0,,,,,,,,, +A7,,IOBS,IO_L10N_0,UNUSED,,0,,,,,,,,, +A8,,IOBS,IO_L33N_0,UNUSED,,0,,,,,,,,, +A9,,IOBS,IO_L35N_GCLK16_0,UNUSED,,0,,,,,,,,, +A10,,IOBS,IO_L37N_GCLK12_0,UNUSED,,0,,,,,,,,, +A11,,IOBS,IO_L39N_0,UNUSED,,0,,,,,,,,, +A12,,IOBS,IO_L41N_0,UNUSED,,0,,,,,,,,, +A13,,IOBS,IO_L50N_0,UNUSED,,0,,,,,,,,, +A14,,IOBS,IO_L62N_VREF_0,UNUSED,,0,,,,,,,,, +A15,,IOBS,IO_L64N_SCP4_0,UNUSED,,0,,,,,,,,, +A16,,IOBS,IO_L66N_SCP0_0,UNUSED,,0,,,,,,,,, +A17,,,TCK,,,,,,,,,,,, +A18,,,GND,,,,,,,,,,,, +B1,,,VCCAUX,,,,,,,,2.5,,,, +B2,,IOBM,IO_L2P_0,UNUSED,,0,,,,,,,,, +B3,,IOBM,IO_L4P_0,UNUSED,,0,,,,,,,,, +B4,GPIO<5>,IOB,IO_L5P_0,INPUT,LVCMOS25*,0,,,,NONE,,LOCATED,NO,NONE, +B5,,,VCCO_0,,,0,,,,,2.50,,,, +B6,,IOBM,IO_L8P_0,UNUSED,,0,,,,,,,,, +B7,,,GND,,,,,,,,,,,, +B8,,IOBM,IO_L33P_0,UNUSED,,0,,,,,,,,, +B9,,IOBM,IO_L35P_GCLK17_0,UNUSED,,0,,,,,,,,, +B10,,,VCCO_0,,,0,,,,,2.50,,,, +B11,,IOBM,IO_L39P_0,UNUSED,,0,,,,,,,,, +B12,,IOBM,IO_L41P_0,UNUSED,,0,,,,,,,,, +B13,,,GND,,,,,,,,,,,, +B14,,IOBM,IO_L62P_0,UNUSED,,0,,,,,,,,, +B15,,,VCCO_0,,,0,,,,,2.50,,,, +B16,,IOBM,IO_L66P_SCP1_0,UNUSED,,0,,,,,,,,, +B17,,,VCCAUX,,,,,,,,2.5,,,, +B18,,,TMS,,,,,,,,,,,, +C1,,IOBS,IO_L83N_VREF_3,UNUSED,,3,,,,,,,,, +C2,,IOBM,IO_L83P_3,UNUSED,,3,,,,,,,,, +C3,,,GND,,,,,,,,,,,, +C4,,IOBS,IO_L1N_VREF_0,UNUSED,,0,,,,,,,,, +C5,,IOBM,IO_L6P_0,UNUSED,,0,,,,,,,,, +C6,,IOBS,IO_L3N_0,UNUSED,,0,,,,,,,,, +C7,,IOBM,IO_L10P_0,UNUSED,,0,,,,,,,,, +C8,,IOBS,IO_L11N_0,UNUSED,,0,,,,,,,,, +C9,,IOBS,IO_L34N_GCLK18_0,UNUSED,,0,,,,,,,,, +C10,,IOBM,IO_L37P_GCLK13_0,UNUSED,,0,,,,,,,,, +C11,,IOBS,IO_L36N_GCLK14_0,UNUSED,,0,,,,,,,,, +C12,,IOBS,IO_L47N_0,UNUSED,,0,,,,,,,,, +C13,,IOBM,IO_L50P_0,UNUSED,,0,,,,,,,,, +C14,,IOBS,IO_L65N_SCP2_0,UNUSED,,0,,,,,,,,, +C15,,IOBM,IO_L64P_SCP5_0,UNUSED,,0,,,,,,,,, +C16,,,GND,,,,,,,,,,,, +C17,,IOBM,IO_L29P_A23_M1A13_1,UNUSED,,1,,,,,,,,, +C18,,IOBS,IO_L29N_A22_M1A14_1,UNUSED,,1,,,,,,,,, +D1,,IOBS,IO_L52N_M3A9_3,UNUSED,,3,,,,,,,,, +D2,,IOBM,IO_L52P_M3A8_3,UNUSED,,3,,,,,,,,, +D3,,IOBS,IO_L54N_M3A11_3,UNUSED,,3,,,,,,,,, +D4,,IOBM,IO_L1P_HSWAPEN_0,UNUSED,,0,,,,,,,,, +D5,,,GND,,,,,,,,,,,, +D6,,IOBM,IO_L3P_0,UNUSED,,0,,,,,,,,, +D7,,,VCCO_0,,,0,,,,,2.50,,,, +D8,,IOBM,IO_L11P_0,UNUSED,,0,,,,,,,,, +D9,,IOBM,IO_L34P_GCLK19_0,UNUSED,,0,,,,,,,,, +D10,,,GND,,,,,,,,,,,, +D11,,IOBM,IO_L36P_GCLK15_0,UNUSED,,0,,,,,,,,, +D12,,IOBM,IO_L47P_0,UNUSED,,0,,,,,,,,, +D13,,,VCCO_0,,,0,,,,,2.50,,,, +D14,DIPSW<0>,IOB,IO_L65P_SCP3_0,INPUT,LVCMOS25*,0,,,,NONE,,LOCATED,NO,NONE, +D15,,,TDI,,,,,,,,,,,, +D16,,,TDO,,,,,,,,,,,, +D17,,IOBM,IO_L31P_A19_M1CKE_1,UNUSED,,1,,,,,,,,, +D18,,IOBS,IO_L31N_A18_M1A12_1,UNUSED,,1,,,,,,,,, +E1,,IOBS,IO_L50N_M3BA2_3,UNUSED,,3,,,,,,,,, +E2,,,VCCO_3,,,3,,,,,any******,,,, +E3,,IOBM,IO_L50P_M3WE_3,UNUSED,,3,,,,,,,,, +E4,BUT<2>,IOB,IO_L54P_M3RESET_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE, +E5,,,VCCAUX,,,,,,,,2.5,,,, +E6,,IOBS,IO_L7N_0,UNUSED,,0,,,,,,,,, +E7,,IOBM,IO_L9P_0,UNUSED,,0,,,,,,,,, +E8,,IOBS,IO_L9N_0,UNUSED,,0,,,,,,,,, +E9,,,VCCAUX,,,,,,,,2.5,,,, +E10,,,VCCO_0,,,0,,,,,2.50,,,, +E11,,IOBS,IO_L42N_0,UNUSED,,0,,,,,,,,, +E12,DIPSW<1>,IOB,IO_L51N_0,INPUT,LVCMOS25*,0,,,,NONE,,LOCATED,NO,NONE, +E13,,IOBS,IO_L63N_SCP6_0,UNUSED,,0,,,,,,,,, +E14,,,VCCAUX,,,,,,,,2.5,,,, +E15,,,GND,,,,,,,,,,,, +E16,,IOBM,IO_L33P_A15_M1A10_1,UNUSED,,1,,,,,,,,, +E17,,,VCCO_1,,,1,,,,,2.50,,,, +E18,,IOBS,IO_L33N_A14_M1A4_1,UNUSED,,1,,,,,,,,, +F1,,IOBS,IO_L48N_M3BA1_3,UNUSED,,3,,,,,,,,, +F2,,IOBM,IO_L48P_M3BA0_3,UNUSED,,3,,,,,,,,, +F3,,IOBS,IO_L51N_M3A4_3,UNUSED,,3,,,,,,,,, +F4,,IOBM,IO_L51P_M3A10_3,UNUSED,,3,,,,,,,,, +F5,BUT<3>,IOB,IO_L55N_M3A14_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE, +F6,BUT<1>,IOB,IO_L55P_M3A13_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE, +F7,,IOBM,IO_L7P_0,UNUSED,,0,,,,,,,,, +F8,,IOBS,IO_L32N_0,UNUSED,,0,,,,,,,,, +F9,,IOBS,IO_L38N_VREF_0,UNUSED,,0,,,,,,,,, +F10,,IOBS,IO_L40N_0,UNUSED,,0,,,,,,,,, +F11,,IOBM,IO_L42P_0,UNUSED,,0,,,,,,,,, +F12,DIPSW<2>,IOB,IO_L51P_0,INPUT,LVCMOS25*,0,,,,NONE,,LOCATED,NO,NONE, +F13,GPIO<6>,IOB,IO_L63P_SCP7_0,INPUT,LVCMOS25*,0,,,,NONE,,LOCATED,NO,NONE, +F14,,IOBM,IO_L30P_A21_M1RESET_1,UNUSED,,1,,,,,,,,, +F15,GPIO<4>,IOB,IO_L1P_A25_1,INPUT,LVCMOS25*,1,,,,NONE,,LOCATED,NO,NONE, +F16,,IOBS,IO_L1N_A24_VREF_1,UNUSED,,1,,,,,,,,, +F17,,IOBM,IO_L35P_A11_M1A7_1,UNUSED,,1,,,,,,,,, +F18,,IOBS,IO_L35N_A10_M1A2_1,UNUSED,,1,,,,,,,,, +G1,,IOBS,IO_L46N_M3CLKN_3,UNUSED,,3,,,,,,,,, +G2,,,GND,,,,,,,,,,,, +G3,,IOBM,IO_L46P_M3CLK_3,UNUSED,,3,,,,,,,,, +G4,,,VCCO_3,,,3,,,,,any******,,,, +G5,,,GND,,,,,,,,,,,, +G6,,IOBS,IO_L53N_M3A12_3,UNUSED,,3,,,,,,,,, +G7,,,VCCINT,,,,,,,,1.2,,,, +G8,,IOBM,IO_L32P_0,UNUSED,,0,,,,,,,,, +G9,,IOBM,IO_L38P_0,UNUSED,,0,,,,,,,,, +G10,,,VCCAUX,,,,,,,,2.5,,,, +G11,,IOBM,IO_L40P_0,UNUSED,,0,,,,,,,,, +G12,,,GND,,,,,,,,,,,, +G13,,IOBS,IO_L32N_A16_M1A9_1,UNUSED,,1,,,,,,,,, +G14,,IOBS,IO_L30N_A20_M1A11_1,UNUSED,,1,,,,,,,,, +G15,,,VCCO_1,,,1,,,,,2.50,,,, +G16,,IOBM,IO_L38P_A5_M1CLK_1,UNUSED,,1,,,,,,,,, +G17,,,GND,,,,,,,,,,,, +G18,,IOBS,IO_L38N_A4_M1CLKN_1,UNUSED,,1,,,,,,,,, +H1,,IOBS,IO_L41N_GCLK26_M3DQ5_3,UNUSED,,3,,,,,,,,, +H2,,IOBM,IO_L41P_GCLK27_M3DQ4_3,UNUSED,,3,,,,,,,,, +H3,,IOBS,IO_L44N_GCLK20_M3A6_3,UNUSED,,3,,,,,,,,, +H4,,IOBM,IO_L44P_GCLK21_M3A5_3,UNUSED,,3,,,,,,,,, +H5,,IOBS,IO_L49N_M3A2_3,UNUSED,,3,,,,,,,,, +H6,,IOBM,IO_L49P_M3A7_3,UNUSED,,3,,,,,,,,, +H7,,IOBM,IO_L53P_M3CKE_3,UNUSED,,3,,,,,,,,, +H8,,,GND,,,,,,,,,,,, +H9,,,VCCINT,,,,,,,,1.2,,,, +H10,,,GND,,,,,,,,,,,, +H11,,,VCCINT,,,,,,,,1.2,,,, +H12,,IOBM,IO_L32P_A17_M1A8_1,UNUSED,,1,,,,,,,,, +H13,,IOBM,IO_L36P_A9_M1BA0_1,UNUSED,,1,,,,,,,,, +H14,,IOBS,IO_L36N_A8_M1BA1_1,UNUSED,,1,,,,,,,,, +H15,,IOBM,IO_L37P_A7_M1A0_1,UNUSED,,1,,,,,,,,, +H16,,IOBS,IO_L37N_A6_M1A1_1,UNUSED,,1,,,,,,,,, +H17,,IOBM,IO_L43P_GCLK5_M1DQ4_1,UNUSED,,1,,,,,,,,, +H18,,IOBS,IO_L43N_GCLK4_M1DQ5_1,UNUSED,,1,,,,,,,,, +J1,,IOBS,IO_L40N_M3DQ7_3,UNUSED,,3,,,,,,,,, +J2,,,VCCO_3,,,3,,,,,any******,,,, +J3,,IOBM,IO_L40P_M3DQ6_3,UNUSED,,3,,,,,,,,, +J4,,,GND,,,,,,,,,,,, +J5,,,VCCO_3,,,3,,,,,any******,,,, +J6,,IOBS,IO_L47N_M3A1_3,UNUSED,,3,,,,,,,,, +J7,,IOBM,IO_L47P_M3A0_3,UNUSED,,3,,,,,,,,, +J8,,,VCCINT,,,,,,,,1.2,,,, +J9,,,GND,,,,,,,,,,,, +J10,,,VCCINT,,,,,,,,1.2,,,, +J11,,,GND,,,,,,,,,,,, +J12,,,VCCAUX,,,,,,,,2.5,,,, +J13,,IOBM,IO_L39P_M1A3_1,UNUSED,,1,,,,,,,,, +J14,,,VCCO_1,,,1,,,,,2.50,,,, +J15,,,GND,,,,,,,,,,,, +J16,,IOBM,IO_L44P_A3_M1DQ6_1,UNUSED,,1,,,,,,,,, +J17,,,VCCO_1,,,1,,,,,2.50,,,, +J18,,IOBS,IO_L44N_A2_M1DQ7_1,UNUSED,,1,,,,,,,,, +K1,,IOBS,IO_L38N_M3DQ3_3,UNUSED,,3,,,,,,,,, +K2,,IOBM,IO_L38P_M3DQ2_3,UNUSED,,3,,,,,,,,, +K3,,IOBS,IO_L42N_GCLK24_M3LDM_3,UNUSED,,3,,,,,,,,, +K4,,IOBM,IO_L42P_GCLK25_TRDY2_M3UDM_3,UNUSED,,3,,,,,,,,, +K5,,IOBS,IO_L43N_GCLK22_IRDY2_M3CASN_3,UNUSED,,3,,,,,,,,, +K6,,IOBS,IO_L45N_M3ODT_3,UNUSED,,3,,,,,,,,, +K7,,,VCCAUX,,,,,,,,2.5,,,, +K8,,,GND,,,,,,,,,,,, +K9,,,VCCINT,,,,,,,,1.2,,,, +K10,,,GND,,,,,,,,,,,, +K11,,,VCCINT,,,,,,,,1.2,,,, +K12,,IOBM,IO_L34P_A13_M1WE_1,UNUSED,,1,,,,,,,,, +K13,,IOBS,IO_L34N_A12_M1BA2_1,UNUSED,,1,,,,,,,,, +K14,,IOBS,IO_L39N_M1ODT_1,UNUSED,,1,,,,,,,,, +K15,,IOBM,IO_L41P_GCLK9_IRDY1_M1RASN_1,UNUSED,,1,,,,,,,,, +K16,,IOBS,IO_L41N_GCLK8_M1CASN_1,UNUSED,,1,,,,,,,,, +K17,,IOBM,IO_L45P_A1_M1LDQS_1,UNUSED,,1,,,,,,,,, +K18,,IOBS,IO_L45N_A0_M1LDQSN_1,UNUSED,,1,,,,,,,,, +L1,,IOBS,IO_L37N_M3DQ1_3,UNUSED,,3,,,,,,,,, +L2,,IOBM,IO_L37P_M3DQ0_3,UNUSED,,3,,,,,,,,, +L3,,IOBS,IO_L39N_M3LDQSN_3,UNUSED,,3,,,,,,,,, +L4,,IOBM,IO_L39P_M3LDQS_3,UNUSED,,3,,,,,,,,, +L5,,IOBM,IO_L43P_GCLK23_M3RASN_3,UNUSED,,3,,,,,,,,, +L6,,IOBM,IO_L31P_3,UNUSED,,3,,,,,,,,, +L7,,IOBM,IO_L45P_M3A3_3,UNUSED,,3,,,,,,,,, +L8,,,VCCINT,,,,,,,,1.2,,,, +L9,,,GND,,,,,,,,,,,, +L10,,,VCCINT,,,,,,,,1.2,,,, +L11,,,GND,,,,,,,,,,,, +L12,,IOBM,IO_L40P_GCLK11_M1A5_1,UNUSED,,1,,,,,,,,, +L13,,IOBS,IO_L40N_GCLK10_M1A6_1,UNUSED,,1,,,,,,,,, +L14,,IOBM,IO_L61P_1,UNUSED,,1,,,,,,,,, +L15,GPIO<3>,IOB,IO_L42P_GCLK7_M1UDM_1,INPUT,LVCMOS25*,1,,,,NONE,,LOCATED,NO,NONE, +L16,,IOBS,IO_L42N_GCLK6_TRDY1_M1LDM_1,UNUSED,,1,,,,,,,,, +L17,,IOBM,IO_L46P_FCS_B_M1DQ2_1,UNUSED,,1,,,,,,,,, +L18,,IOBS,IO_L46N_FOE_B_M1DQ3_1,UNUSED,,1,,,,,,,,, +M1,,IOBS,IO_L36N_M3DQ9_3,UNUSED,,3,,,,,,,,, +M2,,,GND,,,,,,,,,,,, +M3,,IOBM,IO_L36P_M3DQ8_3,UNUSED,,3,,,,,,,,, +M4,,,VCCO_3,,,3,,,,,any******,,,, +M5,,IOBS,IO_L31N_VREF_3,UNUSED,,3,,,,,,,,, +M6,,,GND,,,,,,,,,,,, +M7,,,VCCINT,,,,,,,,1.2,,,, +M8,,IOBM,IO_L40P_2,UNUSED,,2,,,,,,,,, +M9,,,VCCAUX,,,,,,,,2.5,,,, +M10,,IOBM,IO_L22P_2,UNUSED,,2,,,,,,,,, +M11,,IOBM,IO_L15P_2,UNUSED,,2,,,,,,,,, +M12,,,VCCINT,,,,,,,,1.2,,,, +M13,,IOBS,IO_L61N_1,UNUSED,,1,,,,,,,,, +M14,,IOBM,IO_L53P_1,UNUSED,,1,,,,,,,,, +M15,,,VCCO_1,,,1,,,,,2.50,,,, +M16,,IOBM,IO_L47P_FWE_B_M1DQ0_1,UNUSED,,1,,,,,,,,, +M17,,,GND,,,,,,,,,,,, +M18,GPIO<1>,IOB,IO_L47N_LDC_M1DQ1_1,OUTPUT,LVCMOS25*,1,12,SLOW,,,,LOCATED,NO,NONE, +N1,,IOBS,IO_L35N_M3DQ11_3,UNUSED,,3,,,,,,,,, +N2,,IOBM,IO_L35P_M3DQ10_3,UNUSED,,3,,,,,,,,, +N3,,IOBS,IO_L1N_VREF_3,UNUSED,,3,,,,,,,,, +N4,,IOBM,IO_L1P_3,UNUSED,,3,,,,,,,,, +N5,,IOBM,IO_L64P_D8_2,UNUSED,,2,,,,,,,,, +N6,,IOBM,IO_L47P_2,UNUSED,,2,,,,,,,,, +N7,,IOBM,IO_L44P_2,UNUSED,,2,,,,,,,,, +N8,,IOBS,IO_L40N_2,UNUSED,,2,,,,,,,,, +N9,,IOBS,IO_L22N_2,UNUSED,,2,,,,,,,,, +N10,,IOBM,IO_L20P_2,UNUSED,,2,,,,,,,,, +N11,,IOBS,IO_L15N_2,UNUSED,,2,,,,,,,,, +N12,,IOBM,IO_L13P_M1_2,UNUSED,,2,,,,,,,,, +N13,,,GND,,,,,,,,,,,, +N14,,IOBS,IO_L53N_VREF_1,UNUSED,,1,,,,,,,,, +N15,,IOBM,IO_L50P_M1UDQS_1,UNUSED,,1,,,,,,,,, +N16,,IOBS,IO_L50N_M1UDQSN_1,UNUSED,,1,,,,,,,,, +N17,GPIO<0>,IOB,IO_L48P_HDC_M1DQ8_1,OUTPUT,LVCMOS25*,1,12,SLOW,,,,LOCATED,NO,NONE, +N18,,IOBS,IO_L48N_M1DQ9_1,UNUSED,,1,,,,,,,,, +P1,,IOBS,IO_L34N_M3UDQSN_3,UNUSED,,3,,,,,,,,, +P2,,IOBM,IO_L34P_M3UDQS_3,UNUSED,,3,,,,,,,,, +P3,,IOBS,IO_L2N_3,UNUSED,,3,,,,,,,,, +P4,BUT<0>,IOB,IO_L2P_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE, +P5,,,VCCAUX,,,,,,,,2.5,,,, +P6,,IOBS,IO_L64N_D9_2,UNUSED,,2,,,,,,,,, +P7,,IOBS,IO_L47N_2,UNUSED,,2,,,,,,,,, +P8,,IOBS,IO_L44N_2,UNUSED,,2,,,,,,,,, +P9,,,VCCO_2,,,2,,,,,any******,,,, +P10,,,VCCAUX,,,,,,,,2.5,,,, +P11,,IOBS,IO_L20N_2,UNUSED,,2,,,,,,,,, +P12,GPIO<7>,IOB,IO_L13N_D10_2,INPUT,LVCMOS25*,2,,,,NONE,,LOCATED,NO,NONE, +P13,,,CMPCS_B_2,,,,,,,,,,,, +P14,,,VCCAUX,,,,,,,,2.5,,,, +P15,,IOBM,IO_L74P_AWAKE_1,UNUSED,,1,,,,,,,,, +P16,,IOBS,IO_L74N_DOUT_BUSY_1,UNUSED,,1,,,,,,,,, +P17,,IOBM,IO_L49P_M1DQ10_1,UNUSED,,1,,,,,,,,, +P18,,IOBS,IO_L49N_M1DQ11_1,UNUSED,,1,,,,,,,,, +R1,,,GND,,,,,,,,,,,, +R2,,,VCCO_3,,,3,,,,,any******,,,, +R3,,IOBM,IO_L62P_D5_2,UNUSED,,2,,,,,,,,, +R4,,,GND,,,,,,,,,,,, +R5,,IOBM,IO_L48P_D7_2,UNUSED,,2,,,,,,,,, +R6,,,VCCO_2,,,2,,,,,any******,,,, +R7,,IOBM,IO_L46P_2,UNUSED,,2,,,,,,,,, +R8,,IOBM,IO_L31P_GCLK31_D14_2,UNUSED,,2,,,,,,,,, +R9,,,GND,,,,,,,,,,,, +R10,,IOBM,IO_L29P_GCLK3_2,UNUSED,,2,,,,,,,,, +R11,,IOBM,IO_L16P_2,UNUSED,,2,,,,,,,,, +R12,,,VCCO_2,,,2,,,,,any******,,,, +R13,,IOBM,IO_L3P_D0_DIN_MISO_MISO1_2,UNUSED,,2,,,,,,,,, +R14,,,GND,,,,,,,,,,,, +R15,,IOBM,IO_L1P_CCLK_2,UNUSED,,2,,,,,,,,, +R16,,,SUSPEND,,,,,,,,,,,, +R17,,,VCCO_1,,,1,,,,,2.50,,,, +R18,,,GND,,,,,,,,,,,, +T1,,IOBS,IO_L33N_M3DQ13_3,UNUSED,,3,,,,,,,,, +T2,,IOBM,IO_L33P_M3DQ12_3,UNUSED,,3,,,,,,,,, +T3,,IOBS,IO_L62N_D6_2,UNUSED,,2,,,,,,,,, +T4,,IOBM,IO_L63P_2,UNUSED,,2,,,,,,,,, +T5,,IOBS,IO_L48N_RDWR_B_VREF_2,UNUSED,,2,,,,,,,,, +T6,,IOBM,IO_L45P_2,UNUSED,,2,,,,,,,,, +T7,,IOBS,IO_L46N_2,UNUSED,,2,,,,,,,,, +T8,,IOBS,IO_L31N_GCLK30_D15_2,UNUSED,,2,,,,,,,,, +T9,,IOBM,IO_L32P_GCLK29_2,UNUSED,,2,,,,,,,,, +T10,,IOBS,IO_L29N_GCLK2_2,UNUSED,,2,,,,,,,,, +T11,,IOBS,IO_L16N_VREF_2,UNUSED,,2,,,,,,,,, +T12,,IOBM,IO_L19P_2,UNUSED,,2,,,,,,,,, +T13,,IOBS,IO_L3N_MOSI_CSI_B_MISO0_2,UNUSED,,2,,,,,,,,, +T14,,IOBM,IO_L12P_D1_MISO2_2,UNUSED,,2,,,,,,,,, +T15,,IOBS,IO_L1N_M0_CMPMISO_2,UNUSED,,2,,,,,,,,, +T16,,,GND,,,,,,,,,,,, +T17,,IOBM,IO_L51P_M1DQ12_1,UNUSED,,1,,,,,,,,, +T18,,IOBS,IO_L51N_M1DQ13_1,UNUSED,,1,,,,,,,,, +U1,,IOBS,IO_L32N_M3DQ15_3,UNUSED,,3,,,,,,,,, +U2,,IOBM,IO_L32P_M3DQ14_3,UNUSED,,3,,,,,,,,, +U3,,IOBM,IO_L65P_INIT_B_2,UNUSED,,2,,,,,,,,, +U4,,,VCCO_2,,,2,,,,,any******,,,, +U5,,IOBM,IO_L49P_D3_2,UNUSED,,2,,,,,,,,, +U6,,,GND,,,,,,,,,,,, +U7,,IOBM,IO_L43P_2,UNUSED,,2,,,,,,,,, +U8,,IOBM,IO_L41P_2,UNUSED,,2,,,,,,,,, +U9,,,VCCO_2,,,2,,,,,any******,,,, +U10,,IOBM,IO_L30P_GCLK1_D13_2,UNUSED,,2,,,,,,,,, +U11,,IOBM,IO_L23P_2,UNUSED,,2,,,,,,,,, +U12,,,GND,,,,,,,,,,,, +U13,,IOBM,IO_L14P_D11_2,UNUSED,,2,,,,,,,,, +U14,,,VCCO_2,,,2,,,,,any******,,,, +U15,,IOBM,IO_L5P_2,UNUSED,,2,,,,,,,,, +U16,,IOBM,IO_L2P_CMPCLK_2,UNUSED,,2,,,,,,,,, +U17,,IOBM,IO_L52P_M1DQ14_1,UNUSED,,1,,,,,,,,, +U18,,IOBS,IO_L52N_M1DQ15_1,UNUSED,,1,,,,,,,,, +V1,,,GND,,,,,,,,,,,, +V2,,,PROGRAM_B_2,,,,,,,,,,,, +V3,,IOBS,IO_L65N_CSO_B_2,UNUSED,,2,,,,,,,,, +V4,,IOBS,IO_L63N_2,UNUSED,,2,,,,,,,,, +V5,,IOBS,IO_L49N_D4_2,UNUSED,,2,,,,,,,,, +V6,,IOBS,IO_L45N_2,UNUSED,,2,,,,,,,,, +V7,,IOBS,IO_L43N_2,UNUSED,,2,,,,,,,,, +V8,,IOBS,IO_L41N_VREF_2,UNUSED,,2,,,,,,,,, +V9,,IOBS,IO_L32N_GCLK28_2,UNUSED,,2,,,,,,,,, +V10,CLK27MHz,IOB,IO_L30N_GCLK0_USERCCLK_2,INPUT,LVCMOS25*,2,,,,NONE,,LOCATED,NO,NONE, +V11,,IOBS,IO_L23N_2,UNUSED,,2,,,,,,,,, +V12,,IOBS,IO_L19N_2,UNUSED,,2,,,,,,,,, +V13,DIPSW<3>,IOB,IO_L14N_D12_2,INPUT,LVCMOS25*,2,,,,NONE,,LOCATED,NO,NONE, +V14,,IOBS,IO_L12N_D2_MISO3_2,UNUSED,,2,,,,,,,,, +V15,,IOBS,IO_L5N_2,UNUSED,,2,,,,,,,,, +V16,,IOBS,IO_L2N_CMPMOSI_2,UNUSED,,2,,,,,,,,, +V17,,,DONE_2,,,,,,,,,,,, +V18,,,GND,,,,,,,,,,,, + +# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----, +# +#* Default value. +#** This default Pullup/Pulldown value can be overridden in Bitgen. +#****** Special VCCO requirements may apply. Please consult the device +# family datasheet for specific guideline on VCCO requirements. +# +# +# \ No newline at end of file diff --git a/textovhdl_pad.txt b/textovhdl_pad.txt new file mode 100644 index 0000000..6280243 --- /dev/null +++ b/textovhdl_pad.txt @@ -0,0 +1,354 @@ +Release 14.7 - par P.20131013 (nt64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +Wed Jun 08 11:35:52 2022 + + +INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are: +1. The _pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors. +2. The _pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information. +3. The .pad file designed for parsing by customers. It uses the "|" as a data field separator. + +INPUT FILE: textovhdl_map.ncd +OUTPUT FILE: textovhdl_pad.txt +PART TYPE: xc6slx16 +SPEED GRADE: -2 +PACKAGE: csg324 + +Pinout by Pin Number: + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +|Pin Number|Signal Name|Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|IO Register|Signal Integrity| ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +|A1 | | |GND | | | | | | | | | | | | +|A2 | |IOBS |IO_L2N_0 |UNUSED | |0 | | | | | | | | | +|A3 |GPIO<2> |IOB |IO_L4N_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW | | | |LOCATED |NO |NONE | +|A4 | |IOBS |IO_L5N_0 |UNUSED | |0 | | | | | | | | | +|A5 | |IOBS |IO_L6N_0 |UNUSED | |0 | | | | | | | | | +|A6 | |IOBS |IO_L8N_VREF_0 |UNUSED | |0 | | | | | | | | | +|A7 | |IOBS |IO_L10N_0 |UNUSED | |0 | | | | | | | | | +|A8 | |IOBS |IO_L33N_0 |UNUSED | |0 | | | | | | | | | +|A9 | |IOBS |IO_L35N_GCLK16_0 |UNUSED | |0 | | | | | | | | | +|A10 | |IOBS |IO_L37N_GCLK12_0 |UNUSED | |0 | | | | | | | | | +|A11 | |IOBS |IO_L39N_0 |UNUSED | |0 | | | | | | | | | +|A12 | |IOBS |IO_L41N_0 |UNUSED | |0 | | | | | | | | | +|A13 | |IOBS |IO_L50N_0 |UNUSED | |0 | | | | | | | | | +|A14 | |IOBS |IO_L62N_VREF_0 |UNUSED | |0 | | | | | | | | | +|A15 | |IOBS |IO_L64N_SCP4_0 |UNUSED | |0 | | | | | | | | | +|A16 | |IOBS |IO_L66N_SCP0_0 |UNUSED | |0 | | | | | | | | | +|A17 | | |TCK | | | | | | | | | | | | +|A18 | | |GND | | | | | | | | | | | | +|B1 | | |VCCAUX | | | | | | | |2.5 | | | | +|B2 | |IOBM |IO_L2P_0 |UNUSED | |0 | | | | | | | | | +|B3 | |IOBM |IO_L4P_0 |UNUSED | |0 | | | | | | | | | +|B4 |GPIO<5> |IOB |IO_L5P_0 |INPUT |LVCMOS25* |0 | | | |NONE | |LOCATED |NO |NONE | +|B5 | | |VCCO_0 | | |0 | | | | |2.50 | | | | +|B6 | |IOBM |IO_L8P_0 |UNUSED | |0 | | | | | | | | | +|B7 | | |GND | | | | | | | | | | | | +|B8 | |IOBM |IO_L33P_0 |UNUSED | |0 | | | | | | | | | +|B9 | |IOBM |IO_L35P_GCLK17_0 |UNUSED | |0 | | | | | | | | | +|B10 | | |VCCO_0 | | |0 | | | | |2.50 | | | | +|B11 | |IOBM |IO_L39P_0 |UNUSED | |0 | | | | | | | | | +|B12 | |IOBM |IO_L41P_0 |UNUSED | |0 | | | | | | | | | +|B13 | | |GND | | | | | | | | | | | | +|B14 | |IOBM |IO_L62P_0 |UNUSED | |0 | | | | | | | | | +|B15 | | |VCCO_0 | | |0 | | | | |2.50 | | | | +|B16 | |IOBM |IO_L66P_SCP1_0 |UNUSED | |0 | | | | | | | | | +|B17 | | |VCCAUX | | | | | | | |2.5 | | | | +|B18 | | |TMS | | | | | | | | | | | | +|C1 | |IOBS |IO_L83N_VREF_3 |UNUSED | |3 | | | | | | | | | +|C2 | |IOBM |IO_L83P_3 |UNUSED | |3 | | | | | | | | | +|C3 | | |GND | | | | | | | | | | | | +|C4 | |IOBS |IO_L1N_VREF_0 |UNUSED | |0 | | | | | | | | | +|C5 | |IOBM |IO_L6P_0 |UNUSED | |0 | | | | | | | | | +|C6 | |IOBS |IO_L3N_0 |UNUSED | |0 | | | | | | | | | +|C7 | |IOBM |IO_L10P_0 |UNUSED | |0 | | | | | | | | | +|C8 | |IOBS |IO_L11N_0 |UNUSED | |0 | | | | | | | | | +|C9 | |IOBS |IO_L34N_GCLK18_0 |UNUSED | |0 | | | | | | | | | +|C10 | |IOBM |IO_L37P_GCLK13_0 |UNUSED | |0 | | | | | | | | | +|C11 | |IOBS |IO_L36N_GCLK14_0 |UNUSED | |0 | | | | | | | | | +|C12 | |IOBS |IO_L47N_0 |UNUSED | |0 | | | | | | | | | +|C13 | |IOBM |IO_L50P_0 |UNUSED | |0 | | | | | | | | | +|C14 | |IOBS |IO_L65N_SCP2_0 |UNUSED | |0 | | | | | | | | | +|C15 | |IOBM |IO_L64P_SCP5_0 |UNUSED | |0 | | | | | | | | | +|C16 | | |GND | | | | | | | | | | | | +|C17 | |IOBM |IO_L29P_A23_M1A13_1 |UNUSED | |1 | | | | | | | | | +|C18 | |IOBS |IO_L29N_A22_M1A14_1 |UNUSED | |1 | | | | | | | | | +|D1 | |IOBS |IO_L52N_M3A9_3 |UNUSED | |3 | | | | | | | | | +|D2 | |IOBM |IO_L52P_M3A8_3 |UNUSED | |3 | | | | | | | | | +|D3 | |IOBS |IO_L54N_M3A11_3 |UNUSED | |3 | | | | | | | | | +|D4 | |IOBM |IO_L1P_HSWAPEN_0 |UNUSED | |0 | | | | | | | | | +|D5 | | |GND | | | | | | | | | | | | +|D6 | |IOBM |IO_L3P_0 |UNUSED | |0 | | | | | | | | | +|D7 | | |VCCO_0 | | |0 | | | | |2.50 | | | | +|D8 | |IOBM |IO_L11P_0 |UNUSED | |0 | | | | | | | | | +|D9 | |IOBM |IO_L34P_GCLK19_0 |UNUSED | |0 | | | | | | | | | +|D10 | | |GND | | | | | | | | | | | | +|D11 | |IOBM |IO_L36P_GCLK15_0 |UNUSED | |0 | | | | | | | | | +|D12 | |IOBM |IO_L47P_0 |UNUSED | |0 | | | | | | | | | +|D13 | | |VCCO_0 | | |0 | | | | |2.50 | | | | +|D14 |DIPSW<0> |IOB |IO_L65P_SCP3_0 |INPUT |LVCMOS25* |0 | | | |NONE | |LOCATED |NO |NONE | +|D15 | | |TDI | | | | | | | | | | | | +|D16 | | |TDO | | | | | | | | | | | | +|D17 | |IOBM |IO_L31P_A19_M1CKE_1 |UNUSED | |1 | | | | | | | | | +|D18 | |IOBS |IO_L31N_A18_M1A12_1 |UNUSED | |1 | | | | | | | | | +|E1 | |IOBS |IO_L50N_M3BA2_3 |UNUSED | |3 | | | | | | | | | +|E2 | | |VCCO_3 | | |3 | | | | |any******| | | | +|E3 | |IOBM |IO_L50P_M3WE_3 |UNUSED | |3 | | | | | | | | | +|E4 |BUT<2> |IOB |IO_L54P_M3RESET_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE | +|E5 | | |VCCAUX | | | | | | | |2.5 | | | | +|E6 | |IOBS |IO_L7N_0 |UNUSED | |0 | | | | | | | | | +|E7 | |IOBM |IO_L9P_0 |UNUSED | |0 | | | | | | | | | +|E8 | |IOBS |IO_L9N_0 |UNUSED | |0 | | | | | | | | | +|E9 | | |VCCAUX | | | | | | | |2.5 | | | | +|E10 | | |VCCO_0 | | |0 | | | | |2.50 | | | | +|E11 | |IOBS |IO_L42N_0 |UNUSED | |0 | | | | | | | | | +|E12 |DIPSW<1> |IOB |IO_L51N_0 |INPUT |LVCMOS25* |0 | | | |NONE | |LOCATED |NO |NONE | +|E13 | |IOBS |IO_L63N_SCP6_0 |UNUSED | |0 | | | | | | | | | +|E14 | | |VCCAUX | | | | | | | |2.5 | | | | +|E15 | | |GND | | | | | | | | | | | | +|E16 | |IOBM |IO_L33P_A15_M1A10_1 |UNUSED | |1 | | | | | | | | | +|E17 | | |VCCO_1 | | |1 | | | | |2.50 | | | | +|E18 | |IOBS |IO_L33N_A14_M1A4_1 |UNUSED | |1 | | | | | | | | | +|F1 | |IOBS |IO_L48N_M3BA1_3 |UNUSED | |3 | | | | | | | | | +|F2 | |IOBM |IO_L48P_M3BA0_3 |UNUSED | |3 | | | | | | | | | +|F3 | |IOBS |IO_L51N_M3A4_3 |UNUSED | |3 | | | | | | | | | +|F4 | |IOBM |IO_L51P_M3A10_3 |UNUSED | |3 | | | | | | | | | +|F5 |BUT<3> |IOB |IO_L55N_M3A14_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE | +|F6 |BUT<1> |IOB |IO_L55P_M3A13_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE | +|F7 | |IOBM |IO_L7P_0 |UNUSED | |0 | | | | | | | | | +|F8 | |IOBS |IO_L32N_0 |UNUSED | |0 | | | | | | | | | +|F9 | |IOBS |IO_L38N_VREF_0 |UNUSED | |0 | | | | | | | | | +|F10 | |IOBS |IO_L40N_0 |UNUSED | |0 | | | | | | | | | +|F11 | |IOBM |IO_L42P_0 |UNUSED | |0 | | | | | | | | | +|F12 |DIPSW<2> |IOB |IO_L51P_0 |INPUT |LVCMOS25* |0 | | | |NONE | |LOCATED |NO |NONE | +|F13 |GPIO<6> |IOB |IO_L63P_SCP7_0 |INPUT |LVCMOS25* |0 | | | |NONE | |LOCATED |NO |NONE | +|F14 | |IOBM |IO_L30P_A21_M1RESET_1 |UNUSED | |1 | | | | | | | | | +|F15 |GPIO<4> |IOB |IO_L1P_A25_1 |INPUT |LVCMOS25* |1 | | | |NONE | |LOCATED |NO |NONE | +|F16 | |IOBS |IO_L1N_A24_VREF_1 |UNUSED | |1 | | | | | | | | | +|F17 | |IOBM |IO_L35P_A11_M1A7_1 |UNUSED | |1 | | | | | | | | | +|F18 | |IOBS |IO_L35N_A10_M1A2_1 |UNUSED | |1 | | | | | | | | | +|G1 | |IOBS |IO_L46N_M3CLKN_3 |UNUSED | |3 | | | | | | | | | +|G2 | | |GND | | | | | | | | | | | | +|G3 | |IOBM |IO_L46P_M3CLK_3 |UNUSED | |3 | | | | | | | | | +|G4 | | |VCCO_3 | | |3 | | | | |any******| | | | +|G5 | | |GND | | | | | | | | | | | | +|G6 | |IOBS |IO_L53N_M3A12_3 |UNUSED | |3 | | | | | | | | | +|G7 | | |VCCINT | | | | | | | |1.2 | | | | +|G8 | |IOBM |IO_L32P_0 |UNUSED | |0 | | | | | | | | | +|G9 | |IOBM |IO_L38P_0 |UNUSED | |0 | | | | | | | | | +|G10 | | |VCCAUX | | | | | | | |2.5 | | | | +|G11 | |IOBM |IO_L40P_0 |UNUSED | |0 | | | | | | | | | +|G12 | | |GND | | | | | | | | | | | | +|G13 | |IOBS |IO_L32N_A16_M1A9_1 |UNUSED | |1 | | | | | | | | | +|G14 | |IOBS |IO_L30N_A20_M1A11_1 |UNUSED | |1 | | | | | | | | | +|G15 | | |VCCO_1 | | |1 | | | | |2.50 | | | | +|G16 | |IOBM |IO_L38P_A5_M1CLK_1 |UNUSED | |1 | | | | | | | | | +|G17 | | |GND | | | | | | | | | | | | +|G18 | |IOBS |IO_L38N_A4_M1CLKN_1 |UNUSED | |1 | | | | | | | | | +|H1 | |IOBS |IO_L41N_GCLK26_M3DQ5_3 |UNUSED | |3 | | | | | | | | | +|H2 | |IOBM |IO_L41P_GCLK27_M3DQ4_3 |UNUSED | |3 | | | | | | | | | +|H3 | |IOBS |IO_L44N_GCLK20_M3A6_3 |UNUSED | |3 | | | | | | | | | +|H4 | |IOBM |IO_L44P_GCLK21_M3A5_3 |UNUSED | |3 | | | | | | | | | +|H5 | |IOBS |IO_L49N_M3A2_3 |UNUSED | |3 | | | | | | | | | +|H6 | |IOBM |IO_L49P_M3A7_3 |UNUSED | |3 | | | | | | | | | +|H7 | |IOBM |IO_L53P_M3CKE_3 |UNUSED | |3 | | | | | | | | | +|H8 | | |GND | | | | | | | | | | | | +|H9 | | |VCCINT | | | | | | | |1.2 | | | | +|H10 | | |GND | | | | | | | | | | | | +|H11 | | |VCCINT | | | | | | | |1.2 | | | | +|H12 | |IOBM |IO_L32P_A17_M1A8_1 |UNUSED | |1 | | | | | | | | | +|H13 | |IOBM |IO_L36P_A9_M1BA0_1 |UNUSED | |1 | | | | | | | | | +|H14 | |IOBS |IO_L36N_A8_M1BA1_1 |UNUSED | |1 | | | | | | | | | +|H15 | |IOBM |IO_L37P_A7_M1A0_1 |UNUSED | |1 | | | | | | | | | +|H16 | |IOBS |IO_L37N_A6_M1A1_1 |UNUSED | |1 | | | | | | | | | +|H17 | |IOBM |IO_L43P_GCLK5_M1DQ4_1 |UNUSED | |1 | | | | | | | | | +|H18 | |IOBS |IO_L43N_GCLK4_M1DQ5_1 |UNUSED | |1 | | | | | | | | | +|J1 | |IOBS |IO_L40N_M3DQ7_3 |UNUSED | |3 | | | | | | | | | +|J2 | | |VCCO_3 | | |3 | | | | |any******| | | | +|J3 | |IOBM |IO_L40P_M3DQ6_3 |UNUSED | |3 | | | | | | | | | +|J4 | | |GND | | | | | | | | | | | | +|J5 | | |VCCO_3 | | |3 | | | | |any******| | | | +|J6 | |IOBS |IO_L47N_M3A1_3 |UNUSED | |3 | | | | | | | | | +|J7 | |IOBM |IO_L47P_M3A0_3 |UNUSED | |3 | | | | | | | | | +|J8 | | |VCCINT | | | | | | | |1.2 | | | | +|J9 | | |GND | | | | | | | | | | | | +|J10 | | |VCCINT | | | | | | | |1.2 | | | | +|J11 | | |GND | | | | | | | | | | | | +|J12 | | |VCCAUX | | | | | | | |2.5 | | | | +|J13 | |IOBM |IO_L39P_M1A3_1 |UNUSED | |1 | | | | | | | | | +|J14 | | |VCCO_1 | | |1 | | | | |2.50 | | | | +|J15 | | |GND | | | | | | | | | | | | +|J16 | |IOBM |IO_L44P_A3_M1DQ6_1 |UNUSED | |1 | | | | | | | | | +|J17 | | |VCCO_1 | | |1 | | | | |2.50 | | | | +|J18 | |IOBS |IO_L44N_A2_M1DQ7_1 |UNUSED | |1 | | | | | | | | | +|K1 | |IOBS |IO_L38N_M3DQ3_3 |UNUSED | |3 | | | | | | | | | +|K2 | |IOBM |IO_L38P_M3DQ2_3 |UNUSED | |3 | | | | | | | | | +|K3 | |IOBS |IO_L42N_GCLK24_M3LDM_3 |UNUSED | |3 | | | | | | | | | +|K4 | |IOBM |IO_L42P_GCLK25_TRDY2_M3UDM_3 |UNUSED | |3 | | | | | | | | | +|K5 | |IOBS |IO_L43N_GCLK22_IRDY2_M3CASN_3|UNUSED | |3 | | | | | | | | | +|K6 | |IOBS |IO_L45N_M3ODT_3 |UNUSED | |3 | | | | | | | | | +|K7 | | |VCCAUX | | | | | | | |2.5 | | | | +|K8 | | |GND | | | | | | | | | | | | +|K9 | | |VCCINT | | | | | | | |1.2 | | | | +|K10 | | |GND | | | | | | | | | | | | +|K11 | | |VCCINT | | | | | | | |1.2 | | | | +|K12 | |IOBM |IO_L34P_A13_M1WE_1 |UNUSED | |1 | | | | | | | | | +|K13 | |IOBS |IO_L34N_A12_M1BA2_1 |UNUSED | |1 | | | | | | | | | +|K14 | |IOBS |IO_L39N_M1ODT_1 |UNUSED | |1 | | | | | | | | | +|K15 | |IOBM |IO_L41P_GCLK9_IRDY1_M1RASN_1 |UNUSED | |1 | | | | | | | | | +|K16 | |IOBS |IO_L41N_GCLK8_M1CASN_1 |UNUSED | |1 | | | | | | | | | +|K17 | |IOBM |IO_L45P_A1_M1LDQS_1 |UNUSED | |1 | | | | | | | | | +|K18 | |IOBS |IO_L45N_A0_M1LDQSN_1 |UNUSED | |1 | | | | | | | | | +|L1 | |IOBS |IO_L37N_M3DQ1_3 |UNUSED | |3 | | | | | | | | | +|L2 | |IOBM |IO_L37P_M3DQ0_3 |UNUSED | |3 | | | | | | | | | +|L3 | |IOBS |IO_L39N_M3LDQSN_3 |UNUSED | |3 | | | | | | | | | +|L4 | |IOBM |IO_L39P_M3LDQS_3 |UNUSED | |3 | | | | | | | | | +|L5 | |IOBM |IO_L43P_GCLK23_M3RASN_3 |UNUSED | |3 | | | | | | | | | +|L6 | |IOBM |IO_L31P_3 |UNUSED | |3 | | | | | | | | | +|L7 | |IOBM |IO_L45P_M3A3_3 |UNUSED | |3 | | | | | | | | | +|L8 | | |VCCINT | | | | | | | |1.2 | | | | +|L9 | | |GND | | | | | | | | | | | | +|L10 | | |VCCINT | | | | | | | |1.2 | | | | +|L11 | | |GND | | | | | | | | | | | | +|L12 | |IOBM |IO_L40P_GCLK11_M1A5_1 |UNUSED | |1 | | | | | | | | | +|L13 | |IOBS |IO_L40N_GCLK10_M1A6_1 |UNUSED | |1 | | | | | | | | | +|L14 | |IOBM |IO_L61P_1 |UNUSED | |1 | | | | | | | | | +|L15 |GPIO<3> |IOB |IO_L42P_GCLK7_M1UDM_1 |INPUT |LVCMOS25* |1 | | | |NONE | |LOCATED |NO |NONE | +|L16 | |IOBS |IO_L42N_GCLK6_TRDY1_M1LDM_1 |UNUSED | |1 | | | | | | | | | +|L17 | |IOBM |IO_L46P_FCS_B_M1DQ2_1 |UNUSED | |1 | | | | | | | | | +|L18 | |IOBS |IO_L46N_FOE_B_M1DQ3_1 |UNUSED | |1 | | | | | | | | | +|M1 | |IOBS |IO_L36N_M3DQ9_3 |UNUSED | |3 | | | | | | | | | +|M2 | | |GND | | | | | | | | | | | | +|M3 | |IOBM |IO_L36P_M3DQ8_3 |UNUSED | |3 | | | | | | | | | +|M4 | | |VCCO_3 | | |3 | | | | |any******| | | | +|M5 | |IOBS |IO_L31N_VREF_3 |UNUSED | |3 | | | | | | | | | +|M6 | | |GND | | | | | | | | | | | | +|M7 | | |VCCINT | | | | | | | |1.2 | | | | +|M8 | |IOBM |IO_L40P_2 |UNUSED | |2 | | | | | | | | | +|M9 | | |VCCAUX | | | | | | | |2.5 | | | | +|M10 | |IOBM |IO_L22P_2 |UNUSED | |2 | | | | | | | | | +|M11 | |IOBM |IO_L15P_2 |UNUSED | |2 | | | | | | | | | +|M12 | | |VCCINT | | | | | | | |1.2 | | | | +|M13 | |IOBS |IO_L61N_1 |UNUSED | |1 | | | | | | | | | +|M14 | |IOBM |IO_L53P_1 |UNUSED | |1 | | | | | | | | | +|M15 | | |VCCO_1 | | |1 | | | | |2.50 | | | | +|M16 | |IOBM |IO_L47P_FWE_B_M1DQ0_1 |UNUSED | |1 | | | | | | | | | +|M17 | | |GND | | | | | | | | | | | | +|M18 |GPIO<1> |IOB |IO_L47N_LDC_M1DQ1_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW | | | |LOCATED |NO |NONE | +|N1 | |IOBS |IO_L35N_M3DQ11_3 |UNUSED | |3 | | | | | | | | | +|N2 | |IOBM |IO_L35P_M3DQ10_3 |UNUSED | |3 | | | | | | | | | +|N3 | |IOBS |IO_L1N_VREF_3 |UNUSED | |3 | | | | | | | | | +|N4 | |IOBM |IO_L1P_3 |UNUSED | |3 | | | | | | | | | +|N5 | |IOBM |IO_L64P_D8_2 |UNUSED | |2 | | | | | | | | | +|N6 | |IOBM |IO_L47P_2 |UNUSED | |2 | | | | | | | | | +|N7 | |IOBM |IO_L44P_2 |UNUSED | |2 | | | | | | | | | +|N8 | |IOBS |IO_L40N_2 |UNUSED | |2 | | | | | | | | | +|N9 | |IOBS |IO_L22N_2 |UNUSED | |2 | | | | | | | | | +|N10 | |IOBM |IO_L20P_2 |UNUSED | |2 | | | | | | | | | +|N11 | |IOBS |IO_L15N_2 |UNUSED | |2 | | | | | | | | | +|N12 | |IOBM |IO_L13P_M1_2 |UNUSED | |2 | | | | | | | | | +|N13 | | |GND | | | | | | | | | | | | +|N14 | |IOBS |IO_L53N_VREF_1 |UNUSED | |1 | | | | | | | | | +|N15 | |IOBM |IO_L50P_M1UDQS_1 |UNUSED | |1 | | | | | | | | | +|N16 | |IOBS |IO_L50N_M1UDQSN_1 |UNUSED | |1 | | | | | | | | | +|N17 |GPIO<0> |IOB |IO_L48P_HDC_M1DQ8_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW | | | |LOCATED |NO |NONE | +|N18 | |IOBS |IO_L48N_M1DQ9_1 |UNUSED | |1 | | | | | | | | | +|P1 | |IOBS |IO_L34N_M3UDQSN_3 |UNUSED | |3 | | | | | | | | | +|P2 | |IOBM |IO_L34P_M3UDQS_3 |UNUSED | |3 | | | | | | | | | +|P3 | |IOBS |IO_L2N_3 |UNUSED | |3 | | | | | | | | | +|P4 |BUT<0> |IOB |IO_L2P_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE | +|P5 | | |VCCAUX | | | | | | | |2.5 | | | | +|P6 | |IOBS |IO_L64N_D9_2 |UNUSED | |2 | | | | | | | | | +|P7 | |IOBS |IO_L47N_2 |UNUSED | |2 | | | | | | | | | +|P8 | |IOBS |IO_L44N_2 |UNUSED | |2 | | | | | | | | | +|P9 | | |VCCO_2 | | |2 | | | | |any******| | | | +|P10 | | |VCCAUX | | | | | | | |2.5 | | | | +|P11 | |IOBS |IO_L20N_2 |UNUSED | |2 | | | | | | | | | +|P12 |GPIO<7> |IOB |IO_L13N_D10_2 |INPUT |LVCMOS25* |2 | | | |NONE | |LOCATED |NO |NONE | +|P13 | | |CMPCS_B_2 | | | | | | | | | | | | +|P14 | | |VCCAUX | | | | | | | |2.5 | | | | +|P15 | |IOBM |IO_L74P_AWAKE_1 |UNUSED | |1 | | | | | | | | | +|P16 | |IOBS |IO_L74N_DOUT_BUSY_1 |UNUSED | |1 | | | | | | | | | +|P17 | |IOBM |IO_L49P_M1DQ10_1 |UNUSED | |1 | | | | | | | | | +|P18 | |IOBS |IO_L49N_M1DQ11_1 |UNUSED | |1 | | | | | | | | | +|R1 | | |GND | | | | | | | | | | | | +|R2 | | |VCCO_3 | | |3 | | | | |any******| | | | +|R3 | |IOBM |IO_L62P_D5_2 |UNUSED | |2 | | | | | | | | | +|R4 | | |GND | | | | | | | | | | | | +|R5 | |IOBM |IO_L48P_D7_2 |UNUSED | |2 | | | | | | | | | +|R6 | | |VCCO_2 | | |2 | | | | |any******| | | | +|R7 | |IOBM |IO_L46P_2 |UNUSED | |2 | | | | | | | | | +|R8 | |IOBM |IO_L31P_GCLK31_D14_2 |UNUSED | |2 | | | | | | | | | +|R9 | | |GND | | | | | | | | | | | | +|R10 | |IOBM |IO_L29P_GCLK3_2 |UNUSED | |2 | | | | | | | | | +|R11 | |IOBM |IO_L16P_2 |UNUSED | |2 | | | | | | | | | +|R12 | | |VCCO_2 | | |2 | | | | |any******| | | | +|R13 | |IOBM |IO_L3P_D0_DIN_MISO_MISO1_2 |UNUSED | |2 | | | | | | | | | +|R14 | | |GND | | | | | | | | | | | | +|R15 | |IOBM |IO_L1P_CCLK_2 |UNUSED | |2 | | | | | | | | | +|R16 | | |SUSPEND | | | | | | | | | | | | +|R17 | | |VCCO_1 | | |1 | | | | |2.50 | | | | +|R18 | | |GND | | | | | | | | | | | | +|T1 | |IOBS |IO_L33N_M3DQ13_3 |UNUSED | |3 | | | | | | | | | +|T2 | |IOBM |IO_L33P_M3DQ12_3 |UNUSED | |3 | | | | | | | | | +|T3 | |IOBS |IO_L62N_D6_2 |UNUSED | |2 | | | | | | | | | +|T4 | |IOBM |IO_L63P_2 |UNUSED | |2 | | | | | | | | | +|T5 | |IOBS |IO_L48N_RDWR_B_VREF_2 |UNUSED | |2 | | | | | | | | | +|T6 | |IOBM |IO_L45P_2 |UNUSED | |2 | | | | | | | | | +|T7 | |IOBS |IO_L46N_2 |UNUSED | |2 | | | | | | | | | +|T8 | |IOBS |IO_L31N_GCLK30_D15_2 |UNUSED | |2 | | | | | | | | | +|T9 | |IOBM |IO_L32P_GCLK29_2 |UNUSED | |2 | | | | | | | | | +|T10 | |IOBS |IO_L29N_GCLK2_2 |UNUSED | |2 | | | | | | | | | +|T11 | |IOBS |IO_L16N_VREF_2 |UNUSED | |2 | | | | | | | | | +|T12 | |IOBM |IO_L19P_2 |UNUSED | |2 | | | | | | | | | +|T13 | |IOBS |IO_L3N_MOSI_CSI_B_MISO0_2 |UNUSED | |2 | | | | | | | | | +|T14 | |IOBM |IO_L12P_D1_MISO2_2 |UNUSED | |2 | | | | | | | | | +|T15 | |IOBS |IO_L1N_M0_CMPMISO_2 |UNUSED | |2 | | | | | | | | | +|T16 | | |GND | | | | | | | | | | | | +|T17 | |IOBM |IO_L51P_M1DQ12_1 |UNUSED | |1 | | | | | | | | | +|T18 | |IOBS |IO_L51N_M1DQ13_1 |UNUSED | |1 | | | | | | | | | +|U1 | |IOBS |IO_L32N_M3DQ15_3 |UNUSED | |3 | | | | | | | | | +|U2 | |IOBM |IO_L32P_M3DQ14_3 |UNUSED | |3 | | | | | | | | | +|U3 | |IOBM |IO_L65P_INIT_B_2 |UNUSED | |2 | | | | | | | | | +|U4 | | |VCCO_2 | | |2 | | | | |any******| | | | +|U5 | |IOBM |IO_L49P_D3_2 |UNUSED | |2 | | | | | | | | | +|U6 | | |GND | | | | | | | | | | | | +|U7 | |IOBM |IO_L43P_2 |UNUSED | |2 | | | | | | | | | +|U8 | |IOBM |IO_L41P_2 |UNUSED | |2 | | | | | | | | | +|U9 | | |VCCO_2 | | |2 | | | | |any******| | | | +|U10 | |IOBM |IO_L30P_GCLK1_D13_2 |UNUSED | |2 | | | | | | | | | +|U11 | |IOBM |IO_L23P_2 |UNUSED | |2 | | | | | | | | | +|U12 | | |GND | | | | | | | | | | | | +|U13 | |IOBM |IO_L14P_D11_2 |UNUSED | |2 | | | | | | | | | +|U14 | | |VCCO_2 | | |2 | | | | |any******| | | | +|U15 | |IOBM |IO_L5P_2 |UNUSED | |2 | | | | | | | | | +|U16 | |IOBM |IO_L2P_CMPCLK_2 |UNUSED | |2 | | | | | | | | | +|U17 | |IOBM |IO_L52P_M1DQ14_1 |UNUSED | |1 | | | | | | | | | +|U18 | |IOBS |IO_L52N_M1DQ15_1 |UNUSED | |1 | | | | | | | | | +|V1 | | |GND | | | | | | | | | | | | +|V2 | | |PROGRAM_B_2 | | | | | | | | | | | | +|V3 | |IOBS |IO_L65N_CSO_B_2 |UNUSED | |2 | | | | | | | | | +|V4 | |IOBS |IO_L63N_2 |UNUSED | |2 | | | | | | | | | +|V5 | |IOBS |IO_L49N_D4_2 |UNUSED | |2 | | | | | | | | | +|V6 | |IOBS |IO_L45N_2 |UNUSED | |2 | | | | | | | | | +|V7 | |IOBS |IO_L43N_2 |UNUSED | |2 | | | | | | | | | +|V8 | |IOBS |IO_L41N_VREF_2 |UNUSED | |2 | | | | | | | | | +|V9 | |IOBS |IO_L32N_GCLK28_2 |UNUSED | |2 | | | | | | | | | +|V10 |CLK27MHz |IOB |IO_L30N_GCLK0_USERCCLK_2 |INPUT |LVCMOS25* |2 | | | |NONE | |LOCATED |NO |NONE | +|V11 | |IOBS |IO_L23N_2 |UNUSED | |2 | | | | | | | | | +|V12 | |IOBS |IO_L19N_2 |UNUSED | |2 | | | | | | | | | +|V13 |DIPSW<3> |IOB |IO_L14N_D12_2 |INPUT |LVCMOS25* |2 | | | |NONE | |LOCATED |NO |NONE | +|V14 | |IOBS |IO_L12N_D2_MISO3_2 |UNUSED | |2 | | | | | | | | | +|V15 | |IOBS |IO_L5N_2 |UNUSED | |2 | | | | | | | | | +|V16 | |IOBS |IO_L2N_CMPMOSI_2 |UNUSED | |2 | | | | | | | | | +|V17 | | |DONE_2 | | | | | | | | | | | | +|V18 | | |GND | | | | | | | | | | | | ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + +* Default value. +** This default Pullup/Pulldown value can be overridden in Bitgen. +****** Special VCCO requirements may apply. Please consult the device + family datasheet for specific guideline on VCCO requirements. + + diff --git a/textovhdl_par.xrpt b/textovhdl_par.xrpt new file mode 100644 index 0000000..e54d76d --- /dev/null +++ b/textovhdl_par.xrpt @@ -0,0 +1,2400 @@ + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + + + + + + + + + + +
+
+ +
+ + + + +
+ + +
+ + + + + + +
+ + +
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+ + + + +
+
+
+ + + +
+ + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + + + + + + + + + + +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + +
+
+
+ + +
+
+ + + + + + + + + + + + + + +
+
+ + + +
+ + + + diff --git a/textovhdl_summary.html b/textovhdl_summary.html new file mode 100644 index 0000000..9b47b4a --- /dev/null +++ b/textovhdl_summary.html @@ -0,0 +1,411 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
textovhdl Project Status (06/08/2022 - 11:36:16)
Project File:Aula20220608.xiseParser Errors: No Errors
Module Name:textovhdlImplementation State:Programming File Generated
Target Device:xc6slx16-2csg324
  • Errors:
 +No Errors
Product Version:ISE 14.7
  • Warnings:
56 Warnings (56 new)
Design Goal:Balanced
  • Routing Results:
 +All Signals Completely Routed
Design Strategy:Xilinx Default (unlocked)
  • Timing Constraints:
 +All Constraints Met
Environment: + +System Settings +
  • Final Timing Score:
0  (Timing Report)
+ + + + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers3218,2241% 
    Number used as Flip Flops32   
    Number used as Latches0   
    Number used as Latch-thrus0   
    Number used as AND/OR logics0   
Number of Slice LUTs319,1121% 
    Number used as logic299,1121% 
        Number using O6 output only14   
        Number using O5 output only11   
        Number using O5 and O64   
        Number used as ROM0   
    Number used as Memory02,1760% 
    Number used exclusively as route-thrus2   
        Number with same-slice register load0   
        Number with same-slice carry load2   
        Number with other load0   
Number of occupied Slices112,2781% 
Number of MUXCYs used204,5561% 
Number of LUT Flip Flop pairs used31   
    Number with an unused Flip Flop1313% 
    Number with an unused LUT0310% 
    Number of fully used LUT-FF pairs303196% 
    Number of unique control sets2   
    Number of slice register sites lost
        to control set restrictions		818,2241% 
Number of bonded IOBs172327% 
    Number of LOCed IOBs1717100% 
Number of RAMB16BWERs0320% 
Number of RAMB8BWERs0640% 
Number of BUFIO2/BUFIO2_2CLKs0320% 
Number of BUFIO2FB/BUFIO2FB_2CLKs0320% 
Number of BUFG/BUFGMUXs21612% 
    Number used as BUFGs2   
    Number used as BUFGMUX0   
Number of DCM/DCM_CLKGENs040% 
Number of ILOGIC2/ISERDES2s02480% 
Number of IODELAY2/IODRP2/IODRP2_MCBs02480% 
Number of OLOGIC2/OSERDES2s02480% 
Number of BSCANs040% 
Number of BUFHs01280% 
Number of BUFPLLs080% 
Number of BUFPLL_MCBs040% 
Number of DSP48A1s0320% 
Number of ICAPs010% 
Number of MCBs020% 
Number of PCILOGICSEs020% 
Number of PLL_ADVs020% 
Number of PMVs010% 
Number of STARTUPs010% 
Number of SUSPEND_SYNCs010% 
Average Fanout of Non-Clock Nets1.88   
+ + + + 
+ + + + + + + + + + + + + + + + + +
Performance Summary [-]
Final Timing Score:0 (Setup: 0, Hold: 0)Pinout Data:Pinout Report
Routing Results: +All Signals Completely RoutedClock Data:Clock Report
Timing Constraints: +All Constraints Met  
+ + + + 
+ + + + + + + + + + +
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis ReportCurrentWed Jun 8 11:34:43 2022032 Warnings (32 new)1 Info (1 new)
Translation ReportCurrentWed Jun 8 11:35:33 202205 Warnings (5 new)0
Map ReportCurrentWed Jun 8 11:35:43 202204 Warnings (4 new)8 Infos (8 new)
Place and Route ReportCurrentWed Jun 8 11:35:52 2022015 Warnings (15 new)3 Infos (3 new)
Power Report     
Post-PAR Static Timing ReportCurrentWed Jun 8 11:35:59 2022004 Infos (4 new)
Bitgen ReportCurrentWed Jun 8 11:36:14 2022000
+ 
+ + + + +
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentWed Jun 8 11:36:14 2022
WebTalk Log FileCurrentWed Jun 8 11:36:16 2022
+ + +
Date Generated: 06/08/2022 - 11:36:16
+ \ No newline at end of file diff --git a/textovhdl_summary.xml b/textovhdl_summary.xml new file mode 100644 index 0000000..fb30df9 --- /dev/null +++ b/textovhdl_summary.xml @@ -0,0 +1,10 @@ + + + + + + diff --git a/textovhdl_usage.xml b/textovhdl_usage.xml new file mode 100644 index 0000000..5367bc2 --- /dev/null +++ b/textovhdl_usage.xml @@ -0,0 +1,412 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/textovhdl_xst.xrpt b/textovhdl_xst.xrpt new file mode 100644 index 0000000..03df031 --- /dev/null +++ b/textovhdl_xst.xrpt @@ -0,0 +1,197 @@ + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + + + + + + + + + + +
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + +
+
+ + + + + + + + + + +
+
+ + + +
+
+
+
+
+
+
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+ + + + + + + + + + + + +
+
+
+
+
+ + + +
+ + + diff --git a/usage_statistics_webtalk.html b/usage_statistics_webtalk.html new file mode 100644 index 0000000..128fe4c --- /dev/null +++ b/usage_statistics_webtalk.html @@ -0,0 +1,661 @@ +Device Usage Statistics Report + +

Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Software Version and Target Device
Product Version:ISE:14.7 (WebPack) - P.20131013Target Family:Spartan6
OS Platform:NT64Target Device:xc6slx16
Project ID (random number)bd16c3ee05c44948bef10dae3c70184a.047E6D81914F4B9E9C732FAABBF95C82.1Target Package:csg324
Registration ID212425623_0_0_843Target Speed:-2
Date Generated2022-06-08T11:36:14Tool FlowISE
+ 
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
User Environment
OS NameMicrosoft Windows 7 , 64-bitOS ReleaseService Pack 1 (build 7601)
CPU NameIntel(R) Core(TM)2 Duo CPU T9600 @ 2.80GHzCPU Speed2793 MHz
OS NameMicrosoft Windows 7 , 64-bitOS ReleaseService Pack 1 (build 7601)
CPU NameIntel(R) Core(TM)2 Duo CPU T9600 @ 2.80GHzCPU Speed2793 MHz
+ 
+ + + + + + + + + + + + +
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
+Counters=2 +
    +
  • 24-bit up counter=1
    • +
  • 9-bit up counter=1
    • +
+ +Multiplexers=4 +
    +
  • 16-bit 2-to-1 multiplexer=4
    • +
+ +RAMs=1 +
    +
  • 8x4-bit single-port distributed Read Only RAM=1
    • +
+ +Registers=17 +
    +
  • Flip-Flops=17
    • +
+ +		 +MiscellaneousStatistics +
    +
  • AGG_BONDED_IO=17
    • +
  • AGG_IO=17
    • +
  • AGG_LOCED_IO=17
    • +
  • AGG_SLICE=11
    • +
  • NUM_BONDED_IOB=17
    • +
  • NUM_BSFULL=30
    • +
  • NUM_BSLUTONLY=1
    • +
  • NUM_BSUSED=31
    • +
  • NUM_BUFG=2
    • +
  • NUM_LOCED_IOB=17
    • +
  • NUM_LOGIC_O5ANDO6=4
    • +
  • NUM_LOGIC_O5ONLY=11
    • +
  • NUM_LOGIC_O6ONLY=14
    • +
  • NUM_LUT_RT_DRIVES_CARRY4=2
    • +
  • NUM_LUT_RT_EXO6=2
    • +
  • NUM_LUT_RT_O6=11
    • +
  • NUM_SLICEL=5
    • +
  • NUM_SLICEX=6
    • +
  • NUM_SLICE_CARRY4=5
    • +
  • NUM_SLICE_CONTROLSET=2
    • +
  • NUM_SLICE_CYINIT=48
    • +
  • NUM_SLICE_FF=32
    • +
  • NUM_SLICE_UNUSEDCTRL=1
    • +
  • NUM_UNUSABLE_FF_BELS=8
    • +
+ +		 +NetStatistics +
    +
  • NumNets_Active=69
    • +
  • NumNets_Vcc=1
    • +
  • NumNodesOfType_Active_BOUNCEACROSS=2
    • +
  • NumNodesOfType_Active_BOUNCEIN=6
    • +
  • NumNodesOfType_Active_BUFGOUT=2
    • +
  • NumNodesOfType_Active_BUFHINP2OUT=2
    • +
  • NumNodesOfType_Active_CLKPIN=10
    • +
  • NumNodesOfType_Active_CLKPINFEED=6
    • +
  • NumNodesOfType_Active_DOUBLE=8
    • +
  • NumNodesOfType_Active_GENERIC=4
    • +
  • NumNodesOfType_Active_GLOBAL=14
    • +
  • NumNodesOfType_Active_INPUT=5
    • +
  • NumNodesOfType_Active_IOBIN2OUT=3
    • +
  • NumNodesOfType_Active_IOBOUTPUT=3
    • +
  • NumNodesOfType_Active_LUTINPUT=86
    • +
  • NumNodesOfType_Active_OUTBOUND=33
    • +
  • NumNodesOfType_Active_OUTPUT=39
    • +
  • NumNodesOfType_Active_PADINPUT=3
    • +
  • NumNodesOfType_Active_PADOUTPUT=1
    • +
  • NumNodesOfType_Active_PINBOUNCE=19
    • +
  • NumNodesOfType_Active_PINFEED=102
    • +
  • NumNodesOfType_Active_QUAD=22
    • +
  • NumNodesOfType_Active_SINGLE=20
    • +
  • NumNodesOfType_Vcc_HVCCOUT=5
    • +
  • NumNodesOfType_Vcc_LUTINPUT=15
    • +
  • NumNodesOfType_Vcc_PINFEED=15
    • +
+ +SiteStatistics +
    +
  • BUFG-BUFGMUX=2
    • +
  • IOB-IOBM=10
    • +
  • IOB-IOBS=7
    • +
  • SLICEL-SLICEM=2
    • +
  • SLICEX-SLICEL=1
    • +
  • SLICEX-SLICEM=2
    • +
+ +		 +SiteSummary +
    +
  • BUFG=2
    • +
  • BUFG_BUFG=2
    • +
  • CARRY4=5
    • +
  • FF_SR=2
    • +
  • HARD0=2
    • +
  • IOB=17
    • +
  • IOB_IMUX=14
    • +
  • IOB_INBUF=14
    • +
  • IOB_OUTBUF=3
    • +
  • LUT5=15
    • +
  • LUT6=31
    • +
  • PAD=17
    • +
  • REG_SR=30
    • +
  • SLICEL=5
    • +
  • SLICEX=6
    • +
+ +
+ 
+ + + + + + + +
Configuration Data
+FF_SR +
    +
  • CK=[CK:0] [CK_INV:2]
    • +
  • SRINIT=[SRINIT0:2]
    • +
  • SYNC_ATTR=[ASYNC:2]
    • +
+		 + +IOB_OUTBUF +
    +
  • DRIVEATTRBOX=[12:3]
    • +
  • SLEW=[SLOW:3]
    • +
  • SUSPEND=[3STATE:3]
    • +
+		 + +REG_SR +
    +
  • CK=[CK:6] [CK_INV:24]
    • +
  • LATCH_OR_FF=[FF:30]
    • +
  • SRINIT=[SRINIT0:30]
    • +
  • SYNC_ATTR=[ASYNC:30]
    • +
+		 + +SLICEL +
    +
  • CLK=[CLK:2] [CLK_INV:3]
    • +
+ +SLICEX +
    +
  • CLK=[CLK:0] [CLK_INV:5]
    • +
+ +
+ 
+ + + + + + + +
Pin Data
+BUFG +
    +
  • I0=2
    • +
  • O=2
    • +
+ +BUFG_BUFG +
    +
  • I0=2
    • +
  • O=2
    • +
+ +CARRY4 +
    +
  • CIN=3
    • +
  • CO3=3
    • +
  • CYINIT=2
    • +
  • DI0=4
    • +
  • DI1=3
    • +
  • DI2=3
    • +
  • DI3=3
    • +
  • O0=5
    • +
  • O1=4
    • +
  • O2=3
    • +
  • O3=3
    • +
  • S0=5
    • +
  • S1=4
    • +
  • S2=3
    • +
  • S3=3
    • +
+ +FF_SR +
    +
  • CK=2
    • +
  • D=2
    • +
  • Q=2
    • +
+ +HARD0 +
    +
  • 0=2
    • +
+		 + +IOB +
    +
  • I=14
    • +
  • O=3
    • +
  • PAD=17
    • +
+ +IOB_IMUX +
    +
  • I=14
    • +
  • OUT=14
    • +
+ +IOB_INBUF +
    +
  • OUT=14
    • +
  • PAD=14
    • +
+ +IOB_OUTBUF +
    +
  • IN=3
    • +
  • OUT=3
    • +
+ +LUT5 +
    +
  • A3=2
    • +
  • A5=2
    • +
  • O5=15
    • +
+ +LUT6 +
    +
  • A1=5
    • +
  • A2=10
    • +
  • A3=11
    • +
  • A4=30
    • +
  • A5=14
    • +
  • A6=29
    • +
  • O6=31
    • +
+ +PAD +
    +
  • PAD=17
    • +
+ +REG_SR +
    +
  • CK=30
    • +
  • D=30
    • +
  • Q=30
    • +
+		 + +SLICEL +
    +
  • A4=5
    • +
  • A6=4
    • +
  • AQ=5
    • +
  • B4=4
    • +
  • B6=3
    • +
  • BQ=4
    • +
  • C4=3
    • +
  • C6=3
    • +
  • CIN=3
    • +
  • CLK=5
    • +
  • COUT=3
    • +
  • CQ=3
    • +
  • D4=3
    • +
  • D6=3
    • +
  • DQ=3
    • +
+ +SLICEX +
    +
  • A=1
    • +
  • A2=2
    • +
  • A3=3
    • +
  • A4=5
    • +
  • A5=4
    • +
  • A6=6
    • +
  • AMUX=1
    • +
  • AQ=5
    • +
  • B1=1
    • +
  • B2=2
    • +
  • B3=4
    • +
  • B4=4
    • +
  • B5=4
    • +
  • B6=4
    • +
  • BMUX=1
    • +
  • BQ=4
    • +
  • C1=2
    • +
  • C2=3
    • +
  • C3=3
    • +
  • C4=3
    • +
  • C5=3
    • +
  • C6=3
    • +
  • CLK=5
    • +
  • CQ=3
    • +
  • D1=2
    • +
  • D2=3
    • +
  • D3=3
    • +
  • D4=3
    • +
  • D5=3
    • +
  • D6=3
    • +
  • DQ=3
    • +
+		 + +
+ 
+ + +
Tool Usage
Command Line History
    +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-2 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
+ 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact232100000
bitgen343400000
map383300000
ngdbuild383800000
par333300000
trce333300000
xst686800000
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Project Statistics
PROP_Board=Spartan-6 SP601 Evaluation PlatformPROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTMLPROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked)PROP_ManualCompileOrderImp=false
PROP_PropSpecInProjFile=Store all valuesPROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changedPROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=falsePROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2022-06-08T11:31:57PROP_intWbtProjectID=047E6D81914F4B9E9C732FAABBF95C82
PROP_intWbtProjectIteration=1PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=NoPROP_AutoTop=true
PROP_DevFamily=Spartan6PROP_DevDevice=xc6slx16
PROP_DevFamilyPMName=spartan6PROP_DevPackage=csg324
PROP_Synthesis_Tool=XST (VHDL/Verilog)PROP_DevSpeed=-2
PROP_PreferredLanguage=VHDLFILE_UCF=1
FILE_VHDL=1
+ 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1NGDBUILD_NUM_BUFGP=1NGDBUILD_NUM_FD=15NGDBUILD_NUM_FD_1=17
NGDBUILD_NUM_GND=1NGDBUILD_NUM_INV=4NGDBUILD_NUM_LUT1=13NGDBUILD_NUM_LUT2=5
NGDBUILD_NUM_LUT3=1NGDBUILD_NUM_LUT4=1NGDBUILD_NUM_LUT5=5NGDBUILD_NUM_LUT6=5
NGDBUILD_NUM_MUXCY=13NGDBUILD_NUM_OBUF=3NGDBUILD_NUM_OBUFT=4NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=15
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=2NGDBUILD_NUM_FD=15NGDBUILD_NUM_FD_1=17NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=13NGDBUILD_NUM_IBUFG=1NGDBUILD_NUM_INV=4NGDBUILD_NUM_LUT1=13
NGDBUILD_NUM_LUT2=5NGDBUILD_NUM_LUT3=1NGDBUILD_NUM_LUT4=1NGDBUILD_NUM_LUT5=5
NGDBUILD_NUM_LUT6=5NGDBUILD_NUM_MUXCY=13NGDBUILD_NUM_OBUF=3NGDBUILD_NUM_OBUFT=4
NGDBUILD_NUM_VCC=1NGDBUILD_NUM_XORCY=15
+ 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj-ofn=<design_top>-ofmt=NGC-p=xc6slx16-2-csg324
-top=<design_top>-opt_mode=Speed-opt_level=1-power=NO
-iuc=NO-keep_hierarchy=No-netlist_hierarchy=As_Optimized-rtlview=Yes
-glob_opt=AllClockNets-read_cores=YES-write_timing_constraints=NO-cross_clock_analysis=NO
-bus_delimiter=<>-slice_utilization_ratio=100-bram_utilization_ratio=100-dsp_utilization_ratio=100
-reduce_control_sets=Auto-fsm_extract=YES-fsm_encoding=Auto-safe_implementation=No
-fsm_style=LUT-ram_extract=Yes-ram_style=Auto-rom_extract=Yes
-shreg_extract=YES-rom_style=Auto-auto_bram_packing=NO-resource_sharing=YES
-async_to_sync=NO-use_dsp48=Auto-iobuf=YES-max_fanout=100000
-bufg=16-register_duplication=YES-register_balancing=No-optimize_primitives=NO
-use_clock_enable=Auto-use_sync_set=Auto-use_sync_reset=Auto-iob=Auto
-equivalent_register_removal=YES-slice_utilization_ratio_maxmargin=5
+ 
diff --git a/webtalk.log b/webtalk.log new file mode 100644 index 0000000..1466675 --- /dev/null +++ b/webtalk.log @@ -0,0 +1,16 @@ +Release 14.7 - WebTalk (P.20131013) +Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. + +Project Information +-------------------- +ProjectID=047E6D81914F4B9E9C732FAABBF95C82 +ProjectIteration=1 + +WebTalk Summary +---------------- +INFO:WebTalk:2 - WebTalk is enabled. + +INFO:WebTalk:8 - WebTalk Install setting is ON. +INFO:WebTalk:6 - WebTalk User setting is ON. + +INFO:WebTalk:5 - C:/Users/Gabriel/Xilinx/Aula20220608/usage_statistics_webtalk.html WebTalk report has not been sent to Xilinx. Please check your network and proxy settings. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/14.7/ISE_DS/ISE/data/reports/webtalk_introduction.html diff --git a/webtalk_pn.xml b/webtalk_pn.xml new file mode 100644 index 0000000..6705b54 --- /dev/null +++ b/webtalk_pn.xml @@ -0,0 +1,43 @@ + + + + +
+ + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/xlnx_auto_0_xdb/cst.xbcd b/xlnx_auto_0_xdb/cst.xbcd new file mode 100644 index 0000000..bd5eae6 Binary files /dev/null and b/xlnx_auto_0_xdb/cst.xbcd differ diff --git a/xst/work/work.vdbl b/xst/work/work.vdbl new file mode 100644 index 0000000..86e69f6 Binary files /dev/null and b/xst/work/work.vdbl differ diff --git a/xst/work/work.vdbx b/xst/work/work.vdbx new file mode 100644 index 0000000..b0f7165 Binary files /dev/null and b/xst/work/work.vdbx differ