683 lines
32 KiB
Plaintext
683 lines
32 KiB
Plaintext
Release 14.7 - xst P.20131013 (nt64)
|
|
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
|
--> Parameter TMPDIR set to xst/projnav.tmp
|
|
|
|
|
|
Total REAL time to Xst completion: 0.00 secs
|
|
Total CPU time to Xst completion: 0.11 secs
|
|
|
|
--> Parameter xsthdpdir set to xst
|
|
|
|
|
|
Total REAL time to Xst completion: 0.00 secs
|
|
Total CPU time to Xst completion: 0.12 secs
|
|
|
|
--> Reading design: textovhdl.prj
|
|
|
|
TABLE OF CONTENTS
|
|
1) Synthesis Options Summary
|
|
2) HDL Parsing
|
|
3) HDL Elaboration
|
|
4) HDL Synthesis
|
|
4.1) HDL Synthesis Report
|
|
5) Advanced HDL Synthesis
|
|
5.1) Advanced HDL Synthesis Report
|
|
6) Low Level Synthesis
|
|
7) Partition Report
|
|
8) Design Summary
|
|
8.1) Primitive and Black Box Usage
|
|
8.2) Device utilization summary
|
|
8.3) Partition Resource Summary
|
|
8.4) Timing Report
|
|
8.4.1) Clock Information
|
|
8.4.2) Asynchronous Control Signals Information
|
|
8.4.3) Timing Summary
|
|
8.4.4) Timing Details
|
|
8.4.5) Cross Clock Domains Report
|
|
|
|
|
|
=========================================================================
|
|
* Synthesis Options Summary *
|
|
=========================================================================
|
|
---- Source Parameters
|
|
Input File Name : "textovhdl.prj"
|
|
Ignore Synthesis Constraint File : NO
|
|
|
|
---- Target Parameters
|
|
Output File Name : "textovhdl"
|
|
Output Format : NGC
|
|
Target Device : xc6slx16-2-csg324
|
|
|
|
---- Source Options
|
|
Top Module Name : textovhdl
|
|
Automatic FSM Extraction : YES
|
|
FSM Encoding Algorithm : Auto
|
|
Safe Implementation : No
|
|
FSM Style : LUT
|
|
RAM Extraction : Yes
|
|
RAM Style : Auto
|
|
ROM Extraction : Yes
|
|
Shift Register Extraction : YES
|
|
ROM Style : Auto
|
|
Resource Sharing : YES
|
|
Asynchronous To Synchronous : NO
|
|
Shift Register Minimum Size : 2
|
|
Use DSP Block : Auto
|
|
Automatic Register Balancing : No
|
|
|
|
---- Target Options
|
|
LUT Combining : Auto
|
|
Reduce Control Sets : Auto
|
|
Add IO Buffers : YES
|
|
Global Maximum Fanout : 100000
|
|
Add Generic Clock Buffer(BUFG) : 16
|
|
Register Duplication : YES
|
|
Optimize Instantiated Primitives : NO
|
|
Use Clock Enable : Auto
|
|
Use Synchronous Set : Auto
|
|
Use Synchronous Reset : Auto
|
|
Pack IO Registers into IOBs : Auto
|
|
Equivalent register Removal : YES
|
|
|
|
---- General Options
|
|
Optimization Goal : Speed
|
|
Optimization Effort : 1
|
|
Power Reduction : NO
|
|
Keep Hierarchy : No
|
|
Netlist Hierarchy : As_Optimized
|
|
RTL Output : Yes
|
|
Global Optimization : AllClockNets
|
|
Read Cores : YES
|
|
Write Timing Constraints : NO
|
|
Cross Clock Analysis : NO
|
|
Hierarchy Separator : /
|
|
Bus Delimiter : <>
|
|
Case Specifier : Maintain
|
|
Slice Utilization Ratio : 100
|
|
BRAM Utilization Ratio : 100
|
|
DSP48 Utilization Ratio : 100
|
|
Auto BRAM Packing : NO
|
|
Slice Utilization Ratio Delta : 5
|
|
|
|
=========================================================================
|
|
|
|
|
|
=========================================================================
|
|
* HDL Parsing *
|
|
=========================================================================
|
|
Parsing VHDL file "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" into library work
|
|
Parsing entity <textovhdl>.
|
|
Parsing architecture <comportamento> of entity <textovhdl>.
|
|
WARNING:HDLCompiler:946 - "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 44: Actual for formal port en is neither a static name nor a globally static expression
|
|
Parsing entity <CONTBCD_C>.
|
|
Parsing architecture <comportamento> of entity <contbcd_c>.
|
|
Parsing entity <display>.
|
|
Parsing architecture <comportamento> of entity <display>.
|
|
|
|
=========================================================================
|
|
* HDL Elaboration *
|
|
=========================================================================
|
|
|
|
Elaborating entity <textovhdl> (architecture <comportamento>) from library <work>.
|
|
|
|
Elaborating entity <CONTBCD_C> (architecture <comportamento>) from library <work>.
|
|
|
|
Elaborating entity <display> (architecture <comportamento>) from library <work>.
|
|
WARNING:HDLCompiler:1127 - "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 86: Assignment to clk25k ignored, since the identifier is never used
|
|
WARNING:HDLCompiler:1127 - "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 87: Assignment to clk621ms ignored, since the identifier is never used
|
|
WARNING:HDLCompiler:634 - "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" Line 20: Net <num7[3]> does not have a driver.
|
|
|
|
=========================================================================
|
|
* HDL Synthesis *
|
|
=========================================================================
|
|
|
|
Synthesizing Unit <textovhdl>.
|
|
Related source file is "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd".
|
|
WARNING:Xst:647 - Input <BUT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <DIPSW> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
INFO:Xst:3210 - "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd" line 48: Output port <ENOUT> of the instance <UC4> is unconnected or connected to loadless signal.
|
|
Always blocking tristate driving signal <GPIO<7>> is removed.
|
|
Always blocking tristate driving signal <GPIO<6>> is removed.
|
|
Always blocking tristate driving signal <GPIO<5>> is removed.
|
|
Always blocking tristate driving signal <GPIO<4>> is removed.
|
|
Always blocking tristate driving signal <GPIO<3>> is removed.
|
|
Always blocking tristate driving signal <GPIO<2>> is removed.
|
|
Always blocking tristate driving signal <GPIO<1>> is removed.
|
|
Always blocking tristate driving signal <GPIO<0>> is removed.
|
|
WARNING:Xst:653 - Signal <num7> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <num6> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <num5> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <num4> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <num3> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <num2> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <num1> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <num0> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
Found 1-bit register for signal <toggleled>.
|
|
Found 4-bit register for signal <bLeds>.
|
|
Found 24-bit register for signal <cont100k>.
|
|
Found 24-bit register for signal <contaux>.
|
|
Found 2-bit register for signal <ffmicro<18:17>>.
|
|
Found 24-bit adder for signal <contaux[23]_GND_5_o_add_9_OUT> created at line 81.
|
|
Found 24-bit subtractor for signal <GND_5_o_GND_5_o_sub_8_OUT<23:0>> created at line 79.
|
|
Summary:
|
|
inferred 2 Adder/Subtractor(s).
|
|
inferred 55 D-type flip-flop(s).
|
|
Unit <textovhdl> synthesized.
|
|
|
|
Synthesizing Unit <CONTBCD_C>.
|
|
Related source file is "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd".
|
|
Found 4-bit register for signal <cont>.
|
|
Found 4-bit adder for signal <cont[3]_UP_add_3_OUT> created at line 126.
|
|
Summary:
|
|
inferred 1 Adder/Subtractor(s).
|
|
inferred 4 D-type flip-flop(s).
|
|
inferred 3 Multiplexer(s).
|
|
Unit <CONTBCD_C> synthesized.
|
|
|
|
Synthesizing Unit <display>.
|
|
Related source file is "C:\Users\Gabriel\Xilinx\Aula20220608\textovhdl.vhd".
|
|
Found 1-bit register for signal <configur>.
|
|
Found 16-bit register for signal <palavra>.
|
|
Found 9-bit register for signal <EN>.
|
|
Found 9-bit adder for signal <EN[8]_GND_19_o_add_37_OUT> created at line 205.
|
|
Found 8x4-bit Read Only RAM for signal <proxdisplay>
|
|
Summary:
|
|
inferred 1 RAM(s).
|
|
inferred 1 Adder/Subtractor(s).
|
|
inferred 26 D-type flip-flop(s).
|
|
inferred 4 Multiplexer(s).
|
|
Unit <display> synthesized.
|
|
|
|
=========================================================================
|
|
HDL Synthesis Report
|
|
|
|
Macro Statistics
|
|
# RAMs : 1
|
|
8x4-bit single-port Read Only RAM : 1
|
|
# Adders/Subtractors : 8
|
|
24-bit adder : 1
|
|
24-bit subtractor : 1
|
|
4-bit adder : 5
|
|
9-bit adder : 1
|
|
# Registers : 13
|
|
1-bit register : 2
|
|
16-bit register : 1
|
|
2-bit register : 1
|
|
24-bit register : 2
|
|
4-bit register : 6
|
|
9-bit register : 1
|
|
# Multiplexers : 19
|
|
1-bit 2-to-1 multiplexer : 5
|
|
16-bit 2-to-1 multiplexer : 4
|
|
4-bit 2-to-1 multiplexer : 10
|
|
|
|
=========================================================================
|
|
|
|
=========================================================================
|
|
* Advanced HDL Synthesis *
|
|
=========================================================================
|
|
|
|
WARNING:Xst:2677 - Node <bLeds_1> of sequential type is unconnected in block <textovhdl>.
|
|
WARNING:Xst:2677 - Node <bLeds_2> of sequential type is unconnected in block <textovhdl>.
|
|
WARNING:Xst:2677 - Node <bLeds_3> of sequential type is unconnected in block <textovhdl>.
|
|
|
|
Synthesizing (advanced) Unit <display>.
|
|
The following registers are absorbed into counter <EN>: 1 register on signal <EN>.
|
|
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_proxdisplay> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
|
|
-----------------------------------------------------------------------
|
|
| ram_type | Distributed | |
|
|
-----------------------------------------------------------------------
|
|
| Port A |
|
|
| aspect ratio | 8-word x 4-bit | |
|
|
| weA | connected to signal <GND> | high |
|
|
| addrA | connected to signal <EN<7:5>> | |
|
|
| diA | connected to signal <GND> | |
|
|
| doA | connected to signal <proxdisplay> | |
|
|
-----------------------------------------------------------------------
|
|
Unit <display> synthesized (advanced).
|
|
|
|
Synthesizing (advanced) Unit <textovhdl>.
|
|
The following registers are absorbed into counter <cont100k>: 1 register on signal <cont100k>.
|
|
The following registers are absorbed into counter <contaux>: 1 register on signal <contaux>.
|
|
Unit <textovhdl> synthesized (advanced).
|
|
WARNING:Xst:2677 - Node <bLeds_1> of sequential type is unconnected in block <textovhdl>.
|
|
WARNING:Xst:2677 - Node <bLeds_2> of sequential type is unconnected in block <textovhdl>.
|
|
WARNING:Xst:2677 - Node <bLeds_3> of sequential type is unconnected in block <textovhdl>.
|
|
|
|
=========================================================================
|
|
Advanced HDL Synthesis Report
|
|
|
|
Macro Statistics
|
|
# RAMs : 1
|
|
8x4-bit single-port distributed Read Only RAM : 1
|
|
# Adders/Subtractors : 5
|
|
4-bit adder : 5
|
|
# Counters : 3
|
|
24-bit down counter : 1
|
|
24-bit up counter : 1
|
|
9-bit up counter : 1
|
|
# Registers : 41
|
|
Flip-Flops : 41
|
|
# Multiplexers : 19
|
|
1-bit 2-to-1 multiplexer : 5
|
|
16-bit 2-to-1 multiplexer : 4
|
|
4-bit 2-to-1 multiplexer : 10
|
|
|
|
=========================================================================
|
|
|
|
=========================================================================
|
|
* Low Level Synthesis *
|
|
=========================================================================
|
|
WARNING:Xst:2677 - Node <contaux_6> of sequential type is unconnected in block <textovhdl>.
|
|
WARNING:Xst:2677 - Node <contaux_7> of sequential type is unconnected in block <textovhdl>.
|
|
WARNING:Xst:2677 - Node <contaux_8> of sequential type is unconnected in block <textovhdl>.
|
|
WARNING:Xst:2677 - Node <contaux_9> of sequential type is unconnected in block <textovhdl>.
|
|
WARNING:Xst:2677 - Node <contaux_10> of sequential type is unconnected in block <textovhdl>.
|
|
WARNING:Xst:2677 - Node <contaux_11> of sequential type is unconnected in block <textovhdl>.
|
|
WARNING:Xst:2677 - Node <contaux_12> of sequential type is unconnected in block <textovhdl>.
|
|
WARNING:Xst:2677 - Node <contaux_13> of sequential type is unconnected in block <textovhdl>.
|
|
WARNING:Xst:2677 - Node <contaux_14> of sequential type is unconnected in block <textovhdl>.
|
|
WARNING:Xst:2677 - Node <contaux_15> of sequential type is unconnected in block <textovhdl>.
|
|
WARNING:Xst:2677 - Node <contaux_16> of sequential type is unconnected in block <textovhdl>.
|
|
WARNING:Xst:2677 - Node <contaux_17> of sequential type is unconnected in block <textovhdl>.
|
|
WARNING:Xst:2677 - Node <contaux_18> of sequential type is unconnected in block <textovhdl>.
|
|
WARNING:Xst:2677 - Node <contaux_19> of sequential type is unconnected in block <textovhdl>.
|
|
WARNING:Xst:2677 - Node <contaux_20> of sequential type is unconnected in block <textovhdl>.
|
|
WARNING:Xst:2677 - Node <contaux_21> of sequential type is unconnected in block <textovhdl>.
|
|
WARNING:Xst:2677 - Node <contaux_22> of sequential type is unconnected in block <textovhdl>.
|
|
WARNING:Xst:2677 - Node <contaux_23> of sequential type is unconnected in block <textovhdl>.
|
|
|
|
Optimizing unit <textovhdl> ...
|
|
|
|
Optimizing unit <CONTBCD_C> ...
|
|
|
|
Optimizing unit <display> ...
|
|
|
|
Mapping all equations...
|
|
Building and optimizing final netlist ...
|
|
Found area constraint ratio of 100 (+ 5) on block textovhdl, actual ratio is 1.
|
|
FlipFlop cont100k_8 has been replicated 1 time(s)
|
|
|
|
Final Macro Processing ...
|
|
|
|
=========================================================================
|
|
Final Register Report
|
|
|
|
Macro Statistics
|
|
# Registers : 81
|
|
Flip-Flops : 81
|
|
|
|
=========================================================================
|
|
|
|
=========================================================================
|
|
* Partition Report *
|
|
=========================================================================
|
|
|
|
Partition Implementation Status
|
|
-------------------------------
|
|
|
|
No Partitions were found in this design.
|
|
|
|
-------------------------------
|
|
|
|
=========================================================================
|
|
* Design Summary *
|
|
=========================================================================
|
|
|
|
Top Level Output File Name : textovhdl.ngc
|
|
|
|
Primitive and Black Box Usage:
|
|
------------------------------
|
|
# BELS : 213
|
|
# GND : 1
|
|
# INV : 31
|
|
# LUT1 : 14
|
|
# LUT2 : 7
|
|
# LUT3 : 9
|
|
# LUT4 : 4
|
|
# LUT5 : 43
|
|
# LUT6 : 28
|
|
# MUXCY : 36
|
|
# VCC : 1
|
|
# XORCY : 39
|
|
# FlipFlops/Latches : 81
|
|
# FD : 44
|
|
# FD_1 : 4
|
|
# FDCE : 20
|
|
# FDR_1 : 13
|
|
# Clock Buffers : 3
|
|
# BUFG : 2
|
|
# BUFGP : 1
|
|
# IO Buffers : 8
|
|
# IBUF : 1
|
|
# OBUF : 7
|
|
|
|
Device utilization summary:
|
|
---------------------------
|
|
|
|
Selected Device : 6slx16csg324-2
|
|
|
|
|
|
Slice Logic Utilization:
|
|
Number of Slice Registers: 81 out of 18224 0%
|
|
Number of Slice LUTs: 136 out of 9112 1%
|
|
Number used as Logic: 136 out of 9112 1%
|
|
|
|
Slice Logic Distribution:
|
|
Number of LUT Flip Flop pairs used: 138
|
|
Number with an unused Flip Flop: 57 out of 138 41%
|
|
Number with an unused LUT: 2 out of 138 1%
|
|
Number of fully used LUT-FF pairs: 79 out of 138 57%
|
|
Number of unique control sets: 9
|
|
|
|
IO Utilization:
|
|
Number of IOs: 21
|
|
Number of bonded IOBs: 9 out of 232 3%
|
|
|
|
Specific Feature Utilization:
|
|
Number of BUFG/BUFGCTRLs: 3 out of 16 18%
|
|
|
|
---------------------------
|
|
Partition Resource Summary:
|
|
---------------------------
|
|
|
|
No Partitions were found in this design.
|
|
|
|
---------------------------
|
|
|
|
|
|
=========================================================================
|
|
Timing Report
|
|
|
|
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
|
|
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
|
|
GENERATED AFTER PLACE-and-ROUTE.
|
|
|
|
Clock Information:
|
|
------------------
|
|
-----------------------------------+------------------------+-------+
|
|
Clock Signal | Clock buffer(FF name) | Load |
|
|
-----------------------------------+------------------------+-------+
|
|
cont100k_8 | BUFG | 23 |
|
|
toggleled | NONE(bLeds_0) | 1 |
|
|
CLK27MHz | BUFGP | 31 |
|
|
contaux_5 | BUFG | 26 |
|
|
-----------------------------------+------------------------+-------+
|
|
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
|
|
|
|
Asynchronous Control Signals Information:
|
|
----------------------------------------
|
|
No asynchronous control signals found in this design
|
|
|
|
Timing Summary:
|
|
---------------
|
|
Speed Grade: -2
|
|
|
|
Minimum period: 4.284ns (Maximum Frequency: 233.427MHz)
|
|
Minimum input arrival time before clock: 3.096ns
|
|
Maximum output required time after clock: 7.122ns
|
|
Maximum combinational path delay: 5.549ns
|
|
|
|
Timing Details:
|
|
---------------
|
|
All values displayed in nanoseconds (ns)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default period analysis for Clock 'cont100k_8'
|
|
Clock period: 4.284ns (frequency: 233.427MHz)
|
|
Total number of paths / destination ports: 327 / 43
|
|
-------------------------------------------------------------------------
|
|
Delay: 4.284ns (Levels of Logic = 3)
|
|
Source: UC2/cont_0 (FF)
|
|
Destination: UC3/cont_3 (FF)
|
|
Source Clock: cont100k_8 rising
|
|
Destination Clock: cont100k_8 rising
|
|
|
|
Data Path: UC2/cont_0 to UC3/cont_3
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FDCE:C->Q 9 0.525 1.252 UC2/cont_0 (UC2/cont_0)
|
|
LUT4:I0->O 5 0.254 0.841 UC1/Mmux_ENOUT11_SW0 (N10)
|
|
LUT5:I4->O 2 0.254 0.834 UC2/Mmux_ENOUT11_rstpot (UC2/Mmux_ENOUT11_rstpot)
|
|
LUT3:I1->O 1 0.250 0.000 UC3/cont_1_dpot (UC3/cont_1_dpot)
|
|
FDCE:D 0.074 UC3/cont_1
|
|
----------------------------------------
|
|
Total 4.284ns (1.357ns logic, 2.927ns route)
|
|
(31.7% logic, 68.3% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default period analysis for Clock 'toggleled'
|
|
Clock period: 2.260ns (frequency: 442.478MHz)
|
|
Total number of paths / destination ports: 1 / 1
|
|
-------------------------------------------------------------------------
|
|
Delay: 2.260ns (Levels of Logic = 1)
|
|
Source: bLeds_0 (FF)
|
|
Destination: bLeds_0 (FF)
|
|
Source Clock: toggleled rising
|
|
Destination Clock: toggleled rising
|
|
|
|
Data Path: bLeds_0 to bLeds_0
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FD:C->Q 2 0.525 0.725 bLeds_0 (bLeds_0)
|
|
INV:I->O 1 0.255 0.681 bLeds[3]_inv_4_OUT<0>1_INV_0 (bLeds[3]_inv_4_OUT<0>)
|
|
FD:D 0.074 bLeds_0
|
|
----------------------------------------
|
|
Total 2.260ns (0.854ns logic, 1.406ns route)
|
|
(37.8% logic, 62.2% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default period analysis for Clock 'CLK27MHz'
|
|
Clock period: 3.944ns (frequency: 253.550MHz)
|
|
Total number of paths / destination ports: 930 / 31
|
|
-------------------------------------------------------------------------
|
|
Delay: 3.944ns (Levels of Logic = 2)
|
|
Source: cont100k_1 (FF)
|
|
Destination: cont100k_0 (FF)
|
|
Source Clock: CLK27MHz rising
|
|
Destination Clock: CLK27MHz rising
|
|
|
|
Data Path: cont100k_1 to cont100k_0
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FD:C->Q 2 0.525 1.181 cont100k_1 (cont100k_1)
|
|
LUT6:I0->O 24 0.254 1.656 cont100k[23]_GND_5_o_equal_7_o<23>3 (cont100k[23]_GND_5_o_equal_7_o<23>2)
|
|
LUT5:I1->O 1 0.254 0.000 cont100k_0_rstpot (cont100k_0_rstpot)
|
|
FD:D 0.074 cont100k_0
|
|
----------------------------------------
|
|
Total 3.944ns (1.107ns logic, 2.837ns route)
|
|
(28.1% logic, 71.9% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default period analysis for Clock 'contaux_5'
|
|
Clock period: 3.741ns (frequency: 267.308MHz)
|
|
Total number of paths / destination ports: 183 / 39
|
|
-------------------------------------------------------------------------
|
|
Delay: 3.741ns (Levels of Logic = 1)
|
|
Source: UDISP/EN_6 (FF)
|
|
Destination: UDISP/palavra_15 (FF)
|
|
Source Clock: contaux_5 falling
|
|
Destination Clock: contaux_5 falling
|
|
|
|
Data Path: UDISP/EN_6 to UDISP/palavra_15
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FD:C->Q 9 0.525 1.406 UDISP/EN_6 (UDISP/EN_6)
|
|
LUT5:I0->O 13 0.254 1.097 UDISP/_n01261 (UDISP/_n0126)
|
|
FDR_1:R 0.459 UDISP/palavra_1
|
|
----------------------------------------
|
|
Total 3.741ns (1.238ns logic, 2.503ns route)
|
|
(33.1% logic, 66.9% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default OFFSET IN BEFORE for Clock 'cont100k_8'
|
|
Total number of paths / destination ports: 20 / 20
|
|
-------------------------------------------------------------------------
|
|
Offset: 3.096ns (Levels of Logic = 1)
|
|
Source: GPIO<6> (PAD)
|
|
Destination: UC4/cont_3 (FF)
|
|
Destination Clock: cont100k_8 rising
|
|
|
|
Data Path: GPIO<6> to UC4/cont_3
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
IBUF:I->O 21 1.328 1.309 GPIO_6_IBUF (LEDS_3_OBUF)
|
|
FDCE:CLR 0.459 UC4/cont_0
|
|
----------------------------------------
|
|
Total 3.096ns (1.787ns logic, 1.309ns route)
|
|
(57.7% logic, 42.3% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'cont100k_8'
|
|
Total number of paths / destination ports: 21 / 2
|
|
-------------------------------------------------------------------------
|
|
Offset: 7.122ns (Levels of Logic = 3)
|
|
Source: UC0/cont_2 (FF)
|
|
Destination: LEDS<1> (PAD)
|
|
Source Clock: cont100k_8 rising
|
|
|
|
Data Path: UC0/cont_2 to LEDS<1>
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FDCE:C->Q 7 0.525 1.340 UC0/cont_2 (UC0/cont_2)
|
|
LUT6:I1->O 2 0.254 1.156 andcontzero1 (andcontzero)
|
|
LUT5:I0->O 1 0.254 0.681 andcontzero4 (LEDS_1_OBUF)
|
|
OBUF:I->O 2.912 LEDS_1_OBUF (LEDS<1>)
|
|
----------------------------------------
|
|
Total 7.122ns (3.945ns logic, 3.177ns route)
|
|
(55.4% logic, 44.6% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'toggleled'
|
|
Total number of paths / destination ports: 1 / 1
|
|
-------------------------------------------------------------------------
|
|
Offset: 4.162ns (Levels of Logic = 1)
|
|
Source: bLeds_0 (FF)
|
|
Destination: LEDS<0> (PAD)
|
|
Source Clock: toggleled rising
|
|
|
|
Data Path: bLeds_0 to LEDS<0>
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FD:C->Q 2 0.525 0.725 bLeds_0 (bLeds_0)
|
|
OBUF:I->O 2.912 LEDS_0_OBUF (LEDS<0>)
|
|
----------------------------------------
|
|
Total 4.162ns (3.437ns logic, 0.725ns route)
|
|
(82.6% logic, 17.4% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'contaux_5'
|
|
Total number of paths / destination ports: 2 / 2
|
|
-------------------------------------------------------------------------
|
|
Offset: 5.633ns (Levels of Logic = 2)
|
|
Source: UDISP/EN_4 (FF)
|
|
Destination: GPIO<1> (PAD)
|
|
Source Clock: contaux_5 falling
|
|
|
|
Data Path: UDISP/EN_4 to GPIO<1>
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FD:C->Q 19 0.525 1.260 UDISP/EN_4 (UDISP/EN_4)
|
|
INV:I->O 1 0.255 0.681 UDISP/CS1_INV_0 (GPIO_1_OBUF)
|
|
OBUF:I->O 2.912 GPIO_1_OBUF (GPIO<1>)
|
|
----------------------------------------
|
|
Total 5.633ns (3.692ns logic, 1.941ns route)
|
|
(65.5% logic, 34.5% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK27MHz'
|
|
Total number of paths / destination ports: 1 / 1
|
|
-------------------------------------------------------------------------
|
|
Offset: 4.162ns (Levels of Logic = 1)
|
|
Source: contaux_5 (FF)
|
|
Destination: GPIO<0> (PAD)
|
|
Source Clock: CLK27MHz rising
|
|
|
|
Data Path: contaux_5 to GPIO<0>
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FD:C->Q 2 0.525 0.725 contaux_5 (contaux_5)
|
|
OBUF:I->O 2.912 GPIO_0_OBUF (GPIO<0>)
|
|
----------------------------------------
|
|
Total 4.162ns (3.437ns logic, 0.725ns route)
|
|
(82.6% logic, 17.4% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default path analysis
|
|
Total number of paths / destination ports: 1 / 1
|
|
-------------------------------------------------------------------------
|
|
Delay: 5.549ns (Levels of Logic = 2)
|
|
Source: GPIO<6> (PAD)
|
|
Destination: LEDS<3> (PAD)
|
|
|
|
Data Path: GPIO<6> to LEDS<3>
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
IBUF:I->O 21 1.328 1.309 GPIO_6_IBUF (LEDS_3_OBUF)
|
|
OBUF:I->O 2.912 LEDS_3_OBUF (LEDS<3>)
|
|
----------------------------------------
|
|
Total 5.549ns (4.240ns logic, 1.309ns route)
|
|
(76.4% logic, 23.6% route)
|
|
|
|
=========================================================================
|
|
|
|
Cross Clock Domains Report:
|
|
--------------------------
|
|
|
|
Clock to Setup on destination clock CLK27MHz
|
|
---------------+---------+---------+---------+---------+
|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
|
---------------+---------+---------+---------+---------+
|
|
CLK27MHz | 3.944| | | |
|
|
---------------+---------+---------+---------+---------+
|
|
|
|
Clock to Setup on destination clock cont100k_8
|
|
---------------+---------+---------+---------+---------+
|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
|
---------------+---------+---------+---------+---------+
|
|
cont100k_8 | 4.284| | | |
|
|
---------------+---------+---------+---------+---------+
|
|
|
|
Clock to Setup on destination clock contaux_5
|
|
---------------+---------+---------+---------+---------+
|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
|
---------------+---------+---------+---------+---------+
|
|
contaux_5 | | | 3.741| |
|
|
---------------+---------+---------+---------+---------+
|
|
|
|
Clock to Setup on destination clock toggleled
|
|
---------------+---------+---------+---------+---------+
|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
|
---------------+---------+---------+---------+---------+
|
|
toggleled | 2.260| | | |
|
|
---------------+---------+---------+---------+---------+
|
|
|
|
=========================================================================
|
|
|
|
|
|
Total REAL time to Xst completion: 7.00 secs
|
|
Total CPU time to Xst completion: 6.97 secs
|
|
|
|
-->
|
|
|
|
Total memory usage is 258824 kilobytes
|
|
|
|
Number of errors : 0 ( 0 filtered)
|
|
Number of warnings : 38 ( 0 filtered)
|
|
Number of infos : 3 ( 0 filtered)
|
|
|