70 lines
2.9 KiB
Plaintext
70 lines
2.9 KiB
Plaintext
--------------------------------------------------------------------------------
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Release 14.7 Trace (nt64)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 2
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-n 3 -fastpaths -xml textovhdl.twx textovhdl.ncd -o textovhdl.twr textovhdl.pcf
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-ucf restricoes.ucf
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Design file: textovhdl.ncd
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Physical constraint file: textovhdl.pcf
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Device,package,speed: xc6slx16,csg324,C,-2 (PRODUCTION 1.23 2013-10-13)
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Report level: verbose report
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Environment Variable Effect
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-------------------- ------
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NONE No environment variables were set
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--------------------------------------------------------------------------------
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
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INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
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option. All paths that are not constrained will be reported in the
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unconstrained paths section(s) of the report.
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INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
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a 50 Ohm transmission line loading model. For the details of this model,
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and for more information on accounting for different loading conditions,
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please see the device datasheet.
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Data Sheet report:
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-----------------
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All values displayed in nanoseconds (ns)
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Clock CLK27MHz to Pad
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------------+-----------------+------------+-----------------+------------+------------------+--------+
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|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
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Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
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------------+-----------------+------------+-----------------+------------+------------------+--------+
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GPIO<0> | 9.716(R)| SLOW | 4.139(R)| FAST |CLK27MHz_BUFGP | 0.000|
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------------+-----------------+------------+-----------------+------------+------------------+--------+
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Clock to Setup on destination clock CLK27MHz
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---------------+---------+---------+---------+---------+
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| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
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Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
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---------------+---------+---------+---------+---------+
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CLK27MHz | 3.836| | | |
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---------------+---------+---------+---------+---------+
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Pad to Pad
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---------------+---------------+---------+
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Source Pad |Destination Pad| Delay |
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---------------+---------------+---------+
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GPIO<6> |LEDS<3> | 9.433|
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---------------+---------------+---------+
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Analysis completed Wed Jun 08 12:53:12 2022
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--------------------------------------------------------------------------------
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Trace Settings:
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-------------------------
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Trace Settings
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Peak Memory Usage: 219 MB
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