IME/XC3S400
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Gabriel Lima 68da6f5460 Merge pull request 'TXing' (#2) from feature/control_logic into develop 
Reviewed-on: #2
2023-05-29 11:08:39 -03:00
.gitignore
Initial commit
2023-02-07 18:59:37 -03:00
ALU_P379.vhdl
Implement Zero and carry flags in ALU (untested)
2023-02-27 16:18:27 -03:00
constraints.ucf
TXing
2023-05-29 11:00:35 -03:00
main.vhdl
TXing
2023-05-29 11:00:35 -03:00
Opcode descriptions.txt
TXing
2023-05-29 11:00:35 -03:00
program_counter.vhdl
Implemented program counter (untested)
2023-02-27 15:25:31 -03:00
README.md
Initial commit
2023-02-07 18:59:37 -03:00
Registers.vhdl
MOVing
2023-03-20 09:36:03 -03:00
sevseg.vhdl
SevSeg with example
2023-02-07 21:53:39 -03:00
UART.vhdl
TXing
2023-05-29 11:00:35 -03:00
XC3S400.xise
TXing
2023-05-29 11:00:35 -03:00

README.md

XC3S400

Digilent Nexys XC3S400 FPGA development board Xilinx ISE project

Description
Digilent Nexys XC3S400 FPGA development board Xilinx ISE project
Readme 126 KiB
Languages
VHDL 100%