66 lines
1.5 KiB
VHDL
66 lines
1.5 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 09:16:26 05/15/2023
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-- Design Name:
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-- Module Name: UART_TX - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity UART_TX is
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Port ( DATA : in STD_LOGIC_VECTOR (7 downto 0);
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LOAD : in STD_LOGIC;
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CLK : in STD_LOGIC;
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BUSY : out STD_LOGIC;
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TX_PIN : out STD_LOGIC);
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end UART_TX;
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architecture Behavioral of UART_TX is
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signal sending: std_logic_vector (10 downto 0);
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signal to_send: std_logic_vector (9 downto 0);
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begin
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TX_PIN <= sending(0);
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process(CLK, LOAD)
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begin
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if(LOAD = '1') then
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--começa novo envio
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sending <= '1' & DATA & '0' & '1';
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BUSY <= '1';
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elsif(CLK'event and CLK = '1') then
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--envia próximo bit
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sending <= '1' & sending(10 downto 1);
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if(sending = "11111111111") then
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BUSY <= '0';
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end if;
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end if;
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end process;
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end Behavioral;
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