EloDigi/Aula20220603
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This commit is contained in:
Gabriel Lima
2022-06-03 13:04:43 -03:00
parent db9585551b
commit 5446987391
2 changed files with 17 additions and 1 deletions
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3
_xmsgs/pn_parser.xmsgs
View File

@@ -11,5 +11,8 @@
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;C:/Users/Gabriel/Xilinx/Aula20220603/textovhdl.vhd&quot; into library work</arg>
</msg>
<msg type="error" file="ProjectMgmt" num="806" >&quot;<arg fmt="%s" index="1">C:/Users/Gabriel/Xilinx/Aula20220603/textovhdl.vhd</arg>&quot; Line <arg fmt="%d" index="2">119</arg>. <arg fmt="%s" index="3">Syntax error near &quot;:&quot;.</arg>
</msg>
</messages>

15
textovhdl.vhd
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@@ -32,7 +32,7 @@ signal clkcontbits, clrcontbits, contbitsigual32: std_logic;
signal EOTX8: std_logic_vector (1 downto 0);
signal EOTX12: std_logic_vector (2 downto 0);
signal clr12bits, Q900, Q450, Q55, Q165: std_logic;
signal loadshift, clkshift, Q0, outired, clk37915: std_logic;
signal loadshift, clkshift, Q0, outir, clk37915: std_logic;
signal proxTX, atualTX: std_logic_vector(3 downto 0);
signal proxshift32, atualshift32: std_logic_vector (31 downto 0);
signal cont37915: std_logic_vector(23 downto 0);
@@ -96,6 +96,18 @@ begin
end if;
end process;
proxTX <= "000"&BUT(0) when atualTX="0000" else
"00"&(not BUT(0))&'1' when atualTX="0001" else
"001"&Q900 when atualTX="0011" else
"0110" when atualTX="0010" else
"011"&(not Q450) when atualTX="0110" else
@@ -180,6 +192,7 @@ GPIO(1) <= cs;
GPIO(2) <= din;
S_IR <= GPIO(4);
LEDS <= num7;
GPIO(5) <= CLK37915 and OUTIR;
end comportamento;