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clock de 37915

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This commit is contained in:
Gabriel Lima
2022-06-03 12:53:31 -03:00
parent fd695de3f7
commit db9585551b
1 changed files with 9 additions and 3 deletions
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12
textovhdl.vhd
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@@ -35,6 +35,7 @@ signal clr12bits, Q900, Q450, Q55, Q165: std_logic;
signal loadshift, clkshift, Q0, outired, clk37915: std_logic;
signal proxTX, atualTX: std_logic_vector(3 downto 0);
signal proxshift32, atualshift32: std_logic_vector (31 downto 0);
signal cont37915: std_logic_vector(23 downto 0);
component display port( NUM7, NUM6, NUM5, NUM4, NUM3, NUM2, NUM1, NUM0: in std_logic_vector(3 downto 0);
CLK: in std_logic;
@@ -83,10 +84,15 @@ end process;
process(CLK27MHz)
begin
if(CLK27MHz'event and CLK27MHz = '1') then
if (cont100k = "000000000000000000000000") then cont100k <= "000000000000000100001101";
else cont100k <= cont100k-"000000000000000000000001";
if (cont37915 = "000000000000000000000000") then cont37915 <= "0000_0000_0000_0001_0110_0011";
else cont37915 <= cont37915-"000000000000000000000001";
end if;
contaux <= contaux + "000000000000000000000001";
end if;
end process;
process(cont37915(8))
begin
if(cont37915(8)'event and cont37915(8) = '1') then
clk37915 <= not clk37915;
end if;
end process;