EloDigi/Aula20220603
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Contador de 8 bits

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This commit is contained in:
Gabriel Lima
2022-06-03 12:05:05 -03:00
parent c76cdda09b
commit 42285a2837
1 changed files with 6 additions and 3 deletions
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textovhdl.vhd
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@@ -29,6 +29,8 @@ signal proxnum7: std_logic_vector( 3 downto 0);
signal cont32TXIR: std_logic_vector(7 downto 0);
signal conttime: std_logic_vector(11 downto 0);
signal clkcontbits, clrcontbits, contbitsigual32: std_logic;
signal EOTX8: std_logic_vector (1 downto 0);
signal EOTX12: std_logic_vector (2 downto 0);
signal clr12bits, Q900, Q450, Q55, Q165: std_logic;
signal loadshift, clkshift, Q0, outired, clk37915: std_logic;
signal proxTX, atualTX: std_logic_vector(3 downto 0);
@@ -50,10 +52,11 @@ begin
GPIO <= "ZZZZZZZZ";
LEDS <= "ZZZZ";
UT0: CONTBCD_C port map(CLK => CLK100k, CLR => CLR_cont_S, UP => '1', EN => (S_IR and not Q8ms), ENOUT => EO(0), Q => num0);
UT1: CONTBCD_C port map(CLK => CLK100k, CLR => CLR_cont_S, UP => '1', EN => EO(0), ENOUT => EO(1), Q => num1);
--contador 8 bits de transmiss<73>o, conta at<61> 32
UT0: CONTBCD_C port map(CLK => clkcontbits, CLR => clrcontbits, UP => '1', EN => 1, ENOUT => EOTX8(0), Q => cont32TXIR(3 downto 0));
UT1: CONTBCD_C port map(CLK => clkcontbits, CLR => clrcontbits, UP => '1', EN => EOTX8(0), ENOUT => EOTX8(1), Q => cont32TXIR(7 downto 4));
contbitsigual32 <= '1' when cont32TXIR="00110010" else '0';