diff --git a/textovhdl.vhd b/textovhdl.vhd
index 91c35f6..f3dd66d 100644
--- a/textovhdl.vhd
+++ b/textovhdl.vhd
@@ -29,6 +29,8 @@ signal proxnum7: std_logic_vector( 3 downto 0);
 signal cont32TXIR: std_logic_vector(7 downto 0);
 signal conttime: std_logic_vector(11 downto 0);
 signal clkcontbits, clrcontbits, contbitsigual32: std_logic;
+signal EOTX8: std_logic_vector (1 downto 0);
+signal EOTX12: std_logic_vector (2 downto 0);
 signal clr12bits, Q900, Q450, Q55, Q165: std_logic;
 signal loadshift, clkshift, Q0, outired, clk37915: std_logic;
 signal proxTX, atualTX: std_logic_vector(3 downto 0);
@@ -50,10 +52,11 @@ begin
 GPIO <= "ZZZZZZZZ";
 LEDS <= "ZZZZ";
 
-UT0: CONTBCD_C port map(CLK => CLK100k, CLR => CLR_cont_S, UP => '1', EN => (S_IR and not Q8ms), ENOUT => EO(0), Q => num0);
-UT1: CONTBCD_C port map(CLK => CLK100k, CLR => CLR_cont_S, UP => '1', EN => EO(0), ENOUT => EO(1), Q => num1);
-
+--contador 8 bits de transmissão, conta até 32
+UT0: CONTBCD_C port map(CLK => clkcontbits, CLR => clrcontbits, UP => '1', EN => 1, ENOUT => EOTX8(0), Q => cont32TXIR(3 downto 0));
+UT1: CONTBCD_C port map(CLK => clkcontbits, CLR => clrcontbits, UP => '1', EN => EOTX8(0), ENOUT => EOTX8(1), Q => cont32TXIR(7 downto 4));
 
+contbitsigual32 <= '1' when cont32TXIR="00110010" else '0';