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Synthesis e correção de erros

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This commit is contained in:
Gabriel Lima
2022-06-01 12:12:24 -03:00
parent de0e4788c4
commit b2081d97f0
45 changed files with 1079 additions and 859 deletions
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12
Aula20220601.gise
View File

@@ -101,7 +101,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1654093709" xil_pn:in_ck="-4144913829261074638" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-2610007826355223435" xil_pn:start_ts="1654093699">
<transform xil_pn:end_ts="1654096278" xil_pn:in_ck="-4144913829261074638" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-2610007826355223435" xil_pn:start_ts="1654096268">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@@ -123,7 +123,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1654093718" xil_pn:in_ck="6717519187032307095" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7902521214899444903" xil_pn:start_ts="1654093711">
<transform xil_pn:end_ts="1654096287" xil_pn:in_ck="6717519187032307095" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7902521214899444903" xil_pn:start_ts="1654096280">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@@ -132,7 +132,7 @@
<outfile xil_pn:name="textovhdl.bld"/>
<outfile xil_pn:name="textovhdl.ngd"/>
</transform>
<transform xil_pn:end_ts="1654093728" xil_pn:in_ck="6717519187032307096" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-3180699873896808002" xil_pn:start_ts="1654093718">
<transform xil_pn:end_ts="1654096297" xil_pn:in_ck="6717519187032307096" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-3180699873896808002" xil_pn:start_ts="1654096287">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@@ -146,7 +146,7 @@
<outfile xil_pn:name="textovhdl_summary.xml"/>
<outfile xil_pn:name="textovhdl_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1654093743" xil_pn:in_ck="-717353726922960719" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1178055513630676559" xil_pn:start_ts="1654093728">
<transform xil_pn:end_ts="1654096313" xil_pn:in_ck="-717353726922960719" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1178055513630676559" xil_pn:start_ts="1654096297">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@@ -161,7 +161,7 @@
<outfile xil_pn:name="textovhdl_pad.txt"/>
<outfile xil_pn:name="textovhdl_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1654093762" xil_pn:in_ck="-4144913829261083515" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1654093750">
<transform xil_pn:end_ts="1654096326" xil_pn:in_ck="-4144913829261083515" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1654096314">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
@@ -173,7 +173,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1654093743" xil_pn:in_ck="6717519187032306964" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1654093737">
<transform xil_pn:end_ts="1654096313" xil_pn:in_ck="6717519187032306964" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1654096306">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>

2
_ngo/netlist.lst
View File

@@ -1,2 +1,2 @@
C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.ngc 1654093707
C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.ngc 1654096277
OK

24
_xmsgs/map.xmsgs
View File

@@ -5,10 +5,10 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">BUT&lt;3&gt;_IBUF</arg> has no load.
<msg type="info" file="LIT" num="243" delta="old" >Logical network <arg fmt="%s" index="1">BUT&lt;3&gt;_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="395" delta="new" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">12</arg> more times for the following (max. 5 shown):
<msg type="info" file="LIT" num="395" delta="new" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">11</arg> more times for the following (max. 5 shown):
<arg fmt="%s" index="3">BUT&lt;2&gt;_IBUF,
BUT&lt;1&gt;_IBUF,
BUT&lt;0&gt;_IBUF,
@@ -17,34 +17,34 @@ DIPSW&lt;2&gt;_IBUF</arg>
To see the details of these <arg fmt="%s" index="4">info</arg> messages, please use the -detail switch.
</msg>
<msg type="info" file="MapLib" num="562" delta="new" >No environment variables are currently set.
<msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set.
</msg>
<msg type="warning" file="MapLib" num="701" delta="new" >Signal <arg fmt="%s" index="1">LEDS&lt;3&gt;</arg> connected to top level port <arg fmt="%s" index="2">LEDS&lt;3&gt;</arg> has been removed.
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">LEDS&lt;3&gt;</arg> connected to top level port <arg fmt="%s" index="2">LEDS&lt;3&gt;</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="new" >Signal <arg fmt="%s" index="1">LEDS&lt;2&gt;</arg> connected to top level port <arg fmt="%s" index="2">LEDS&lt;2&gt;</arg> has been removed.
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">LEDS&lt;2&gt;</arg> connected to top level port <arg fmt="%s" index="2">LEDS&lt;2&gt;</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="new" >Signal <arg fmt="%s" index="1">LEDS&lt;1&gt;</arg> connected to top level port <arg fmt="%s" index="2">LEDS&lt;1&gt;</arg> has been removed.
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">LEDS&lt;1&gt;</arg> connected to top level port <arg fmt="%s" index="2">LEDS&lt;1&gt;</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="new" >Signal <arg fmt="%s" index="1">LEDS&lt;0&gt;</arg> connected to top level port <arg fmt="%s" index="2">LEDS&lt;0&gt;</arg> has been removed.
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">LEDS&lt;0&gt;</arg> connected to top level port <arg fmt="%s" index="2">LEDS&lt;0&gt;</arg> has been removed.
</msg>
<msg type="info" file="LIT" num="244" delta="new" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
<msg type="info" file="LIT" num="244" delta="old" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
</msg>
<msg type="info" file="Pack" num="1716" delta="new" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)
<msg type="info" file="Pack" num="1716" delta="old" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)
</msg>
<msg type="info" file="Pack" num="1720" delta="new" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts)
<msg type="info" file="Pack" num="1720" delta="old" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts)
</msg>
<msg type="info" file="Map" num="215" delta="new" >The Interim Design Summary has been generated in the MAP Report (.mrp).
<msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp).
</msg>
<msg type="info" file="Pack" num="1650" delta="new" >Map created a placed design.
<msg type="info" file="Pack" num="1650" delta="old" >Map created a placed design.
</msg>
</messages>

10
_xmsgs/ngdbuild.xmsgs
View File

@@ -5,19 +5,19 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="NgdBuild" num="470" delta="new" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">GPIO&lt;7&gt;</arg>&apos; has no legal driver
<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">GPIO&lt;7&gt;</arg>&apos; has no legal driver
</msg>
<msg type="warning" file="NgdBuild" num="470" delta="new" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">GPIO&lt;6&gt;</arg>&apos; has no legal driver
<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">GPIO&lt;6&gt;</arg>&apos; has no legal driver
</msg>
<msg type="warning" file="NgdBuild" num="470" delta="new" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">GPIO&lt;5&gt;</arg>&apos; has no legal driver
<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">GPIO&lt;5&gt;</arg>&apos; has no legal driver
</msg>
<msg type="warning" file="NgdBuild" num="470" delta="new" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">GPIO&lt;4&gt;</arg>&apos; has no legal driver
<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">GPIO&lt;3&gt;</arg>&apos; has no legal driver
</msg>
<msg type="warning" file="NgdBuild" num="470" delta="new" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">GPIO&lt;3&gt;</arg>&apos; has no legal driver
<msg type="warning" file="ParHelpers" num="414" delta="new" >An error has occured while generating a Map report. The <arg fmt="%s" index="1">libReportC_Core</arg>.xrpt XML report file will not be generated.
</msg>
</messages>

37
_xmsgs/par.xmsgs
View File

@@ -5,58 +5,55 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Par" num="282" delta="new" >No user timing constraints were detected or you have set the option to ignore timing constraints (&quot;par -x&quot;). Place and Route will run in &quot;Performance Evaluation Mode&quot; to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to &quot;std&quot;. For best performance, set the effort level to &quot;high&quot;.
<msg type="info" file="Par" num="282" delta="old" >No user timing constraints were detected or you have set the option to ignore timing constraints (&quot;par -x&quot;). Place and Route will run in &quot;Performance Evaluation Mode&quot; to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to &quot;std&quot;. For best performance, set the effort level to &quot;high&quot;.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">BUT&lt;2&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">BUT&lt;2&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">BUT&lt;3&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">BUT&lt;3&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">GPIO&lt;3&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">GPIO&lt;3&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">GPIO&lt;4&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">GPIO&lt;5&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">GPIO&lt;5&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">GPIO&lt;6&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">GPIO&lt;6&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">GPIO&lt;7&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">GPIO&lt;7&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">DIPSW&lt;0&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">DIPSW&lt;0&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">DIPSW&lt;1&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">DIPSW&lt;1&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">DIPSW&lt;2&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">DIPSW&lt;2&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">DIPSW&lt;3&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">DIPSW&lt;3&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">BUT&lt;0&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">BUT&lt;0&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">BUT&lt;1&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">BUT&lt;1&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
<msg type="info" file="Par" num="459" delta="old" >The Clock Report is not displayed in the non timing-driven mode.
</msg>
<msg type="info" file="Par" num="459" delta="new" >The Clock Report is not displayed in the non timing-driven mode.
</msg>
<msg type="info" file="Timing" num="2761" delta="old" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg>
<msg type="info" file="Timing" num="2761" delta="new" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg>
<msg type="warning" file="ParHelpers" num="361" delta="new" >There are <arg fmt="%d" index="1">13</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
<msg type="warning" file="ParHelpers" num="361" delta="new" >There are <arg fmt="%d" index="1">12</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
</msg>
<msg type="warning" file="Par" num="283" delta="new" >There are <arg fmt="%d" index="1">13</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
<msg type="warning" file="Par" num="283" delta="new" >There are <arg fmt="%d" index="1">12</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
</msg>

8
_xmsgs/trce.xmsgs
View File

@@ -5,13 +5,13 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Timing" num="2698" delta="new" >No timing constraints found, doing default enumeration.</msg>
<msg type="info" file="Timing" num="2698" delta="old" >No timing constraints found, doing default enumeration.</msg>
<msg type="info" file="Timing" num="3412" delta="new" >To improve timing, see the Timing Closure User Guide (UG612).</msg>
<msg type="info" file="Timing" num="3412" delta="old" >To improve timing, see the Timing Closure User Guide (UG612).</msg>
<msg type="info" file="Timing" num="2752" delta="new" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
<msg type="info" file="Timing" num="2752" delta="old" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
<msg type="info" file="Timing" num="3339" delta="new" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
<msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
</messages>

66
_xmsgs/xst.xmsgs
View File

@@ -5,103 +5,103 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd" Line 54: Assignment to <arg fmt="%s" index="1">clk100k</arg> ignored, since the identifier is never used
<msg type="warning" file="HDLCompiler" num="946" delta="old" >"C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd" Line 79: Actual for formal port <arg fmt="%s" index="1">en</arg> is neither a static name nor a globally static expression
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd" Line 55: Assignment to <arg fmt="%s" index="1">clk25k</arg> ignored, since the identifier is never used
<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd" Line 65: Assignment to <arg fmt="%s" index="1">codigo32</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd" Line 56: Assignment to <arg fmt="%s" index="1">clk621ms</arg> ignored, since the identifier is never used
<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd" Line 101: Assignment to <arg fmt="%s" index="1">clk25k</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="old" >"C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd" Line 20: Net &lt;<arg fmt="%s" index="1">num7[3]</arg>&gt; does not have a driver.
<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd" Line 102: Assignment to <arg fmt="%s" index="1">clk621ms</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">BUT</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd" Line 20: Net &lt;<arg fmt="%s" index="1">num7[3]</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DIPSW</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">BUT</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">num7</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">DIPSW</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">num6</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd</arg>&quot; line <arg fmt="%s" index="2">81</arg>: Output port &lt;<arg fmt="%s" index="3">ENOUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">UC2</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">num5</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">num7</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">num4</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">num6</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">num3</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">num5</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">num2</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">num4</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">num1</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">num3</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">num0</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
<msg type="info" file="Xst" num="3218" delta="new" >HDL ADVISOR - The RAM &lt;<arg fmt="%s" index="1">Mram_proxdisplay</arg>&gt; will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
</msg>
<msg type="info" file="Xst" num="3218" delta="old" >HDL ADVISOR - The RAM &lt;<arg fmt="%s" index="1">Mram_proxdisplay</arg>&gt; will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_6</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_6</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_7</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_7</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_8</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_8</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_9</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_9</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_10</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_10</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_11</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_11</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_12</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_12</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_13</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_13</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_14</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_14</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_15</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_15</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_16</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_16</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_17</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_17</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_18</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_18</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_19</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_19</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_20</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_20</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_21</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_21</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_22</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_22</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_23</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">contaux_23</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">textovhdl</arg>&gt;.
<msg type="info" file="Xst" num="2169" delta="new" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
</msg>
</messages>

40
par_usage_statistics.html
View File

@@ -1,32 +1,32 @@
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>39</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>104</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>104</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>100</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>4.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>4.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>4.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>120</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>369</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>369</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>348</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>4.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>4.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>4.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>5.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>5.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>5.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>5.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>5.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>5.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>5.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>2.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>2.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>9.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>4.1</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>0.6</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>5.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>5.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>5.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>5.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>5.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>5.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>1.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>1.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>3.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>0.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>4.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>0.9</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0050</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0215</xtag-par-property-value></TD></TR>
</xtag-section>
</TABLE>

2
textovhdl.bgn
View File

@@ -5,7 +5,7 @@ C:\Xilinx\14.7\ISE_DS\ISE\.
"textovhdl" is an NCD, version 3.2, device xc6slx16, package csg324, speed -2
Opened constraints file textovhdl.pcf.
Wed Jun 01 11:29:15 2022
Wed Jun 01 12:11:59 2022
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 textovhdl.ncd

BIN
textovhdl.bit
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Binary file not shown.

9
textovhdl.bld
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@@ -18,7 +18,6 @@ Checking expanded design ...
WARNING:NgdBuild:470 - bidirect pad net 'GPIO<7>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'GPIO<6>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'GPIO<5>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'GPIO<4>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'GPIO<3>' has no legal driver
Partition Implementation Status
@@ -30,12 +29,14 @@ Partition Implementation Status
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 5
Number of warnings: 4
Total memory usage is 161008 kilobytes
Total memory usage is 162032 kilobytes
WARNING:ParHelpers:414 - An error has occured while generating a Map report. The
libReportC_Core.xrpt XML report file will not be generated.
Writing NGD file "textovhdl.ngd" ...
Total REAL time to NGDBUILD completion: 4 sec
Total REAL time to NGDBUILD completion: 3 sec
Total CPU time to NGDBUILD completion: 3 sec
Writing NGDBUILD log file "textovhdl.bld"...

9
textovhdl.cmd_log
View File

@@ -6,3 +6,12 @@ map -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0 -re
par -w -intstyle ise -ol high -mt off textovhdl_map.ncd textovhdl.ncd textovhdl.pcf
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml textovhdl.twx textovhdl.ncd -o textovhdl.twr textovhdl.pcf -ucf restricoes.ucf
bitgen -intstyle ise -f textovhdl.ut textovhdl.ncd
xst -intstyle ise -ifn "C:/Users/Gabriel/Xilinx/Aula20220601/textovhdl.xst" -ofn "C:/Users/Gabriel/Xilinx/Aula20220601/textovhdl.syr"
xst -intstyle ise -ifn "C:/Users/Gabriel/Xilinx/Aula20220601/textovhdl.xst" -ofn "C:/Users/Gabriel/Xilinx/Aula20220601/textovhdl.syr"
xst -intstyle ise -ifn "C:/Users/Gabriel/Xilinx/Aula20220601/textovhdl.xst" -ofn "C:/Users/Gabriel/Xilinx/Aula20220601/textovhdl.syr"
xst -intstyle ise -ifn "C:/Users/Gabriel/Xilinx/Aula20220601/textovhdl.xst" -ofn "C:/Users/Gabriel/Xilinx/Aula20220601/textovhdl.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc restricoes.ucf -p xc6slx16-csg324-2 textovhdl.ngc textovhdl.ngd
map -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o textovhdl_map.ncd textovhdl.ngd textovhdl.pcf
par -w -intstyle ise -ol high -mt off textovhdl_map.ncd textovhdl.ncd textovhdl.pcf
trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml textovhdl.twx textovhdl.ncd -o textovhdl.twr textovhdl.pcf -ucf restricoes.ucf
bitgen -intstyle ise -f textovhdl.ut textovhdl.ncd

2
textovhdl.drc
View File

@@ -1,7 +1,7 @@
Release 14.7 Drc P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Wed Jun 01 11:29:15 2022
Wed Jun 01 12:11:59 2022
drc -z textovhdl.ncd textovhdl.pcf

2
textovhdl.ncd
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File diff suppressed because one or more lines are too long

2
textovhdl.ngc
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File diff suppressed because one or more lines are too long

2
textovhdl.ngd
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File diff suppressed because one or more lines are too long

2
textovhdl.ngr
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File diff suppressed because one or more lines are too long

2
textovhdl.pad
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@@ -1,7 +1,7 @@
Release 14.7 - par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Wed Jun 01 11:28:55 2022
Wed Jun 01 12:11:44 2022
# NOTE: This file is designed to be imported into a spreadsheet program

52
textovhdl.par
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@@ -1,7 +1,7 @@
Release 14.7 par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
GABRIEL-E5400:: Wed Jun 01 11:28:49 2022
GABRIEL-E5400:: Wed Jun 01 12:11:38 2022
par -w -intstyle ise -ol high -mt off textovhdl_map.ncd textovhdl.ncd
textovhdl.pcf
@@ -27,16 +27,16 @@ Device speed data version: "PRODUCTION 1.23 2013-10-13".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 32 out of 18,224 1%
Number used as Flip Flops: 32
Number of Slice Registers: 70 out of 18,224 1%
Number used as Flip Flops: 70
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 31 out of 9,112 1%
Number used as logic: 29 out of 9,112 1%
Number using O6 output only: 14
Number using O5 output only: 11
Number using O5 and O6: 4
Number of Slice LUTs: 100 out of 9,112 1%
Number used as logic: 98 out of 9,112 1%
Number using O6 output only: 54
Number using O5 output only: 12
Number using O5 and O6: 32
Number used as ROM: 0
Number used as Memory: 0 out of 2,176 0%
Number used exclusively as route-thrus: 2
@@ -45,12 +45,12 @@ Slice Logic Utilization:
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 11 out of 2,278 1%
Number of MUXCYs used: 20 out of 4,556 1%
Number of LUT Flip Flop pairs used: 31
Number with an unused Flip Flop: 1 out of 31 3%
Number with an unused LUT: 0 out of 31 0%
Number of fully used LUT-FF pairs: 30 out of 31 96%
Number of occupied Slices: 30 out of 2,278 1%
Number of MUXCYs used: 44 out of 4,556 1%
Number of LUT Flip Flop pairs used: 100
Number with an unused Flip Flop: 37 out of 100 37%
Number with an unused LUT: 0 out of 100 0%
Number of fully used LUT-FF pairs: 63 out of 100 63%
Number of slice register sites lost
to control set restrictions: 0 out of 18,224 0%
@@ -99,7 +99,6 @@ Finished initial Timing Analysis. REAL time: 4 secs
WARNING:Par:288 - The signal BUT<2>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal BUT<3>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO<3>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO<4>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO<5>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO<6>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO<7>_IBUF has no load. PAR will not attempt to route this signal.
@@ -112,13 +111,13 @@ WARNING:Par:288 - The signal BUT<1>_IBUF has no load. PAR will not attempt to r
Starting Router
Phase 1 : 119 unrouted; REAL time: 4 secs
Phase 1 : 413 unrouted; REAL time: 4 secs
Phase 2 : 93 unrouted; REAL time: 4 secs
Phase 2 : 351 unrouted; REAL time: 4 secs
Phase 3 : 4 unrouted; REAL time: 4 secs
Phase 3 : 48 unrouted; REAL time: 4 secs
Phase 4 : 4 unrouted; (Par is working to improve performance) REAL time: 5 secs
Phase 4 : 48 unrouted; (Par is working to improve performance) REAL time: 5 secs
Updating file: textovhdl.ncd with current fully routed design.
@@ -154,11 +153,14 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net con | SETUP | N/A| 1.993ns| N/A| 0
Autotimespec constraint for clock net CLK | SETUP | N/A| 3.706ns| N/A| 0
27MHz_BUFGP | HOLD | 0.530ns| | 0| 0
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net con | SETUP | N/A| 2.480ns| N/A| 0
taux_5_BUFG | HOLD | 0.463ns| | 0| 0
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net CLK | SETUP | N/A| 1.805ns| N/A| 0
27MHz_BUFGP | HOLD | 0.530ns| | 0| 0
Autotimespec constraint for clock net con | SETUP | N/A| 3.342ns| N/A| 0
t100k<8> | HOLD | 0.419ns| | 0| 0
----------------------------------------------------------------------------------------------------------
@@ -174,18 +176,18 @@ Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 13 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
WARNING:Par:283 - There are 12 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 6 secs
Total CPU time to PAR completion: 6 secs
Peak Memory Usage: 306 MB
Peak Memory Usage: 314 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 15
Number of warning messages: 14
Number of info messages: 2
Writing design to file textovhdl.ncd

2
textovhdl.pcf
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@@ -1,5 +1,5 @@
//! **************************************************************************
// Written by: Map P.20131013 on Wed Jun 01 11:28:46 2022
// Written by: Map P.20131013 on Wed Jun 01 12:11:35 2022
//! **************************************************************************
SCHEMATIC START;

2
textovhdl.ptwx
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@@ -329,4 +329,4 @@
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net contaux_5_BUFG</twConstName><twConstData type="SETUP" best="1.993" units="ns" score="0"/><twConstData type="HOLD" slack="0.463" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net CLK27MHz_BUFGP</twConstName><twConstData type="SETUP" best="1.805" units="ns" score="0"/><twConstData type="HOLD" slack="0.530" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="6">0</twUnmetConstCnt><twInfo anchorID="7">INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</twInfo></twSumRpt></twBody></twReport>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net CLK27MHz_BUFGP</twConstName><twConstData type="SETUP" best="3.706" units="ns" score="0"/><twConstData type="HOLD" slack="0.530" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net contaux_5_BUFG</twConstName><twConstData type="SETUP" best="2.480" units="ns" score="0"/><twConstData type="HOLD" slack="0.463" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net cont100k&lt;8&gt;</twConstName><twConstData type="SETUP" best="3.342" units="ns" score="0"/><twConstData type="HOLD" slack="0.419" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="8">0</twUnmetConstCnt><twInfo anchorID="9">INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</twInfo></twSumRpt></twBody></twReport>

290
textovhdl.syr
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@@ -4,13 +4,13 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.12 secs
Total CPU time to Xst completion: 0.11 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.12 secs
Total CPU time to Xst completion: 0.11 secs
--> Reading design: textovhdl.prj
@@ -108,6 +108,7 @@ Slice Utilization Ratio Delta : 5
Parsing VHDL file "C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd" into library work
Parsing entity <textovhdl>.
Parsing architecture <comportamento> of entity <textovhdl>.
WARNING:HDLCompiler:946 - "C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd" Line 79: Actual for formal port en is neither a static name nor a globally static expression
Parsing entity <CONTBCD_C>.
Parsing architecture <comportamento> of entity <contbcd_c>.
Parsing entity <display>.
@@ -120,9 +121,11 @@ Parsing architecture <comportamento> of entity <display>.
Elaborating entity <textovhdl> (architecture <comportamento>) from library <work>.
Elaborating entity <display> (architecture <comportamento>) from library <work>.
WARNING:HDLCompiler:1127 - "C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd" Line 54: Assignment to clk100k ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd" Line 55: Assignment to clk25k ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd" Line 56: Assignment to clk621ms ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd" Line 65: Assignment to codigo32 ignored, since the identifier is never used
Elaborating entity <CONTBCD_C> (architecture <comportamento>) from library <work>.
WARNING:HDLCompiler:1127 - "C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd" Line 101: Assignment to clk25k ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd" Line 102: Assignment to clk621ms ignored, since the identifier is never used
WARNING:HDLCompiler:634 - "C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd" Line 20: Net <num7[3]> does not have a driver.
=========================================================================
@@ -133,6 +136,7 @@ Synthesizing Unit <textovhdl>.
Related source file is "C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd".
WARNING:Xst:647 - Input <BUT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DIPSW> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd" line 81: Output port <ENOUT> of the instance <UC2> is unconnected or connected to loadless signal.
Always blocking tristate driving signal <GPIO<7>> is removed.
Always blocking tristate driving signal <GPIO<6>> is removed.
Always blocking tristate driving signal <GPIO<5>> is removed.
@@ -146,18 +150,21 @@ WARNING:Xst:653 - Signal <num6> is used but never assigned. This sourceless sign
WARNING:Xst:653 - Signal <num5> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <num4> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <num3> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <num2> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <num1> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <num0> is used but never assigned. This sourceless signal will be automatically connected to value GND.
Found 2-bit register for signal <atual_S>.
Found 24-bit register for signal <cont100k>.
Found 24-bit register for signal <contaux>.
Found 24-bit adder for signal <contaux[23]_GND_5_o_add_5_OUT> created at line 50.
Found 1-bit tristate buffer for signal <LEDS<3>> created at line 39
Found 1-bit tristate buffer for signal <LEDS<2>> created at line 39
Found 1-bit tristate buffer for signal <LEDS<1>> created at line 39
Found 1-bit tristate buffer for signal <LEDS<0>> created at line 39
Found 24-bit adder for signal <contaux[23]_GND_5_o_add_15_OUT> created at line 96.
Found 24-bit subtractor for signal <GND_5_o_GND_5_o_sub_14_OUT<23:0>> created at line 94.
Found 2-bit 4-to-1 multiplexer for signal <prox_S> created at line 24.
Found 1-bit tristate buffer for signal <LEDS<3>> created at line 44
Found 1-bit tristate buffer for signal <LEDS<2>> created at line 44
Found 1-bit tristate buffer for signal <LEDS<1>> created at line 44
Found 1-bit tristate buffer for signal <LEDS<0>> created at line 44
HDL ADVISOR - Describing an operational reset or an explicit power-up state for register <atual_S> would allow inference of a finite state machine and as consequence better performance and smaller area.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 24 D-type flip-flop(s).
inferred 2 Adder/Subtractor(s).
inferred 50 D-type flip-flop(s).
inferred 2 Multiplexer(s).
inferred 4 Tristate(s).
Unit <textovhdl> synthesized.
@@ -166,31 +173,49 @@ Synthesizing Unit <display>.
Found 1-bit register for signal <configur>.
Found 16-bit register for signal <palavra>.
Found 9-bit register for signal <EN>.
Found 9-bit adder for signal <EN[8]_GND_18_o_add_37_OUT> created at line 169.
Found 9-bit adder for signal <EN[8]_GND_18_o_add_37_OUT> created at line 216.
Found 8x4-bit Read Only RAM for signal <proxdisplay>
Summary:
inferred 1 RAM(s).
inferred 1 Adder/Subtractor(s).
inferred 26 D-type flip-flop(s).
inferred 4 Multiplexer(s).
inferred 9 Multiplexer(s).
Unit <display> synthesized.
Synthesizing Unit <CONTBCD_C>.
Related source file is "C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd".
Found 4-bit register for signal <cont>.
Found 4-bit adder for signal <cont[3]_UP_add_3_OUT> created at line 137.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 4 D-type flip-flop(s).
inferred 3 Multiplexer(s).
Unit <CONTBCD_C> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# RAMs : 1
8x4-bit single-port Read Only RAM : 1
# Adders/Subtractors : 2
# Adders/Subtractors : 6
24-bit adder : 1
24-bit subtractor : 1
4-bit adder : 3
9-bit adder : 1
# Registers : 4
# Registers : 9
1-bit register : 1
16-bit register : 1
24-bit register : 1
2-bit register : 1
24-bit register : 2
4-bit register : 3
9-bit register : 1
# Multiplexers : 4
16-bit 2-to-1 multiplexer : 4
# Multiplexers : 20
1-bit 2-to-1 multiplexer : 3
16-bit 2-to-1 multiplexer : 5
2-bit 4-to-1 multiplexer : 1
24-bit 2-to-1 multiplexer : 1
4-bit 2-to-1 multiplexer : 10
# Tristates : 4
1-bit tristate buffer : 4
@@ -217,6 +242,7 @@ INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_proxdisplay> will be implemented on
Unit <display> synthesized (advanced).
Synthesizing (advanced) Unit <textovhdl>.
The following registers are absorbed into counter <cont100k>: 1 register on signal <cont100k>.
The following registers are absorbed into counter <contaux>: 1 register on signal <contaux>.
Unit <textovhdl> synthesized (advanced).
@@ -226,13 +252,19 @@ Advanced HDL Synthesis Report
Macro Statistics
# RAMs : 1
8x4-bit single-port distributed Read Only RAM : 1
# Counters : 2
# Adders/Subtractors : 3
4-bit adder : 3
# Counters : 3
24-bit down counter : 1
24-bit up counter : 1
9-bit up counter : 1
# Registers : 17
Flip-Flops : 17
# Multiplexers : 4
16-bit 2-to-1 multiplexer : 4
# Registers : 31
Flip-Flops : 31
# Multiplexers : 19
1-bit 2-to-1 multiplexer : 3
16-bit 2-to-1 multiplexer : 5
2-bit 4-to-1 multiplexer : 1
4-bit 2-to-1 multiplexer : 10
=========================================================================
@@ -260,11 +292,13 @@ WARNING:Xst:2677 - Node <contaux_23> of sequential type is unconnected in block
Optimizing unit <textovhdl> ...
Optimizing unit <CONTBCD_C> ...
Optimizing unit <display> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block textovhdl, actual ratio is 0.
Found area constraint ratio of 100 (+ 5) on block textovhdl, actual ratio is 1.
Final Macro Processing ...
@@ -272,8 +306,8 @@ Final Macro Processing ...
Final Register Report
Macro Statistics
# Registers : 32
Flip-Flops : 32
# Registers : 70
Flip-Flops : 70
=========================================================================
@@ -296,25 +330,27 @@ Top Level Output File Name : textovhdl.ngc
Primitive and Black Box Usage:
------------------------------
# BELS : 64
# BELS : 188
# GND : 1
# INV : 4
# LUT1 : 13
# LUT2 : 5
# LUT3 : 1
# LUT4 : 1
# LUT5 : 5
# LUT6 : 5
# MUXCY : 13
# INV : 30
# LUT1 : 14
# LUT2 : 7
# LUT3 : 8
# LUT4 : 5
# LUT5 : 34
# LUT6 : 13
# MUXCY : 36
# VCC : 1
# XORCY : 15
# FlipFlops/Latches : 32
# FD : 15
# XORCY : 39
# FlipFlops/Latches : 70
# FD : 41
# FD_1 : 17
# FDCE : 12
# Clock Buffers : 2
# BUFG : 1
# BUFGP : 1
# IO Buffers : 7
# IO Buffers : 8
# IBUF : 1
# OBUF : 3
# OBUFT : 4
@@ -325,20 +361,20 @@ Selected Device : 6slx16csg324-2
Slice Logic Utilization:
Number of Slice Registers: 32 out of 18224 0%
Number of Slice LUTs: 34 out of 9112 0%
Number used as Logic: 34 out of 9112 0%
Number of Slice Registers: 70 out of 18224 0%
Number of Slice LUTs: 111 out of 9112 1%
Number used as Logic: 111 out of 9112 1%
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 34
Number with an unused Flip Flop: 2 out of 34 5%
Number with an unused LUT: 0 out of 34 0%
Number of fully used LUT-FF pairs: 32 out of 34 94%
Number of unique control sets: 3
Number of LUT Flip Flop pairs used: 111
Number with an unused Flip Flop: 41 out of 111 36%
Number with an unused LUT: 0 out of 111 0%
Number of fully used LUT-FF pairs: 70 out of 111 63%
Number of unique control sets: 7
IO Utilization:
Number of IOs: 21
Number of bonded IOBs: 8 out of 232 3%
Number of bonded IOBs: 9 out of 232 3%
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: 2 out of 16 12%
@@ -364,9 +400,11 @@ Clock Information:
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
CLK27MHz | BUFGP | 6 |
cont100k_8 | NONE(atual_S_0) | 14 |
CLK27MHz | BUFGP | 30 |
contaux_5 | BUFG | 26 |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
Asynchronous Control Signals Information:
----------------------------------------
@@ -376,8 +414,8 @@ Timing Summary:
---------------
Speed Grade: -2
Minimum period: 2.579ns (Maximum Frequency: 387.785MHz)
Minimum input arrival time before clock: No path found
Minimum period: 4.375ns (Maximum Frequency: 228.571MHz)
Minimum input arrival time before clock: 5.275ns
Maximum output required time after clock: 5.607ns
Maximum combinational path delay: No path found
@@ -386,59 +424,110 @@ Timing Details:
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'CLK27MHz'
Clock period: 2.049ns (frequency: 488.043MHz)
Total number of paths / destination ports: 21 / 6
Timing constraint: Default period analysis for Clock 'cont100k_8'
Clock period: 4.375ns (frequency: 228.571MHz)
Total number of paths / destination ports: 156 / 38
-------------------------------------------------------------------------
Delay: 2.049ns (Levels of Logic = 7)
Source: contaux_0 (FF)
Destination: contaux_5 (FF)
Delay: 4.375ns (Levels of Logic = 3)
Source: UC0/cont_3 (FF)
Destination: UC2/cont_3 (FF)
Source Clock: cont100k_8 rising
Destination Clock: cont100k_8 rising
Data Path: UC0/cont_3 to UC2/cont_3
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 4 0.525 1.234 UC0/cont_3 (UC0/cont_3)
LUT6:I1->O 9 0.254 0.976 UC0/Mmux_ENOUT11 (EO<0>)
LUT5:I4->O 4 0.254 0.804 UC1/Mmux_ENOUT11 (EO<1>)
LUT5:I4->O 1 0.254 0.000 UC2/Mmux_proxcont21 (UC2/proxcont<1>)
FDCE:D 0.074 UC2/cont_1
----------------------------------------
Total 4.375ns (1.361ns logic, 3.014ns route)
(31.1% logic, 68.9% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'CLK27MHz'
Clock period: 4.101ns (frequency: 243.843MHz)
Total number of paths / destination ports: 897 / 30
-------------------------------------------------------------------------
Delay: 4.101ns (Levels of Logic = 16)
Source: cont100k_8 (FF)
Destination: cont100k_21 (FF)
Source Clock: CLK27MHz rising
Destination Clock: CLK27MHz rising
Data Path: contaux_0 to contaux_5
Data Path: cont100k_8 to cont100k_21
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 1 0.525 0.681 contaux_0 (contaux_0)
INV:I->O 1 0.255 0.000 Mcount_contaux_lut<0>_INV_0 (Mcount_contaux_lut<0>)
MUXCY:S->O 1 0.215 0.000 Mcount_contaux_cy<0> (Mcount_contaux_cy<0>)
MUXCY:CI->O 1 0.023 0.000 Mcount_contaux_cy<1> (Mcount_contaux_cy<1>)
MUXCY:CI->O 1 0.023 0.000 Mcount_contaux_cy<2> (Mcount_contaux_cy<2>)
MUXCY:CI->O 1 0.023 0.000 Mcount_contaux_cy<3> (Mcount_contaux_cy<3>)
MUXCY:CI->O 0 0.023 0.000 Mcount_contaux_cy<4> (Mcount_contaux_cy<4>)
XORCY:CI->O 1 0.206 0.000 Mcount_contaux_xor<5> (Result<5>)
FD:D 0.074 contaux_5
FD:C->Q 16 0.525 1.181 cont100k_8 (cont100k_8)
INV:I->O 1 0.255 0.000 Mcount_cont100k_lut<8>_INV_0 (Mcount_cont100k_lut<8>)
MUXCY:S->O 1 0.215 0.000 Mcount_cont100k_cy<8> (Mcount_cont100k_cy<8>)
MUXCY:CI->O 1 0.023 0.000 Mcount_cont100k_cy<9> (Mcount_cont100k_cy<9>)
MUXCY:CI->O 1 0.023 0.000 Mcount_cont100k_cy<10> (Mcount_cont100k_cy<10>)
MUXCY:CI->O 1 0.023 0.000 Mcount_cont100k_cy<11> (Mcount_cont100k_cy<11>)
MUXCY:CI->O 1 0.023 0.000 Mcount_cont100k_cy<12> (Mcount_cont100k_cy<12>)
MUXCY:CI->O 1 0.023 0.000 Mcount_cont100k_cy<13> (Mcount_cont100k_cy<13>)
MUXCY:CI->O 1 0.023 0.000 Mcount_cont100k_cy<14> (Mcount_cont100k_cy<14>)
MUXCY:CI->O 1 0.023 0.000 Mcount_cont100k_cy<15> (Mcount_cont100k_cy<15>)
MUXCY:CI->O 1 0.023 0.000 Mcount_cont100k_cy<16> (Mcount_cont100k_cy<16>)
MUXCY:CI->O 1 0.023 0.000 Mcount_cont100k_cy<17> (Mcount_cont100k_cy<17>)
MUXCY:CI->O 1 0.023 0.000 Mcount_cont100k_cy<18> (Mcount_cont100k_cy<18>)
MUXCY:CI->O 1 0.023 0.000 Mcount_cont100k_cy<19> (Mcount_cont100k_cy<19>)
MUXCY:CI->O 1 0.023 0.000 Mcount_cont100k_cy<20> (Mcount_cont100k_cy<20>)
XORCY:CI->O 1 0.206 1.112 Mcount_cont100k_xor<21> (Result<21>1)
LUT5:I0->O 1 0.254 0.000 Mcount_cont100k_eqn_211 (Mcount_cont100k_eqn_21)
FD:D 0.074 cont100k_21
----------------------------------------
Total 2.049ns (1.368ns logic, 0.681ns route)
(66.8% logic, 33.2% route)
Total 4.101ns (1.808ns logic, 2.293ns route)
(44.1% logic, 55.9% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'contaux_5'
Clock period: 2.579ns (frequency: 387.785MHz)
Total number of paths / destination ports: 117 / 26
Clock period: 2.962ns (frequency: 337.610MHz)
Total number of paths / destination ports: 119 / 26
-------------------------------------------------------------------------
Delay: 2.579ns (Levels of Logic = 6)
Source: UDISP/EN_4 (FF)
Destination: UDISP/EN_8 (FF)
Delay: 2.962ns (Levels of Logic = 2)
Source: UDISP/configur (FF)
Destination: UDISP/palavra_3 (FF)
Source Clock: contaux_5 falling
Destination Clock: contaux_5 falling
Data Path: UDISP/EN_4 to UDISP/EN_8
Data Path: UDISP/configur to UDISP/palavra_3
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 18 0.525 1.235 UDISP/EN_4 (UDISP/EN_4)
LUT1:I0->O 1 0.254 0.000 UDISP/Mcount_EN_cy<4>_rt (UDISP/Mcount_EN_cy<4>_rt)
MUXCY:S->O 1 0.215 0.000 UDISP/Mcount_EN_cy<4> (UDISP/Mcount_EN_cy<4>)
MUXCY:CI->O 1 0.023 0.000 UDISP/Mcount_EN_cy<5> (UDISP/Mcount_EN_cy<5>)
MUXCY:CI->O 1 0.023 0.000 UDISP/Mcount_EN_cy<6> (UDISP/Mcount_EN_cy<6>)
MUXCY:CI->O 0 0.023 0.000 UDISP/Mcount_EN_cy<7> (UDISP/Mcount_EN_cy<7>)
XORCY:CI->O 1 0.206 0.000 UDISP/Mcount_EN_xor<8> (UDISP/Result<8>)
FD:D 0.074 UDISP/EN_8
FD_1:C->Q 12 0.525 1.177 UDISP/configur (UDISP/configur)
LUT6:I4->O 1 0.250 0.682 UDISP/Mmux_palavra[14]_proxpalavra[15]_mux_38_OUT91 (UDISP/Mmux_palavra[14]_proxpalavra[15]_mux_38_OUT9)
LUT4:I3->O 1 0.254 0.000 UDISP/Mmux_palavra[14]_proxpalavra[15]_mux_38_OUT92 (UDISP/palavra[14]_proxpalavra[15]_mux_38_OUT<2>)
FD_1:D 0.074 UDISP/palavra_2
----------------------------------------
Total 2.579ns (1.344ns logic, 1.235ns route)
(52.1% logic, 47.9% route)
Total 2.962ns (1.103ns logic, 1.859ns route)
(37.2% logic, 62.8% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'cont100k_8'
Total number of paths / destination ports: 20 / 20
-------------------------------------------------------------------------
Offset: 5.275ns (Levels of Logic = 4)
Source: GPIO<4> (PAD)
Destination: UC2/cont_3 (FF)
Destination Clock: cont100k_8 rising
Data Path: GPIO<4> to UC2/cont_3
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 6 1.328 1.331 GPIO_4_IBUF (GPIO_4_IBUF)
LUT6:I0->O 9 0.254 0.976 UC0/Mmux_ENOUT11 (EO<0>)
LUT5:I4->O 4 0.254 0.804 UC1/Mmux_ENOUT11 (EO<1>)
LUT5:I4->O 1 0.254 0.000 UC2/Mmux_proxcont21 (UC2/proxcont<1>)
FDCE:D 0.074 UC2/cont_1
----------------------------------------
Total 5.275ns (2.164ns logic, 3.111ns route)
(41.0% logic, 59.0% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'contaux_5'
@@ -489,7 +578,15 @@ Clock to Setup on destination clock CLK27MHz
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK27MHz | 2.049| | | |
CLK27MHz | 4.101| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock cont100k_8
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
cont100k_8 | 4.375| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock contaux_5
@@ -497,20 +594,21 @@ Clock to Setup on destination clock contaux_5
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
contaux_5 | | | 2.579| |
cont100k_8 | | | 3.154| |
contaux_5 | | | 2.962| |
---------------+---------+---------+---------+---------+
=========================================================================
Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 6.49 secs
Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 6.91 secs
-->
Total memory usage is 258888 kilobytes
Total memory usage is 258568 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 32 ( 0 filtered)
Number of infos : 1 ( 0 filtered)
Number of warnings : 30 ( 0 filtered)
Number of infos : 3 ( 0 filtered)

8
textovhdl.twr
View File

@@ -37,7 +37,7 @@ Clock CLK27MHz to Pad
|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
------------+-----------------+------------+-----------------+------------+------------------+--------+
GPIO<0> | 9.967(R)| SLOW | 4.260(R)| FAST |CLK27MHz_BUFGP | 0.000|
GPIO<0> | 9.717(R)| SLOW | 4.137(R)| FAST |CLK27MHz_BUFGP | 0.000|
------------+-----------------+------------+-----------------+------------+------------------+--------+
Clock to Setup on destination clock CLK27MHz
@@ -45,18 +45,18 @@ Clock to Setup on destination clock CLK27MHz
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK27MHz | 1.805| | | |
CLK27MHz | 3.706| | | |
---------------+---------+---------+---------+---------+
Analysis completed Wed Jun 01 11:29:02 2022
Analysis completed Wed Jun 01 12:11:51 2022
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 217 MB
Peak Memory Usage: 218 MB

4
textovhdl.twx
View File

@@ -333,7 +333,7 @@
-n 3 -fastpaths -xml textovhdl.twx textovhdl.ncd -o textovhdl.twr textovhdl.pcf
-ucf restricoes.ucf
</twCmdLine><twDesign>textovhdl.ncd</twDesign><twDesignPath>textovhdl.ncd</twDesignPath><twPCF>textovhdl.pcf</twPCF><twPcfPath>textovhdl.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="csg324"><twDevName>xc6slx16</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-2</twSpeedGrade><twSpeedVer>PRODUCTION 1.23 2013-10-13</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:2698 - No timing constraints found, doing default enumeration.</twInfo><twInfo anchorID="3">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="4">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="5">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twDataSheet anchorID="6" twNameLen="15"><twClk2OutList anchorID="7" twDestWidth="7" twPhaseWidth="14"><twSrc>CLK27MHz</twSrc><twClk2Out twOutPad = "GPIO&lt;0&gt;" twMinTime = "4.260" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "9.967" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK27MHz_BUFGP" twClkPhase="0.000" ></twClk2Out></twClk2OutList><twClk2SUList anchorID="8" twDestWidth="8"><twDest>CLK27MHz</twDest><twClk2SU><twSrc>CLK27MHz</twSrc><twRiseRise>1.805</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twFoot><twTimestamp>Wed Jun 01 11:29:02 2022 </twTimestamp></twFoot><twClientInfo anchorID="9"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
</twCmdLine><twDesign>textovhdl.ncd</twDesign><twDesignPath>textovhdl.ncd</twDesignPath><twPCF>textovhdl.pcf</twPCF><twPcfPath>textovhdl.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="csg324"><twDevName>xc6slx16</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-2</twSpeedGrade><twSpeedVer>PRODUCTION 1.23 2013-10-13</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:2698 - No timing constraints found, doing default enumeration.</twInfo><twInfo anchorID="3">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="4">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="5">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twDataSheet anchorID="6" twNameLen="15"><twClk2OutList anchorID="7" twDestWidth="7" twPhaseWidth="14"><twSrc>CLK27MHz</twSrc><twClk2Out twOutPad = "GPIO&lt;0&gt;" twMinTime = "4.137" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "9.717" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK27MHz_BUFGP" twClkPhase="0.000" ></twClk2Out></twClk2OutList><twClk2SUList anchorID="8" twDestWidth="8"><twDest>CLK27MHz</twDest><twClk2SU><twSrc>CLK27MHz</twSrc><twRiseRise>3.706</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twFoot><twTimestamp>Wed Jun 01 12:11:51 2022 </twTimestamp></twFoot><twClientInfo anchorID="9"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
Peak Memory Usage: 217 MB
Peak Memory Usage: 218 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>

5
textovhdl.unroutes
View File

@@ -1,11 +1,11 @@
Release 14.7 - par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Wed Jun 01 11:28:55 2022
Wed Jun 01 12:11:45 2022
All signals are completely routed.
WARNING:ParHelpers:361 - There are 13 loadless signals in this design. This design will cause Bitgen to issue DRC
WARNING:ParHelpers:361 - There are 12 loadless signals in this design. This design will cause Bitgen to issue DRC
warnings.
BUT<0>_IBUF
@@ -17,7 +17,6 @@ WARNING:ParHelpers:361 - There are 13 loadless signals in this design. This desi
DIPSW<2>_IBUF
DIPSW<3>_IBUF
GPIO<3>_IBUF
GPIO<4>_IBUF
GPIO<5>_IBUF
GPIO<6>_IBUF
GPIO<7>_IBUF

8
textovhdl.vhd
View File

@@ -18,12 +18,12 @@ signal cont100k,contaux: std_logic_vector(23 downto 0);
signal CLK100k,clk621ms,clk25k: std_logic;
signal clkdisp,cs,din: std_logic;
signal num7,num6,num5,num4,num3,num2,num1,num0: std_logic_vector(3 downto 0);
--signal EO: std_logic_vector (7 downto 0);
signal EO: std_logic_vector (7 downto 0);
--signal estadoprox, estadoatual: std_logic;
signal S_IR, CLR_cont_S: std_logic;
signal prox_S, atual_S: std_logic_vector(1 downto 0);
signal Q1ms, Q4ms, Q8ms: std_logic;
signal proxshift, atualshift, codigo32: std_logic_vector(1 downto 0);
signal proxshift, atualshift, codigo32: std_logic_vector(31 downto 0);
signal SIshift, ENshift: std_logic;
component display port( NUM7, NUM6, NUM5, NUM4, NUM3, NUM2, NUM1, NUM0: in std_logic_vector(3 downto 0);
@@ -77,8 +77,8 @@ begin
end process;
UC0: CONTBCD_C port map(CLK => CLK100k, CLR => CLR_cont_S, UP => '1', EN => (S_IR and not Q8ms), ENOUT => EO(0), Q => num0);
UC0: CONTBCD_C port map(CLK => CLK100k, CLR => CLR_cont_S, UP => '1', EN => EO(0), ENOUT => EO(1), Q => num1);
UC0: CONTBCD_C port map(CLK => CLK100k, CLR => CLR_cont_S, UP => '1', EN => EO(1), ENOUT => EO(2), Q => num2);
UC1: CONTBCD_C port map(CLK => CLK100k, CLR => CLR_cont_S, UP => '1', EN => EO(0), ENOUT => EO(1), Q => num1);
UC2: CONTBCD_C port map(CLK => CLK100k, CLR => CLR_cont_S, UP => '1', EN => EO(1), ENOUT => EO(2), Q => num2);
Q1ms <= num2(0);
Q4ms <= num2(2);

2
textovhdl_guide.ncd
View File

File diff suppressed because one or more lines are too long

68
textovhdl_map.map
View File

@@ -10,7 +10,7 @@ Target Device : xc6slx16
Target Package : csg324
Target Speed : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Wed Jun 01 11:28:39 2022
Mapped Date : Wed Jun 01 12:11:28 2022
Mapping design into LUTs...
WARNING:MapLib:701 - Signal LEDS<3> connected to top level port LEDS<3> has been
@@ -31,47 +31,47 @@ Total REAL time at the beginning of Placer: 5 secs
Total CPU time at the beginning of Placer: 5 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:3fba7d2c) REAL time: 5 secs
Phase 1.1 Initial Placement Analysis (Checksum:ac2028f0) REAL time: 5 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:3fba7d2c) REAL time: 5 secs
Phase 2.7 Design Feasibility Check (Checksum:ac2028f0) REAL time: 5 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:3fba7d2c) REAL time: 5 secs
Phase 3.31 Local Placement Optimization (Checksum:ac2028f0) REAL time: 5 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:a88cf486) REAL time: 6 secs
(Checksum:1384188) REAL time: 6 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:a88cf486) REAL time: 6 secs
Phase 5.36 Local Placement Optimization (Checksum:1384188) REAL time: 6 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:a88cf486) REAL time: 6 secs
Phase 6.30 Global Clock Region Assignment (Checksum:1384188) REAL time: 6 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:a88cf486) REAL time: 6 secs
Phase 7.3 Local Placement Optimization (Checksum:1384188) REAL time: 6 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:a88cf486) REAL time: 6 secs
Phase 8.5 Local Placement Optimization (Checksum:1384188) REAL time: 6 secs
Phase 9.8 Global Placement
....
....
Phase 9.8 Global Placement (Checksum:74c7df35) REAL time: 6 secs
........
........
Phase 9.8 Global Placement (Checksum:709950b0) REAL time: 6 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:74c7df35) REAL time: 6 secs
Phase 10.5 Local Placement Optimization (Checksum:709950b0) REAL time: 6 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:b8849b8d) REAL time: 6 secs
Phase 11.18 Placement Optimization (Checksum:714d3910) REAL time: 6 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:b8849b8d) REAL time: 6 secs
Phase 12.5 Local Placement Optimization (Checksum:714d3910) REAL time: 6 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:b8849b8d) REAL time: 6 secs
Phase 13.34 Placement Validation (Checksum:714d3910) REAL time: 6 secs
Total REAL time to Placer completion: 6 secs
Total CPU time to Placer completion: 6 secs
@@ -85,16 +85,16 @@ Design Summary:
Number of errors: 0
Number of warnings: 4
Slice Logic Utilization:
Number of Slice Registers: 32 out of 18,224 1%
Number used as Flip Flops: 32
Number of Slice Registers: 70 out of 18,224 1%
Number used as Flip Flops: 70
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 31 out of 9,112 1%
Number used as logic: 29 out of 9,112 1%
Number using O6 output only: 14
Number using O5 output only: 11
Number using O5 and O6: 4
Number of Slice LUTs: 100 out of 9,112 1%
Number used as logic: 98 out of 9,112 1%
Number using O6 output only: 54
Number using O5 output only: 12
Number using O5 and O6: 32
Number used as ROM: 0
Number used as Memory: 0 out of 2,176 0%
Number used exclusively as route-thrus: 2
@@ -103,15 +103,15 @@ Slice Logic Utilization:
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 11 out of 2,278 1%
Number of MUXCYs used: 20 out of 4,556 1%
Number of LUT Flip Flop pairs used: 31
Number with an unused Flip Flop: 1 out of 31 3%
Number with an unused LUT: 0 out of 31 0%
Number of fully used LUT-FF pairs: 30 out of 31 96%
Number of unique control sets: 2
Number of occupied Slices: 30 out of 2,278 1%
Number of MUXCYs used: 44 out of 4,556 1%
Number of LUT Flip Flop pairs used: 100
Number with an unused Flip Flop: 37 out of 100 37%
Number with an unused LUT: 0 out of 100 0%
Number of fully used LUT-FF pairs: 63 out of 100 63%
Number of unique control sets: 6
Number of slice register sites lost
to control set restrictions: 8 out of 18,224 1%
to control set restrictions: 26 out of 18,224 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
@@ -148,11 +148,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 1.88
Average Fanout of Non-Clock Nets: 2.80
Peak Memory Usage: 345 MB
Peak Memory Usage: 347 MB
Total REAL time to MAP completion: 7 secs
Total CPU time to MAP completion: 6 secs
Total CPU time to MAP completion: 7 secs
Mapping completed.
See MAP report file "textovhdl_map.mrp" for details.

40
textovhdl_map.mrp
View File

@@ -10,23 +10,23 @@ Target Device : xc6slx16
Target Package : csg324
Target Speed : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Wed Jun 01 11:28:39 2022
Mapped Date : Wed Jun 01 12:11:28 2022
Design Summary
--------------
Number of errors: 0
Number of warnings: 4
Slice Logic Utilization:
Number of Slice Registers: 32 out of 18,224 1%
Number used as Flip Flops: 32
Number of Slice Registers: 70 out of 18,224 1%
Number used as Flip Flops: 70
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 31 out of 9,112 1%
Number used as logic: 29 out of 9,112 1%
Number using O6 output only: 14
Number using O5 output only: 11
Number using O5 and O6: 4
Number of Slice LUTs: 100 out of 9,112 1%
Number used as logic: 98 out of 9,112 1%
Number using O6 output only: 54
Number using O5 output only: 12
Number using O5 and O6: 32
Number used as ROM: 0
Number used as Memory: 0 out of 2,176 0%
Number used exclusively as route-thrus: 2
@@ -35,15 +35,15 @@ Slice Logic Utilization:
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 11 out of 2,278 1%
Number of MUXCYs used: 20 out of 4,556 1%
Number of LUT Flip Flop pairs used: 31
Number with an unused Flip Flop: 1 out of 31 3%
Number with an unused LUT: 0 out of 31 0%
Number of fully used LUT-FF pairs: 30 out of 31 96%
Number of unique control sets: 2
Number of occupied Slices: 30 out of 2,278 1%
Number of MUXCYs used: 44 out of 4,556 1%
Number of LUT Flip Flop pairs used: 100
Number with an unused Flip Flop: 37 out of 100 37%
Number with an unused LUT: 0 out of 100 0%
Number of fully used LUT-FF pairs: 63 out of 100 63%
Number of unique control sets: 6
Number of slice register sites lost
to control set restrictions: 8 out of 18,224 1%
to control set restrictions: 26 out of 18,224 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
@@ -80,11 +80,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 1.88
Average Fanout of Non-Clock Nets: 2.80
Peak Memory Usage: 345 MB
Peak Memory Usage: 347 MB
Total REAL time to MAP completion: 7 secs
Total CPU time to MAP completion: 6 secs
Total CPU time to MAP completion: 7 secs
Table of Contents
-----------------
@@ -119,7 +119,7 @@ WARNING:MapLib:701 - Signal LEDS<0> connected to top level port LEDS<0> has been
Section 3 - Informational
-------------------------
INFO:LIT:243 - Logical network BUT<3>_IBUF has no load.
INFO:LIT:395 - The above info message is repeated 12 more times for the
INFO:LIT:395 - The above info message is repeated 11 more times for the
following (max. 5 shown):
BUT<2>_IBUF,
BUT<1>_IBUF,

2
textovhdl_map.ncd
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2
textovhdl_map.ngm
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46
textovhdl_map.xrpt
View File

@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Map" timeStamp="Wed Jun 01 11:28:46 2022">
<application stringID="Map" timeStamp="Wed Jun 01 12:11:35 2022">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@@ -65,16 +65,16 @@
<item DEFAULT="None" label="-p" stringID="MAP_PARTNAME" value="xc6slx16-csg324-2"/>
</section>
<task stringID="MAP_PACK_REPORT">
<item AVAILABLE="18224" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="32">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="32"/>
<item AVAILABLE="18224" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="70">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="70"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
</item>
<item AVAILABLE="9112" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="31">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="11"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="14"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="4"/>
<item AVAILABLE="9112" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="100">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="12"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="54"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="32"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
@@ -117,21 +117,21 @@
<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="4"/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="353676"/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="355212"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="7 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="6 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="7 secs "/>
</section>
<section stringID="MAP_SLICE_REPORTING">
<item AVAILABLE="18224" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="32">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="32"/>
<item AVAILABLE="18224" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="70">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="70"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
</item>
<item AVAILABLE="9112" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="31">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="11"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="14"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="4"/>
<item AVAILABLE="9112" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="100">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="12"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="54"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="32"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
@@ -151,15 +151,15 @@
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="2"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item>
<item AVAILABLE="2278" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="11">
<item AVAILABLE="595" dataType="int" stringID="MAP_NUM_SLICEL" value="5"/>
<item AVAILABLE="2278" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="30">
<item AVAILABLE="595" dataType="int" stringID="MAP_NUM_SLICEL" value="11"/>
<item AVAILABLE="544" dataType="int" stringID="MAP_NUM_SLICEM" value="0"/>
<item AVAILABLE="1139" dataType="int" stringID="MAP_NUM_SLICEX" value="6"/>
<item AVAILABLE="1139" dataType="int" stringID="MAP_NUM_SLICEX" value="19"/>
</item>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="31">
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="1"/>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="100">
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="37"/>
<item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="0"/>
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="30"/>
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="63"/>
</item>
</section>
<section stringID="MAP_IOB_REPORTING">
@@ -330,7 +330,7 @@
</section>
<section stringID="MAP_RPM_MACROS">
<section stringID="MAP_SHAPE_SECTION">
<item dataType="int" stringID="MAP_NUM_SHAPE" value="2"/>
<item dataType="int" stringID="MAP_NUM_SHAPE" value="3"/>
</section>
</section>
<section stringID="MAP_GUIDE_REPORT"/>
@@ -339,7 +339,7 @@
<section stringID="MAP_CONFIGURATION_STRING_DETAILS"/>
<section stringID="MAP_GENERAL_CONFIG_DATA"/>
<section stringID="MAP_CONTROL_SET_INFORMATION">
<item dataType="int" label="Number of unique control sets" stringID="MAP_NUM_CONTROL_SETS" value="2"/>
<item dataType="int" label="Number of unique control sets" stringID="MAP_NUM_CONTROL_SETS" value="6"/>
<tree stringID="MAP_CONTROL_SET_HIERARCHY">
<property stringID="MAP_CLOCK_SIGNAL"/>
<property stringID="MAP_RESET_SIGNAL"/>

2
textovhdl_pad.csv
View File

@@ -1,7 +1,7 @@
#Release 14.7 - par P.20131013 (nt64)
#Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
#Wed Jun 01 11:28:55 2022
#Wed Jun 01 12:11:44 2022
#
## NOTE: This file is designed to be imported into a spreadsheet program
1 #Release 14.7 - par P.20131013 (nt64)
2 #Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
3 #Wed Jun 01 11:28:55 2022 #Wed Jun 01 12:11:44 2022
4 #
5 ## NOTE: This file is designed to be imported into a spreadsheet program
6 # such as Microsoft Excel for viewing, printing and sorting. The |
7 # character is used as the data field separator. This file is also designed

2
textovhdl_pad.txt
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@@ -1,7 +1,7 @@
Release 14.7 - par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Wed Jun 01 11:28:55 2022
Wed Jun 01 12:11:44 2022
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:

30
textovhdl_par.xrpt
View File

@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="par" timeStamp="Wed Jun 01 11:28:53 2022">
<application stringID="par" timeStamp="Wed Jun 01 12:11:42 2022">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@@ -2263,12 +2263,12 @@
<section stringID="PAR_UNROUTES_REPORT">
<item dataType="int" stringID="PAR_UNROUTED_NETS" value="0"/>
<item dataType="int" stringID="PAR_TOTAL_SOURCELESS_NETS" value="0"/>
<item dataType="int" stringID="PAR_TOTAL_LOADLESS_NETS" value="13"/>
<item dataType="int" stringID="PAR_TOTAL_LOADLESS_NETS" value="12"/>
</section>
</task>
</application>
<application stringID="Par" timeStamp="Wed Jun 01 11:28:53 2022">
<application stringID="Par" timeStamp="Wed Jun 01 12:11:42 2022">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@@ -2314,16 +2314,16 @@
</section>
<task label="Device Utilization Summary" stringID="PAR_DEVICE_UTLIZATION">
<section stringID="PAR_SLICE_REPORTING">
<item AVAILABLE="18224" dataType="int" label="Number of Slice Registers" stringID="PAR_SLICE_REGISTERS" value="32">
<item dataType="int" stringID="PAR_NUM_SLICE_FF" value="32"/>
<item AVAILABLE="18224" dataType="int" label="Number of Slice Registers" stringID="PAR_SLICE_REGISTERS" value="70">
<item dataType="int" stringID="PAR_NUM_SLICE_FF" value="70"/>
<item dataType="int" stringID="PAR_NUM_SLICE_LATCH" value="0"/>
<item dataType="int" stringID="PAR_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="PAR_NUM_SLICE_LATCHLOGIC" value="0"/>
</item>
<item AVAILABLE="9112" dataType="int" label="Number of Slice LUTS" stringID="PAR_SLICE_LUTS" value="31">
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ONLY" value="11"/>
<item dataType="int" stringID="PAR_NUM_LOGIC_O6ONLY" value="14"/>
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ANDO6" value="4"/>
<item AVAILABLE="9112" dataType="int" label="Number of Slice LUTS" stringID="PAR_SLICE_LUTS" value="100">
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ONLY" value="12"/>
<item dataType="int" stringID="PAR_NUM_LOGIC_O6ONLY" value="54"/>
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ANDO6" value="32"/>
<item dataType="int" stringID="PAR_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="PAR_NUM_ROM_O6ONLY" value="0"/>
<item dataType="int" stringID="PAR_NUM_ROM_O5ANDO6" value="0"/>
@@ -2343,15 +2343,15 @@
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_CARRY4" value="2"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item>
<item AVAILABLE="2278" dataType="int" stringID="PAR_OCCUPIED_SLICES" value="11">
<item AVAILABLE="595" dataType="int" stringID="PAR_NUM_SLICEL" value="5"/>
<item AVAILABLE="2278" dataType="int" stringID="PAR_OCCUPIED_SLICES" value="30">
<item AVAILABLE="595" dataType="int" stringID="PAR_NUM_SLICEL" value="11"/>
<item AVAILABLE="544" dataType="int" stringID="PAR_NUM_SLICEM" value="0"/>
<item AVAILABLE="1139" dataType="int" stringID="PAR_NUM_SLICEX" value="6"/>
<item AVAILABLE="1139" dataType="int" stringID="PAR_NUM_SLICEX" value="19"/>
</item>
<item dataType="int" stringID="PAR_OCCUPIED_LUT_AND_FF" value="31">
<item dataType="int" stringID="PAR_OCCUPIED_LUT_ONLY" value="1"/>
<item dataType="int" stringID="PAR_OCCUPIED_LUT_AND_FF" value="100">
<item dataType="int" stringID="PAR_OCCUPIED_LUT_ONLY" value="37"/>
<item dataType="int" stringID="PAR_OCCUPIED_FF_ONLY" value="0"/>
<item dataType="int" stringID="PAR_OCCUPIED_FF_AND_LUT" value="30"/>
<item dataType="int" stringID="PAR_OCCUPIED_FF_AND_LUT" value="63"/>
</item>
</section>
<section stringID="PAR_IOB_REPORTING">

65
textovhdl_summary.html
View File

@@ -2,7 +2,7 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>textovhdl Project Status (06/01/2022 - 11:29:22)</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>textovhdl Project Status (06/01/2022 - 12:12:06)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>Aula20220601.xise</TD>
@@ -19,13 +19,12 @@
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc6slx16-2csg324</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>
No Errors</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220601\_xmsgs/*.xmsgs?&DataKey=Warning'>56 Warnings (25 new)</A></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
@@ -60,13 +59,13 @@ System Settings</A>
<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
<TD ALIGN=RIGHT>32</TD>
<TD ALIGN=RIGHT>70</TD>
<TD ALIGN=RIGHT>18,224</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Flip Flops</TD>
<TD ALIGN=RIGHT>32</TD>
<TD ALIGN=RIGHT>70</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
@@ -90,31 +89,31 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
<TD ALIGN=RIGHT>31</TD>
<TD ALIGN=RIGHT>100</TD>
<TD ALIGN=RIGHT>9,112</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
<TD ALIGN=RIGHT>29</TD>
<TD ALIGN=RIGHT>98</TD>
<TD ALIGN=RIGHT>9,112</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
<TD ALIGN=RIGHT>14</TD>
<TD ALIGN=RIGHT>54</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
<TD ALIGN=RIGHT>11</TD>
<TD ALIGN=RIGHT>12</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>32</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
@@ -156,49 +155,49 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
<TD ALIGN=RIGHT>11</TD>
<TD ALIGN=RIGHT>30</TD>
<TD ALIGN=RIGHT>2,278</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MUXCYs used</TD>
<TD ALIGN=RIGHT>20</TD>
<TD ALIGN=RIGHT>44</TD>
<TD ALIGN=RIGHT>4,556</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
<TD ALIGN=RIGHT>31</TD>
<TD ALIGN=RIGHT>100</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused Flip Flop</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>31</TD>
<TD ALIGN=RIGHT>3%</TD>
<TD ALIGN=RIGHT>37</TD>
<TD ALIGN=RIGHT>100</TD>
<TD ALIGN=RIGHT>37%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused LUT</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>31</TD>
<TD ALIGN=RIGHT>100</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of fully used LUT-FF pairs</TD>
<TD ALIGN=RIGHT>30</TD>
<TD ALIGN=RIGHT>31</TD>
<TD ALIGN=RIGHT>96%</TD>
<TD ALIGN=RIGHT>63</TD>
<TD ALIGN=RIGHT>100</TD>
<TD ALIGN=RIGHT>63%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of unique control sets</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>6</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of slice register sites lost<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;to control set restrictions</TD>
<TD ALIGN=RIGHT>8</TD>
<TD ALIGN=RIGHT>26</TD>
<TD ALIGN=RIGHT>18,224</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
@@ -354,7 +353,7 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
<TD ALIGN=RIGHT>1.88</TD>
<TD ALIGN=RIGHT>2.80</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
@@ -391,21 +390,21 @@ System Settings</A>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220601\textovhdl.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Jun 1 11:28:27 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220601\_xmsgs/xst.xmsgs?&DataKey=Warning'>32 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220601\_xmsgs/xst.xmsgs?&DataKey=Info'>1 Info (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220601\textovhdl.bld'>Translation Report</A></TD><TD>Current</TD><TD>Wed Jun 1 11:28:37 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220601\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>5 Warnings (5 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220601\textovhdl_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Wed Jun 1 11:28:46 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220601\_xmsgs/map.xmsgs?&DataKey=Warning'>4 Warnings (4 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220601\_xmsgs/map.xmsgs?&DataKey=Info'>8 Infos (8 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220601\textovhdl.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Wed Jun 1 11:28:55 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220601\_xmsgs/par.xmsgs?&DataKey=Warning'>15 Warnings (15 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220601\_xmsgs/par.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220601\textovhdl.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Jun 1 12:11:17 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220601\_xmsgs/xst.xmsgs?&DataKey=Warning'>30 Warnings (29 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220601\_xmsgs/xst.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220601\textovhdl.bld'>Translation Report</A></TD><TD>Current</TD><TD>Wed Jun 1 12:11:25 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220601\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>5 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220601\textovhdl_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Wed Jun 1 12:11:36 2022</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220601\textovhdl.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Wed Jun 1 12:11:45 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220601\_xmsgs/par.xmsgs?&DataKey=Warning'>14 Warnings (2 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220601\_xmsgs/par.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220601\textovhdl.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Wed Jun 1 11:29:02 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220601\_xmsgs/trce.xmsgs?&DataKey=Info'>4 Infos (4 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220601\textovhdl.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Wed Jun 1 11:29:19 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220601\textovhdl.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Wed Jun 1 12:11:51 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220601\_xmsgs/trce.xmsgs?&DataKey=Info'>4 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220601\textovhdl.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Wed Jun 1 12:12:04 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220601\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Wed Jun 1 11:29:20 2022</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220601\webtalk.log'>WebTalk Log File</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Wed Jun 1 11:29:22 2022</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220601\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Jun 1 12:12:04 2022</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Aula20220601\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Jun 1 12:12:06 2022</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 06/01/2022 - 11:30:10</center>
<br><center><b>Date Generated:</b> 06/01/2022 - 12:12:06</center>
</BODY></HTML>

2
textovhdl_summary.xml
View File

@@ -4,7 +4,7 @@
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DesignSummary rev="2">
<DesignSummary rev="4">
<CmdHistory>
</CmdHistory>
</DesignSummary>

640
textovhdl_usage.xml
View File

@@ -4,406 +4,460 @@
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DeviceUsageSummary rev="2">
<DesignStatistics TimeStamp="Wed Jun 01 11:29:19 2022"><group name="NetStatistics">
<item name="NumNets_Active" rev="2">
<attrib name="value" value="69"/></item>
<item name="NumNets_Vcc" rev="2">
<DeviceUsageSummary rev="4">
<DesignStatistics TimeStamp="Wed Jun 01 12:12:04 2022"><group name="NetStatistics">
<item name="NumNets_Active" rev="4">
<attrib name="value" value="149"/></item>
<item name="NumNets_Vcc" rev="4">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Active_BOUNCEACROSS" rev="2">
<item name="NumNodesOfType_Active_BOUNCEACROSS" rev="4">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Active_BOUNCEIN" rev="2">
<attrib name="value" value="6"/></item>
<item name="NumNodesOfType_Active_BUFGOUT" rev="2">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Active_BUFHINP2OUT" rev="2">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Active_CLKPIN" rev="2">
<attrib name="value" value="10"/></item>
<item name="NumNodesOfType_Active_CLKPINFEED" rev="2">
<attrib name="value" value="6"/></item>
<item name="NumNodesOfType_Active_DOUBLE" rev="2">
<attrib name="value" value="8"/></item>
<item name="NumNodesOfType_Active_GENERIC" rev="2">
<attrib name="value" value="4"/></item>
<item name="NumNodesOfType_Active_GLOBAL" rev="2">
<item name="NumNodesOfType_Active_BOUNCEIN" rev="4">
<attrib name="value" value="14"/></item>
<item name="NumNodesOfType_Active_INPUT" rev="2">
<item name="NumNodesOfType_Active_BUFGOUT" rev="4">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Active_BUFHINP2OUT" rev="4">
<attrib name="value" value="5"/></item>
<item name="NumNodesOfType_Active_IOBIN2OUT" rev="2">
<attrib name="value" value="3"/></item>
<item name="NumNodesOfType_Active_IOBOUTPUT" rev="2">
<attrib name="value" value="3"/></item>
<item name="NumNodesOfType_Active_LUTINPUT" rev="2">
<attrib name="value" value="86"/></item>
<item name="NumNodesOfType_Active_OUTBOUND" rev="2">
<attrib name="value" value="33"/></item>
<item name="NumNodesOfType_Active_OUTPUT" rev="2">
<attrib name="value" value="39"/></item>
<item name="NumNodesOfType_Active_PADINPUT" rev="2">
<attrib name="value" value="3"/></item>
<item name="NumNodesOfType_Active_PADOUTPUT" rev="2">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Active_PINBOUNCE" rev="2">
<attrib name="value" value="19"/></item>
<item name="NumNodesOfType_Active_PINFEED" rev="2">
<attrib name="value" value="102"/></item>
<item name="NumNodesOfType_Active_QUAD" rev="2">
<item name="NumNodesOfType_Active_CLKPIN" rev="4">
<attrib name="value" value="22"/></item>
<item name="NumNodesOfType_Active_SINGLE" rev="2">
<attrib name="value" value="20"/></item>
<item name="NumNodesOfType_Vcc_HVCCOUT" rev="2">
<attrib name="value" value="5"/></item>
<item name="NumNodesOfType_Vcc_LUTINPUT" rev="2">
<attrib name="value" value="15"/></item>
<item name="NumNodesOfType_Vcc_PINFEED" rev="2">
<item name="NumNodesOfType_Active_CLKPINFEED" rev="4">
<attrib name="value" value="9"/></item>
<item name="NumNodesOfType_Active_CNTRLPIN" rev="4">
<attrib name="value" value="8"/></item>
<item name="NumNodesOfType_Active_DOUBLE" rev="4">
<attrib name="value" value="78"/></item>
<item name="NumNodesOfType_Active_GENERIC" rev="4">
<attrib name="value" value="6"/></item>
<item name="NumNodesOfType_Active_GLOBAL" rev="4">
<attrib name="value" value="25"/></item>
<item name="NumNodesOfType_Active_INPUT" rev="4">
<attrib name="value" value="10"/></item>
<item name="NumNodesOfType_Active_IOBIN2OUT" rev="4">
<attrib name="value" value="4"/></item>
<item name="NumNodesOfType_Active_IOBOUTPUT" rev="4">
<attrib name="value" value="4"/></item>
<item name="NumNodesOfType_Active_LUTINPUT" rev="4">
<attrib name="value" value="326"/></item>
<item name="NumNodesOfType_Active_OUTBOUND" rev="4">
<attrib name="value" value="113"/></item>
<item name="NumNodesOfType_Active_OUTPUT" rev="4">
<attrib name="value" value="124"/></item>
<item name="NumNodesOfType_Active_PADINPUT" rev="4">
<attrib name="value" value="3"/></item>
<item name="NumNodesOfType_Active_PADOUTPUT" rev="4">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Active_PINBOUNCE" rev="4">
<attrib name="value" value="53"/></item>
<item name="NumNodesOfType_Active_PINFEED" rev="4">
<attrib name="value" value="358"/></item>
<item name="NumNodesOfType_Active_QUAD" rev="4">
<attrib name="value" value="27"/></item>
<item name="NumNodesOfType_Active_SINGLE" rev="4">
<attrib name="value" value="150"/></item>
<item name="NumNodesOfType_Vcc_HVCCOUT" rev="4">
<attrib name="value" value="15"/></item>
<item name="NumNodesOfType_Vcc_LUTINPUT" rev="4">
<attrib name="value" value="44"/></item>
<item name="NumNodesOfType_Vcc_PINFEED" rev="4">
<attrib name="value" value="44"/></item>
</group>
<group name="SiteStatistics">
<item name="BUFG-BUFGMUX" rev="2">
<item name="BUFG-BUFGMUX" rev="4">
<attrib name="value" value="2"/></item>
<item name="IOB-IOBM" rev="2">
<item name="IOB-IOBM" rev="4">
<attrib name="value" value="10"/></item>
<item name="IOB-IOBS" rev="2">
<item name="IOB-IOBS" rev="4">
<attrib name="value" value="7"/></item>
<item name="SLICEL-SLICEM" rev="2">
<attrib name="value" value="2"/></item>
<item name="SLICEX-SLICEL" rev="2">
<attrib name="value" value="1"/></item>
<item name="SLICEX-SLICEM" rev="2">
<attrib name="value" value="2"/></item>
<item name="SLICEL-SLICEM" rev="4">
<attrib name="value" value="8"/></item>
<item name="SLICEX-SLICEL" rev="4">
<attrib name="value" value="5"/></item>
<item name="SLICEX-SLICEM" rev="4">
<attrib name="value" value="4"/></item>
</group>
<group name="MiscellaneousStatistics">
<item name="AGG_BONDED_IO" rev="1">
<item name="AGG_BONDED_IO" rev="3">
<attrib name="value" value="17"/></item>
<item name="AGG_IO" rev="1">
<item name="AGG_IO" rev="3">
<attrib name="value" value="17"/></item>
<item name="AGG_LOCED_IO" rev="1">
<item name="AGG_LOCED_IO" rev="3">
<attrib name="value" value="17"/></item>
<item name="AGG_SLICE" rev="1">
<attrib name="value" value="11"/></item>
<item name="NUM_BONDED_IOB" rev="1">
<attrib name="value" value="17"/></item>
<item name="NUM_BSFULL" rev="1">
<item name="AGG_SLICE" rev="3">
<attrib name="value" value="30"/></item>
<item name="NUM_BSLUTONLY" rev="1">
<attrib name="value" value="1"/></item>
<item name="NUM_BSUSED" rev="1">
<attrib name="value" value="31"/></item>
<item name="NUM_BUFG" rev="1">
<attrib name="value" value="2"/></item>
<item name="NUM_LOCED_IOB" rev="1">
<item name="NUM_BONDED_IOB" rev="3">
<attrib name="value" value="17"/></item>
<item name="NUM_LOGIC_O5ANDO6" rev="1">
<attrib name="value" value="4"/></item>
<item name="NUM_LOGIC_O5ONLY" rev="1">
<attrib name="value" value="11"/></item>
<item name="NUM_LOGIC_O6ONLY" rev="1">
<attrib name="value" value="14"/></item>
<item name="NUM_LUT_RT_DRIVES_CARRY4" rev="1">
<item name="NUM_BSFULL" rev="3">
<attrib name="value" value="63"/></item>
<item name="NUM_BSLUTONLY" rev="3">
<attrib name="value" value="37"/></item>
<item name="NUM_BSUSED" rev="3">
<attrib name="value" value="100"/></item>
<item name="NUM_BUFG" rev="3">
<attrib name="value" value="2"/></item>
<item name="NUM_LUT_RT_EXO6" rev="1">
<attrib name="value" value="2"/></item>
<item name="NUM_LUT_RT_O6" rev="1">
<attrib name="value" value="11"/></item>
<item name="NUM_SLICEL" rev="1">
<attrib name="value" value="5"/></item>
<item name="NUM_SLICEX" rev="1">
<attrib name="value" value="6"/></item>
<item name="NUM_SLICE_CARRY4" rev="1">
<attrib name="value" value="5"/></item>
<item name="NUM_SLICE_CONTROLSET" rev="1">
<attrib name="value" value="2"/></item>
<item name="NUM_SLICE_CYINIT" rev="1">
<attrib name="value" value="48"/></item>
<item name="NUM_SLICE_FF" rev="1">
<item name="NUM_LOCED_IOB" rev="3">
<attrib name="value" value="17"/></item>
<item name="NUM_LOGIC_O5ANDO6" rev="3">
<attrib name="value" value="32"/></item>
<item name="NUM_SLICE_UNUSEDCTRL" rev="1">
<attrib name="value" value="1"/></item>
<item name="NUM_UNUSABLE_FF_BELS" rev="1">
<item name="NUM_LOGIC_O5ONLY" rev="3">
<attrib name="value" value="12"/></item>
<item name="NUM_LOGIC_O6ONLY" rev="3">
<attrib name="value" value="54"/></item>
<item name="NUM_LUT_RT_DRIVES_CARRY4" rev="3">
<attrib name="value" value="2"/></item>
<item name="NUM_LUT_RT_EXO6" rev="3">
<attrib name="value" value="2"/></item>
<item name="NUM_LUT_RT_O6" rev="3">
<attrib name="value" value="12"/></item>
<item name="NUM_SLICEL" rev="3">
<attrib name="value" value="11"/></item>
<item name="NUM_SLICEX" rev="3">
<attrib name="value" value="19"/></item>
<item name="NUM_SLICE_CARRY4" rev="3">
<attrib name="value" value="11"/></item>
<item name="NUM_SLICE_CONTROLSET" rev="3">
<attrib name="value" value="6"/></item>
<item name="NUM_SLICE_CYINIT" rev="3">
<attrib name="value" value="147"/></item>
<item name="NUM_SLICE_FF" rev="3">
<attrib name="value" value="70"/></item>
<item name="NUM_SLICE_UNUSEDCTRL" rev="3">
<attrib name="value" value="8"/></item>
<item name="NUM_UNUSABLE_FF_BELS" rev="3">
<attrib name="value" value="26"/></item>
</group>
</DesignStatistics>
<DeviceUsage TimeStamp="Wed Jun 01 11:29:19 2022"><group name="SiteSummary">
<item name="BUFG" rev="2">
<DeviceUsage TimeStamp="Wed Jun 01 12:12:04 2022"><group name="SiteSummary">
<item name="BUFG" rev="4">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="BUFG_BUFG" rev="2">
<item name="BUFG_BUFG" rev="4">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="CARRY4" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="5"/></item>
<item name="FF_SR" rev="2">
<item name="CARRY4" rev="4">
<attrib name="total" value="1000000"/><attrib name="used" value="11"/></item>
<item name="FF_SR" rev="4">
<attrib name="total" value="1000000"/><attrib name="used" value="7"/></item>
<item name="HARD0" rev="4">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="HARD0" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="IOB" rev="2">
<item name="HARD1" rev="4">
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="IOB" rev="4">
<attrib name="total" value="1000000"/><attrib name="used" value="17"/></item>
<item name="IOB_IMUX" rev="2">
<item name="IOB_IMUX" rev="4">
<attrib name="total" value="1000000"/><attrib name="used" value="14"/></item>
<item name="IOB_INBUF" rev="2">
<item name="IOB_INBUF" rev="4">
<attrib name="total" value="1000000"/><attrib name="used" value="14"/></item>
<item name="IOB_OUTBUF" rev="2">
<item name="IOB_OUTBUF" rev="4">
<attrib name="total" value="1000000"/><attrib name="used" value="3"/></item>
<item name="LUT5" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="15"/></item>
<item name="LUT6" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="31"/></item>
<item name="PAD" rev="2">
<item name="LUT5" rev="4">
<attrib name="total" value="1000000"/><attrib name="used" value="44"/></item>
<item name="LUT6" rev="4">
<attrib name="total" value="1000000"/><attrib name="used" value="100"/></item>
<item name="PAD" rev="4">
<attrib name="total" value="1000000"/><attrib name="used" value="17"/></item>
<item name="REG_SR" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="30"/></item>
<item name="SLICEL" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="5"/></item>
<item name="SLICEX" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="6"/></item>
<item name="REG_SR" rev="4">
<attrib name="total" value="1000000"/><attrib name="used" value="63"/></item>
<item name="SLICEL" rev="4">
<attrib name="total" value="1000000"/><attrib name="used" value="11"/></item>
<item name="SLICEX" rev="4">
<attrib name="total" value="1000000"/><attrib name="used" value="19"/></item>
</group>
</DeviceUsage>
<ReportConfigData TimeStamp="Wed Jun 01 11:29:19 2022"><group name="REG_SR">
<item name="CK" rev="2">
<attrib name="CK" value="6"/><attrib name="CK_INV" value="24"/></item>
<item name="LATCH_OR_FF" rev="2">
<attrib name="FF" value="30"/></item>
<item name="SRINIT" rev="2">
<attrib name="SRINIT0" value="30"/></item>
<item name="SYNC_ATTR" rev="2">
<attrib name="ASYNC" value="30"/></item>
<ReportConfigData TimeStamp="Wed Jun 01 12:12:04 2022"><group name="REG_SR">
<item name="CK" rev="4">
<attrib name="CK" value="41"/><attrib name="CK_INV" value="22"/></item>
<item name="LATCH_OR_FF" rev="4">
<attrib name="FF" value="63"/></item>
<item name="SRINIT" rev="4">
<attrib name="SRINIT0" value="63"/></item>
<item name="SYNC_ATTR" rev="4">
<attrib name="ASYNC" value="63"/></item>
</group>
<group name="SLICEL">
<item name="CLK" rev="2">
<item name="CLK" rev="4">
<attrib name="CLK" value="2"/><attrib name="CLK_INV" value="3"/></item>
</group>
<group name="IOB_OUTBUF">
<item name="DRIVEATTRBOX" rev="2">
<item name="DRIVEATTRBOX" rev="4">
<attrib name="12" value="3"/></item>
<item name="SLEW" rev="2">
<item name="SLEW" rev="4">
<attrib name="SLOW" value="3"/></item>
<item name="SUSPEND" rev="2">
<item name="SUSPEND" rev="4">
<attrib name="3STATE" value="3"/></item>
</group>
<group name="SLICEX">
<item name="CLK" rev="2">
<attrib name="CLK" value="0"/><attrib name="CLK_INV" value="5"/></item>
<item name="CLK" rev="4">
<attrib name="CLK" value="12"/><attrib name="CLK_INV" value="5"/></item>
</group>
<group name="FF_SR">
<item name="CK" rev="2">
<attrib name="CK" value="0"/><attrib name="CK_INV" value="2"/></item>
<item name="SRINIT" rev="2">
<attrib name="SRINIT0" value="2"/></item>
<item name="SYNC_ATTR" rev="2">
<attrib name="ASYNC" value="2"/></item>
<item name="CK" rev="4">
<attrib name="CK" value="3"/><attrib name="CK_INV" value="4"/></item>
<item name="SRINIT" rev="4">
<attrib name="SRINIT0" value="7"/></item>
<item name="SYNC_ATTR" rev="4">
<attrib name="ASYNC" value="7"/></item>
</group>
</ReportConfigData>
<ReportPinData TimeStamp="Wed Jun 01 11:29:19 2022"><group name="REG_SR">
<item name="CK" rev="2">
<attrib name="value" value="30"/></item>
<item name="D" rev="2">
<attrib name="value" value="30"/></item>
<item name="Q" rev="2">
<attrib name="value" value="30"/></item>
<ReportPinData TimeStamp="Wed Jun 01 12:12:04 2022"><group name="REG_SR">
<item name="CE" rev="4">
<attrib name="value" value="10"/></item>
<item name="CK" rev="4">
<attrib name="value" value="63"/></item>
<item name="D" rev="4">
<attrib name="value" value="63"/></item>
<item name="Q" rev="4">
<attrib name="value" value="63"/></item>
<item name="SR" rev="4">
<attrib name="value" value="10"/></item>
</group>
<group name="SLICEL">
<item name="A4" rev="2">
<item name="A4" rev="4">
<attrib name="value" value="5"/></item>
<item name="A6" rev="2">
<attrib name="value" value="4"/></item>
<item name="AQ" rev="2">
<item name="A5" rev="4">
<attrib name="value" value="6"/></item>
<item name="A6" rev="4">
<attrib name="value" value="10"/></item>
<item name="AMUX" rev="4">
<attrib name="value" value="6"/></item>
<item name="AQ" rev="4">
<attrib name="value" value="5"/></item>
<item name="B4" rev="2">
<item name="B4" rev="4">
<attrib name="value" value="4"/></item>
<item name="B6" rev="2">
<attrib name="value" value="3"/></item>
<item name="BQ" rev="2">
<item name="B5" rev="4">
<attrib name="value" value="6"/></item>
<item name="B6" rev="4">
<attrib name="value" value="9"/></item>
<item name="BMUX" rev="4">
<attrib name="value" value="6"/></item>
<item name="BQ" rev="4">
<attrib name="value" value="4"/></item>
<item name="C4" rev="2">
<item name="C4" rev="4">
<attrib name="value" value="3"/></item>
<item name="C6" rev="2">
<attrib name="value" value="3"/></item>
<item name="CIN" rev="2">
<attrib name="value" value="3"/></item>
<item name="CLK" rev="2">
<item name="C5" rev="4">
<attrib name="value" value="6"/></item>
<item name="C6" rev="4">
<attrib name="value" value="9"/></item>
<item name="CIN" rev="4">
<attrib name="value" value="8"/></item>
<item name="CLK" rev="4">
<attrib name="value" value="5"/></item>
<item name="COUT" rev="2">
<item name="CMUX" rev="4">
<attrib name="value" value="6"/></item>
<item name="COUT" rev="4">
<attrib name="value" value="8"/></item>
<item name="CQ" rev="4">
<attrib name="value" value="3"/></item>
<item name="CQ" rev="2">
<item name="D4" rev="4">
<attrib name="value" value="3"/></item>
<item name="D4" rev="2">
<attrib name="value" value="3"/></item>
<item name="D6" rev="2">
<attrib name="value" value="3"/></item>
<item name="DQ" rev="2">
<item name="D5" rev="4">
<attrib name="value" value="5"/></item>
<item name="D6" rev="4">
<attrib name="value" value="9"/></item>
<item name="DMUX" rev="4">
<attrib name="value" value="6"/></item>
<item name="DQ" rev="4">
<attrib name="value" value="3"/></item>
</group>
<group name="IOB_OUTBUF">
<item name="IN" rev="2">
<item name="IN" rev="4">
<attrib name="value" value="3"/></item>
<item name="OUT" rev="2">
<item name="OUT" rev="4">
<attrib name="value" value="3"/></item>
</group>
<group name="SLICEX">
<item name="A" rev="2">
<attrib name="value" value="1"/></item>
<item name="A2" rev="2">
<item name="A" rev="4">
<attrib name="value" value="2"/></item>
<item name="A3" rev="2">
<item name="A1" rev="4">
<attrib name="value" value="3"/></item>
<item name="A4" rev="2">
<item name="A2" rev="4">
<attrib name="value" value="12"/></item>
<item name="A3" rev="4">
<attrib name="value" value="12"/></item>
<item name="A4" rev="4">
<attrib name="value" value="14"/></item>
<item name="A5" rev="4">
<attrib name="value" value="12"/></item>
<item name="A6" rev="4">
<attrib name="value" value="12"/></item>
<item name="AMUX" rev="4">
<attrib name="value" value="1"/></item>
<item name="AQ" rev="4">
<attrib name="value" value="12"/></item>
<item name="B" rev="4">
<attrib name="value" value="5"/></item>
<item name="A5" rev="2">
<attrib name="value" value="4"/></item>
<item name="A6" rev="2">
<attrib name="value" value="6"/></item>
<item name="AMUX" rev="2">
<attrib name="value" value="1"/></item>
<item name="AQ" rev="2">
<item name="B1" rev="4">
<attrib name="value" value="8"/></item>
<item name="B2" rev="4">
<attrib name="value" value="14"/></item>
<item name="B3" rev="4">
<attrib name="value" value="14"/></item>
<item name="B4" rev="4">
<attrib name="value" value="14"/></item>
<item name="B5" rev="4">
<attrib name="value" value="14"/></item>
<item name="B6" rev="4">
<attrib name="value" value="14"/></item>
<item name="BMUX" rev="4">
<attrib name="value" value="2"/></item>
<item name="BQ" rev="4">
<attrib name="value" value="9"/></item>
<item name="C" rev="4">
<attrib name="value" value="2"/></item>
<item name="C1" rev="4">
<attrib name="value" value="5"/></item>
<item name="B1" rev="2">
<attrib name="value" value="1"/></item>
<item name="B2" rev="2">
<item name="C2" rev="4">
<attrib name="value" value="14"/></item>
<item name="C3" rev="4">
<attrib name="value" value="14"/></item>
<item name="C4" rev="4">
<attrib name="value" value="15"/></item>
<item name="C5" rev="4">
<attrib name="value" value="15"/></item>
<item name="C6" rev="4">
<attrib name="value" value="15"/></item>
<item name="CE" rev="4">
<attrib name="value" value="4"/></item>
<item name="CLK" rev="4">
<attrib name="value" value="17"/></item>
<item name="CMUX" rev="4">
<attrib name="value" value="3"/></item>
<item name="CQ" rev="4">
<attrib name="value" value="13"/></item>
<item name="D" rev="4">
<attrib name="value" value="4"/></item>
<item name="D1" rev="4">
<attrib name="value" value="3"/></item>
<item name="D2" rev="4">
<attrib name="value" value="11"/></item>
<item name="D3" rev="4">
<attrib name="value" value="12"/></item>
<item name="D4" rev="4">
<attrib name="value" value="14"/></item>
<item name="D5" rev="4">
<attrib name="value" value="16"/></item>
<item name="D6" rev="4">
<attrib name="value" value="18"/></item>
<item name="DMUX" rev="4">
<attrib name="value" value="2"/></item>
<item name="B3" rev="2">
<item name="DQ" rev="4">
<attrib name="value" value="14"/></item>
<item name="SR" rev="4">
<attrib name="value" value="4"/></item>
<item name="B4" rev="2">
<attrib name="value" value="4"/></item>
<item name="B5" rev="2">
<attrib name="value" value="4"/></item>
<item name="B6" rev="2">
<attrib name="value" value="4"/></item>
<item name="BMUX" rev="2">
<attrib name="value" value="1"/></item>
<item name="BQ" rev="2">
<attrib name="value" value="4"/></item>
<item name="C1" rev="2">
<attrib name="value" value="2"/></item>
<item name="C2" rev="2">
<attrib name="value" value="3"/></item>
<item name="C3" rev="2">
<attrib name="value" value="3"/></item>
<item name="C4" rev="2">
<attrib name="value" value="3"/></item>
<item name="C5" rev="2">
<attrib name="value" value="3"/></item>
<item name="C6" rev="2">
<attrib name="value" value="3"/></item>
<item name="CLK" rev="2">
<attrib name="value" value="5"/></item>
<item name="CQ" rev="2">
<attrib name="value" value="3"/></item>
<item name="D1" rev="2">
<attrib name="value" value="2"/></item>
<item name="D2" rev="2">
<attrib name="value" value="3"/></item>
<item name="D3" rev="2">
<attrib name="value" value="3"/></item>
<item name="D4" rev="2">
<attrib name="value" value="3"/></item>
<item name="D5" rev="2">
<attrib name="value" value="3"/></item>
<item name="D6" rev="2">
<attrib name="value" value="3"/></item>
<item name="DQ" rev="2">
<attrib name="value" value="3"/></item>
</group>
<group name="BUFG_BUFG">
<item name="I0" rev="2">
<item name="I0" rev="4">
<attrib name="value" value="2"/></item>
<item name="O" rev="2">
<item name="O" rev="4">
<attrib name="value" value="2"/></item>
</group>
<group name="PAD">
<item name="PAD" rev="2">
<item name="PAD" rev="4">
<attrib name="value" value="17"/></item>
</group>
<group name="IOB_INBUF">
<item name="OUT" rev="2">
<item name="OUT" rev="4">
<attrib name="value" value="14"/></item>
<item name="PAD" rev="2">
<item name="PAD" rev="4">
<attrib name="value" value="14"/></item>
</group>
<group name="CARRY4">
<item name="CIN" rev="2">
<attrib name="value" value="3"/></item>
<item name="CO3" rev="2">
<attrib name="value" value="3"/></item>
<item name="CYINIT" rev="2">
<attrib name="value" value="2"/></item>
<item name="DI0" rev="2">
<attrib name="value" value="4"/></item>
<item name="DI1" rev="2">
<attrib name="value" value="3"/></item>
<item name="DI2" rev="2">
<attrib name="value" value="3"/></item>
<item name="DI3" rev="2">
<attrib name="value" value="3"/></item>
<item name="O0" rev="2">
<attrib name="value" value="5"/></item>
<item name="O1" rev="2">
<attrib name="value" value="4"/></item>
<item name="O2" rev="2">
<attrib name="value" value="3"/></item>
<item name="O3" rev="2">
<attrib name="value" value="3"/></item>
<item name="S0" rev="2">
<attrib name="value" value="5"/></item>
<item name="S1" rev="2">
<attrib name="value" value="4"/></item>
<item name="S2" rev="2">
<attrib name="value" value="3"/></item>
<item name="S3" rev="2">
<item name="CIN" rev="4">
<attrib name="value" value="8"/></item>
<item name="CO3" rev="4">
<attrib name="value" value="8"/></item>
<item name="CYINIT" rev="4">
<attrib name="value" value="3"/></item>
<item name="DI0" rev="4">
<attrib name="value" value="10"/></item>
<item name="DI1" rev="4">
<attrib name="value" value="9"/></item>
<item name="DI2" rev="4">
<attrib name="value" value="9"/></item>
<item name="DI3" rev="4">
<attrib name="value" value="8"/></item>
<item name="O0" rev="4">
<attrib name="value" value="11"/></item>
<item name="O1" rev="4">
<attrib name="value" value="10"/></item>
<item name="O2" rev="4">
<attrib name="value" value="9"/></item>
<item name="O3" rev="4">
<attrib name="value" value="9"/></item>
<item name="S0" rev="4">
<attrib name="value" value="11"/></item>
<item name="S1" rev="4">
<attrib name="value" value="10"/></item>
<item name="S2" rev="4">
<attrib name="value" value="9"/></item>
<item name="S3" rev="4">
<attrib name="value" value="9"/></item>
</group>
<group name="LUT5">
<item name="A3" rev="2">
<attrib name="value" value="2"/></item>
<item name="A5" rev="2">
<attrib name="value" value="2"/></item>
<item name="O5" rev="2">
<attrib name="value" value="15"/></item>
<item name="A1" rev="4">
<attrib name="value" value="6"/></item>
<item name="A2" rev="4">
<attrib name="value" value="6"/></item>
<item name="A3" rev="4">
<attrib name="value" value="7"/></item>
<item name="A4" rev="4">
<attrib name="value" value="7"/></item>
<item name="A5" rev="4">
<attrib name="value" value="3"/></item>
<item name="O5" rev="4">
<attrib name="value" value="44"/></item>
</group>
<group name="LUT6">
<item name="A1" rev="2">
<attrib name="value" value="5"/></item>
<item name="A2" rev="2">
<attrib name="value" value="10"/></item>
<item name="A3" rev="2">
<attrib name="value" value="11"/></item>
<item name="A4" rev="2">
<attrib name="value" value="30"/></item>
<item name="A5" rev="2">
<attrib name="value" value="14"/></item>
<item name="A6" rev="2">
<attrib name="value" value="29"/></item>
<item name="O6" rev="2">
<attrib name="value" value="31"/></item>
<item name="A1" rev="4">
<attrib name="value" value="15"/></item>
<item name="A2" rev="4">
<attrib name="value" value="48"/></item>
<item name="A3" rev="4">
<attrib name="value" value="49"/></item>
<item name="A4" rev="4">
<attrib name="value" value="72"/></item>
<item name="A5" rev="4">
<attrib name="value" value="80"/></item>
<item name="A6" rev="4">
<attrib name="value" value="96"/></item>
<item name="O6" rev="4">
<attrib name="value" value="100"/></item>
</group>
<group name="IOB_IMUX">
<item name="I" rev="2">
<item name="I" rev="4">
<attrib name="value" value="14"/></item>
<item name="OUT" rev="2">
<item name="OUT" rev="4">
<attrib name="value" value="14"/></item>
</group>
<group name="IOB">
<item name="I" rev="2">
<item name="I" rev="4">
<attrib name="value" value="14"/></item>
<item name="O" rev="2">
<item name="O" rev="4">
<attrib name="value" value="3"/></item>
<item name="PAD" rev="2">
<item name="PAD" rev="4">
<attrib name="value" value="17"/></item>
</group>
<group name="HARD0">
<item name="0" rev="2">
<item name="0" rev="4">
<attrib name="value" value="2"/></item>
</group>
<group name="HARD1">
<item name="1" rev="4">
<attrib name="value" value="1"/></item>
</group>
<group name="FF_SR">
<item name="CK" rev="2">
<item name="CE" rev="4">
<attrib name="value" value="2"/></item>
<item name="D" rev="2">
<attrib name="value" value="2"/></item>
<item name="Q" rev="2">
<item name="CK" rev="4">
<attrib name="value" value="7"/></item>
<item name="D" rev="4">
<attrib name="value" value="7"/></item>
<item name="Q" rev="4">
<attrib name="value" value="7"/></item>
<item name="SR" rev="4">
<attrib name="value" value="2"/></item>
</group>
<group name="BUFG">
<item name="I0" rev="2">
<item name="I0" rev="4">
<attrib name="value" value="2"/></item>
<item name="O" rev="2">
<item name="O" rev="4">
<attrib name="value" value="2"/></item>
</group>
</ReportPinData>

85
textovhdl_xst.xrpt
View File

@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Wed Jun 01 11:28:21 2022">
<application stringID="Xst" timeStamp="Wed Jun 01 12:11:10 2022">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@@ -103,14 +103,20 @@
</section>
<section stringID="XST_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_RAMS" value="1"></item>
<item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="2"></item>
<item dataType="int" stringID="XST_REGISTERS" value="4">
<item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="6">
<item dataType="int" stringID="XST_4BIT_ADDER" value="3"/>
</item>
<item dataType="int" stringID="XST_REGISTERS" value="9">
<item dataType="int" stringID="XST_1BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_16BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_2BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_4BIT_REGISTER" value="3"/>
<item dataType="int" stringID="XST_9BIT_REGISTER" value="1"/>
</item>
<item dataType="int" stringID="XST_MULTIPLEXERS" value="4">
<item dataType="int" stringID="XST_16BIT_2TO1_MULTIPLEXER" value="4"/>
<item dataType="int" stringID="XST_MULTIPLEXERS" value="20">
<item dataType="int" stringID="XST_1BIT_2TO1_MULTIPLEXER" value="3"/>
<item dataType="int" stringID="XST_16BIT_2TO1_MULTIPLEXER" value="5"/>
<item dataType="int" stringID="XST_4BIT_2TO1_MULTIPLEXER" value="10"/>
</item>
<item dataType="int" stringID="XST_TRISTATES" value="4">
<item dataType="int" stringID="XST_1BIT_TRISTATE_BUFFER" value="4"/>
@@ -118,19 +124,24 @@
</section>
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_RAMS" value="1"></item>
<item dataType="int" stringID="XST_COUNTERS" value="2">
<item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="3">
<item dataType="int" stringID="XST_4BIT_ADDER" value="3"/>
</item>
<item dataType="int" stringID="XST_COUNTERS" value="3">
<item dataType="int" stringID="XST_9BIT_UP_COUNTER" value="1"/>
</item>
<item dataType="int" stringID="XST_REGISTERS" value="17">
<item dataType="int" stringID="XST_FLIPFLOPS" value="17"/>
<item dataType="int" stringID="XST_REGISTERS" value="31">
<item dataType="int" stringID="XST_FLIPFLOPS" value="31"/>
</item>
<item dataType="int" stringID="XST_MULTIPLEXERS" value="4">
<item dataType="int" stringID="XST_16BIT_2TO1_MULTIPLEXER" value="4"/>
<item dataType="int" stringID="XST_MULTIPLEXERS" value="19">
<item dataType="int" stringID="XST_1BIT_2TO1_MULTIPLEXER" value="3"/>
<item dataType="int" stringID="XST_16BIT_2TO1_MULTIPLEXER" value="5"/>
<item dataType="int" stringID="XST_4BIT_2TO1_MULTIPLEXER" value="10"/>
</item>
</section>
<section stringID="XST_FINAL_REGISTER_REPORT">
<item dataType="int" stringID="XST_REGISTERS" value="32">
<item dataType="int" stringID="XST_FLIPFLOPS" value="32"/>
<item dataType="int" stringID="XST_REGISTERS" value="70">
<item dataType="int" stringID="XST_FLIPFLOPS" value="70"/>
</item>
</section>
<section stringID="XST_PARTITION_REPORT">
@@ -143,28 +154,30 @@
<item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="textovhdl.ngc"/>
</section>
<section stringID="XST_PRIMITIVE_AND_BLACK_BOX_USAGE">
<item dataType="int" stringID="XST_BELS" value="64">
<item dataType="int" stringID="XST_BELS" value="188">
<item dataType="int" stringID="XST_GND" value="1"/>
<item dataType="int" stringID="XST_INV" value="4"/>
<item dataType="int" stringID="XST_LUT1" value="13"/>
<item dataType="int" stringID="XST_LUT2" value="5"/>
<item dataType="int" stringID="XST_LUT3" value="1"/>
<item dataType="int" stringID="XST_LUT4" value="1"/>
<item dataType="int" stringID="XST_LUT5" value="5"/>
<item dataType="int" stringID="XST_LUT6" value="5"/>
<item dataType="int" stringID="XST_MUXCY" value="13"/>
<item dataType="int" stringID="XST_INV" value="30"/>
<item dataType="int" stringID="XST_LUT1" value="14"/>
<item dataType="int" stringID="XST_LUT2" value="7"/>
<item dataType="int" stringID="XST_LUT3" value="8"/>
<item dataType="int" stringID="XST_LUT4" value="5"/>
<item dataType="int" stringID="XST_LUT5" value="34"/>
<item dataType="int" stringID="XST_LUT6" value="13"/>
<item dataType="int" stringID="XST_MUXCY" value="36"/>
<item dataType="int" stringID="XST_VCC" value="1"/>
<item dataType="int" stringID="XST_XORCY" value="15"/>
<item dataType="int" stringID="XST_XORCY" value="39"/>
</item>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="32">
<item dataType="int" stringID="XST_FD" value="15"/>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="70">
<item dataType="int" stringID="XST_FD" value="41"/>
<item dataType="int" stringID="XST_FD1" value="17"/>
<item dataType="int" stringID="XST_FDCE" value="12"/>
</item>
<item dataType="int" stringID="XST_CLOCK_BUFFERS" value="2">
<item dataType="int" label="-bufg" stringID="XST_BUFG" value="1"/>
<item dataType="int" stringID="XST_BUFGP" value="1"/>
</item>
<item dataType="int" stringID="XST_IO_BUFFERS" value="7">
<item dataType="int" stringID="XST_IO_BUFFERS" value="8">
<item dataType="int" stringID="XST_IBUF" value="1"/>
<item dataType="int" stringID="XST_OBUF" value="3"/>
<item dataType="int" stringID="XST_OBUFT" value="4"/>
</item>
@@ -172,16 +185,16 @@
</section>
<section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
<item stringID="XST_SELECTED_DEVICE" value="6slx16csg324-2"/>
<item AVAILABLE="18224" dataType="int" label="Number of Slice Registers" stringID="XST_NUMBER_OF_SLICE_REGISTERS" value="32"/>
<item AVAILABLE="9112" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="34"/>
<item AVAILABLE="9112" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="34"/>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="34"/>
<item AVAILABLE="34" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="2"/>
<item AVAILABLE="34" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="0"/>
<item AVAILABLE="34" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="32"/>
<item dataType="int" label="Number of unique control sets" stringID="XST_NUMBER_OF_UNIQUE_CONTROL_SETS" value="3"/>
<item AVAILABLE="18224" dataType="int" label="Number of Slice Registers" stringID="XST_NUMBER_OF_SLICE_REGISTERS" value="70"/>
<item AVAILABLE="9112" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="111"/>
<item AVAILABLE="9112" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="111"/>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="111"/>
<item AVAILABLE="111" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="41"/>
<item AVAILABLE="111" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="0"/>
<item AVAILABLE="111" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="70"/>
<item dataType="int" label="Number of unique control sets" stringID="XST_NUMBER_OF_UNIQUE_CONTROL_SETS" value="7"/>
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="21"/>
<item AVAILABLE="232" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="8"/>
<item AVAILABLE="232" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="9"/>
<item AVAILABLE="16" dataType="int" label="Number of BUFG/BUFGCTRLs" stringID="XST_NUMBER_OF_BUFGBUFGCTRLS" value="2"/>
</section>
<section stringID="XST_PARTITION_RESOURCE_SUMMARY">
@@ -189,8 +202,8 @@
</section>
<section stringID="XST_ERRORS_STATISTICS">
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="32"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="1"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="30"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="3"/>
</section>
</application>

342
usage_statistics_webtalk.html
View File

@@ -17,7 +17,7 @@
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project ID (random number)</B></TD>
<TD><xtag-property name="RandomID">bd16c3ee05c44948bef10dae3c70184a</xtag-property>.<xtag-property name="ProjectID">C59F24DEFAA841F7B8F7FB3A62750569</xtag-property>.<xtag-property name="ProjectIteration">1</xtag-property></TD>
<TD><xtag-property name="RandomID">bd16c3ee05c44948bef10dae3c70184a</xtag-property>.<xtag-property name="ProjectID">C59F24DEFAA841F7B8F7FB3A62750569</xtag-property>.<xtag-property name="ProjectIteration">2</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Package:</B></TD>
<TD><xtag-property name="TargetPackage">csg324</xtag-property></TD>
</TR>
@@ -29,7 +29,7 @@
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Date Generated</B></TD>
<TD><xtag-property name="Date Generated">2022-06-01T11:29:20</xtag-property></TD>
<TD><xtag-property name="Date Generated">2022-06-01T12:12:04</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Tool Flow</B></TD>
<TD><xtag-property name="ToolFlow">ISE</xtag-property></TD>
</TR>
@@ -67,15 +67,24 @@
<TR ALIGN=CENTER BGCOLOR='#FFFF99'><TD><B>Macro Statistics</B></TD><TD><B>Miscellaneous Statistics</B></TD><TD><B>Net Statistics</B></TD><TD><B>Site Usage</B></TD></TR><TR VALIGN=TOP>
<xtag-section name="MacroStatistics">
<TD>
<xtag-group><xtag-group-name name="Counters=2">Counters=2</xtag-group-name>
<xtag-group><xtag-group-name name="Adders/Subtractors=3">Adders/Subtractors=3</xtag-group-name>
<UL>
<LI><xtag-item1>4-bit adder=3</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="Counters=3">Counters=3</xtag-group-name>
<UL>
<LI><xtag-item1>24-bit down counter=1</xtag-item1></LI>
<LI><xtag-item1>24-bit up counter=1</xtag-item1></LI>
<LI><xtag-item1>9-bit up counter=1</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="Multiplexers=4">Multiplexers=4</xtag-group-name>
<xtag-group><xtag-group-name name="Multiplexers=19">Multiplexers=19</xtag-group-name>
<UL>
<LI><xtag-item1>16-bit 2-to-1 multiplexer=4</xtag-item1></LI>
<LI><xtag-item1>1-bit 2-to-1 multiplexer=3</xtag-item1></LI>
<LI><xtag-item1>16-bit 2-to-1 multiplexer=5</xtag-item1></LI>
<LI><xtag-item1>2-bit 4-to-1 multiplexer=1</xtag-item1></LI>
<LI><xtag-item1>4-bit 2-to-1 multiplexer=10</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="RAMs=1">RAMs=1</xtag-group-name>
@@ -83,9 +92,9 @@
<LI><xtag-item1>8x4-bit single-port distributed Read Only RAM=1</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="Registers=17">Registers=17</xtag-group-name>
<xtag-group><xtag-group-name name="Registers=31">Registers=31</xtag-group-name>
<UL>
<LI><xtag-item1>Flip-Flops=17</xtag-item1></LI>
<LI><xtag-item1>Flip-Flops=31</xtag-item1></LI>
</UL>
</xtag-group>
</TD>
@@ -97,59 +106,60 @@
<LI><xtag-item1>AGG_BONDED_IO=17</xtag-item1></LI>
<LI><xtag-item1>AGG_IO=17</xtag-item1></LI>
<LI><xtag-item1>AGG_LOCED_IO=17</xtag-item1></LI>
<LI><xtag-item1>AGG_SLICE=11</xtag-item1></LI>
<LI><xtag-item1>AGG_SLICE=30</xtag-item1></LI>
<LI><xtag-item1>NUM_BONDED_IOB=17</xtag-item1></LI>
<LI><xtag-item1>NUM_BSFULL=30</xtag-item1></LI>
<LI><xtag-item1>NUM_BSLUTONLY=1</xtag-item1></LI>
<LI><xtag-item1>NUM_BSUSED=31</xtag-item1></LI>
<LI><xtag-item1>NUM_BSFULL=63</xtag-item1></LI>
<LI><xtag-item1>NUM_BSLUTONLY=37</xtag-item1></LI>
<LI><xtag-item1>NUM_BSUSED=100</xtag-item1></LI>
<LI><xtag-item1>NUM_BUFG=2</xtag-item1></LI>
<LI><xtag-item1>NUM_LOCED_IOB=17</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O5ANDO6=4</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O5ONLY=11</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O6ONLY=14</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O5ANDO6=32</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O5ONLY=12</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O6ONLY=54</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_DRIVES_CARRY4=2</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_EXO6=2</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_O6=11</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEL=5</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEX=6</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CARRY4=5</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CONTROLSET=2</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CYINIT=48</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_FF=32</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_UNUSEDCTRL=1</xtag-item1></LI>
<LI><xtag-item1>NUM_UNUSABLE_FF_BELS=8</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_O6=12</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEL=11</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEX=19</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CARRY4=11</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CONTROLSET=6</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CYINIT=147</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_FF=70</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_UNUSEDCTRL=8</xtag-item1></LI>
<LI><xtag-item1>NUM_UNUSABLE_FF_BELS=26</xtag-item1></LI>
</UL>
</xtag-group>
</TD>
<TD>
<xtag-group><xtag-group-name name="NetStatistics">NetStatistics</xtag-group-name>
<UL>
<LI><xtag-item1>NumNets_Active=69</xtag-item1></LI>
<LI><xtag-item1>NumNets_Active=149</xtag-item1></LI>
<LI><xtag-item1>NumNets_Vcc=1</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEACROSS=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEIN=6</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEIN=14</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BUFGOUT=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BUFHINP2OUT=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=10</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPINFEED=6</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=8</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GENERIC=4</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=14</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_INPUT=5</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBIN2OUT=3</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBOUTPUT=3</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_LUTINPUT=86</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTBOUND=33</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=39</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BUFHINP2OUT=5</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=22</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPINFEED=9</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CNTRLPIN=8</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=78</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GENERIC=6</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=25</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_INPUT=10</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBIN2OUT=4</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBOUTPUT=4</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_LUTINPUT=326</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTBOUND=113</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=124</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PADINPUT=3</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PADOUTPUT=1</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINBOUNCE=19</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINFEED=102</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_QUAD=22</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_SINGLE=20</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_HVCCOUT=5</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_LUTINPUT=15</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PINFEED=15</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PADOUTPUT=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINBOUNCE=53</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINFEED=358</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_QUAD=27</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_SINGLE=150</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_HVCCOUT=15</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_LUTINPUT=44</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PINFEED=44</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SiteStatistics">SiteStatistics</xtag-group-name>
@@ -157,9 +167,9 @@
<LI><xtag-item1>BUFG-BUFGMUX=2</xtag-item1></LI>
<LI><xtag-item1>IOB-IOBM=10</xtag-item1></LI>
<LI><xtag-item1>IOB-IOBS=7</xtag-item1></LI>
<LI><xtag-item1>SLICEL-SLICEM=2</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEL=1</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEM=2</xtag-item1></LI>
<LI><xtag-item1>SLICEL-SLICEM=8</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEL=5</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEM=4</xtag-item1></LI>
</UL>
</xtag-group>
</TD>
@@ -170,19 +180,20 @@
<UL>
<LI><xtag-item2>BUFG=2</xtag-item2></LI>
<LI><xtag-item2>BUFG_BUFG=2</xtag-item2></LI>
<LI><xtag-item2>CARRY4=5</xtag-item2></LI>
<LI><xtag-item2>FF_SR=2</xtag-item2></LI>
<LI><xtag-item2>CARRY4=11</xtag-item2></LI>
<LI><xtag-item2>FF_SR=7</xtag-item2></LI>
<LI><xtag-item2>HARD0=2</xtag-item2></LI>
<LI><xtag-item2>HARD1=1</xtag-item2></LI>
<LI><xtag-item2>IOB=17</xtag-item2></LI>
<LI><xtag-item2>IOB_IMUX=14</xtag-item2></LI>
<LI><xtag-item2>IOB_INBUF=14</xtag-item2></LI>
<LI><xtag-item2>IOB_OUTBUF=3</xtag-item2></LI>
<LI><xtag-item2>LUT5=15</xtag-item2></LI>
<LI><xtag-item2>LUT6=31</xtag-item2></LI>
<LI><xtag-item2>LUT5=44</xtag-item2></LI>
<LI><xtag-item2>LUT6=100</xtag-item2></LI>
<LI><xtag-item2>PAD=17</xtag-item2></LI>
<LI><xtag-item2>REG_SR=30</xtag-item2></LI>
<LI><xtag-item2>SLICEL=5</xtag-item2></LI>
<LI><xtag-item2>SLICEX=6</xtag-item2></LI>
<LI><xtag-item2>REG_SR=63</xtag-item2></LI>
<LI><xtag-item2>SLICEL=11</xtag-item2></LI>
<LI><xtag-item2>SLICEX=19</xtag-item2></LI>
</UL>
</xtag-group>
</TD>
@@ -194,9 +205,9 @@
<TD>
<xtag-group><xtag-group-name name="FF_SR">FF_SR</xtag-group-name>
<UL>
<LI><xtag-item3>CK=[CK:0] [CK_INV:2]</xtag-item3></LI>
<LI><xtag-item3>SRINIT=[SRINIT0:2]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:2]</xtag-item3></LI>
<LI><xtag-item3>CK=[CK:3] [CK_INV:4]</xtag-item3></LI>
<LI><xtag-item3>SRINIT=[SRINIT0:7]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:7]</xtag-item3></LI>
</UL>
</TD>
<TD>
@@ -212,10 +223,10 @@
</xtag-group>
<xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name>
<UL>
<LI><xtag-item3>CK=[CK:6] [CK_INV:24]</xtag-item3></LI>
<LI><xtag-item3>LATCH_OR_FF=[FF:30]</xtag-item3></LI>
<LI><xtag-item3>SRINIT=[SRINIT0:30]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:30]</xtag-item3></LI>
<LI><xtag-item3>CK=[CK:41] [CK_INV:22]</xtag-item3></LI>
<LI><xtag-item3>LATCH_OR_FF=[FF:63]</xtag-item3></LI>
<LI><xtag-item3>SRINIT=[SRINIT0:63]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:63]</xtag-item3></LI>
</UL>
</TD>
<TD>
@@ -227,7 +238,7 @@
</xtag-group>
<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name>
<UL>
<LI><xtag-item3>CLK=[CLK:0] [CLK_INV:5]</xtag-item3></LI>
<LI><xtag-item3>CLK=[CLK:12] [CLK_INV:5]</xtag-item3></LI>
</UL>
</xtag-group>
</TD>
@@ -251,36 +262,41 @@
</xtag-group>
<xtag-group><xtag-group-name name="CARRY4">CARRY4</xtag-group-name>
<UL>
<LI><xtag-item1>CIN=3</xtag-item1></LI>
<LI><xtag-item1>CO3=3</xtag-item1></LI>
<LI><xtag-item1>CYINIT=2</xtag-item1></LI>
<LI><xtag-item1>DI0=4</xtag-item1></LI>
<LI><xtag-item1>DI1=3</xtag-item1></LI>
<LI><xtag-item1>DI2=3</xtag-item1></LI>
<LI><xtag-item1>DI3=3</xtag-item1></LI>
<LI><xtag-item1>O0=5</xtag-item1></LI>
<LI><xtag-item1>O1=4</xtag-item1></LI>
<LI><xtag-item1>O2=3</xtag-item1></LI>
<LI><xtag-item1>O3=3</xtag-item1></LI>
<LI><xtag-item1>S0=5</xtag-item1></LI>
<LI><xtag-item1>S1=4</xtag-item1></LI>
<LI><xtag-item1>S2=3</xtag-item1></LI>
<LI><xtag-item1>S3=3</xtag-item1></LI>
<LI><xtag-item1>CIN=8</xtag-item1></LI>
<LI><xtag-item1>CO3=8</xtag-item1></LI>
<LI><xtag-item1>CYINIT=3</xtag-item1></LI>
<LI><xtag-item1>DI0=10</xtag-item1></LI>
<LI><xtag-item1>DI1=9</xtag-item1></LI>
<LI><xtag-item1>DI2=9</xtag-item1></LI>
<LI><xtag-item1>DI3=8</xtag-item1></LI>
<LI><xtag-item1>O0=11</xtag-item1></LI>
<LI><xtag-item1>O1=10</xtag-item1></LI>
<LI><xtag-item1>O2=9</xtag-item1></LI>
<LI><xtag-item1>O3=9</xtag-item1></LI>
<LI><xtag-item1>S0=11</xtag-item1></LI>
<LI><xtag-item1>S1=10</xtag-item1></LI>
<LI><xtag-item1>S2=9</xtag-item1></LI>
<LI><xtag-item1>S3=9</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="FF_SR">FF_SR</xtag-group-name>
<UL>
<LI><xtag-item1>CK=2</xtag-item1></LI>
<LI><xtag-item1>D=2</xtag-item1></LI>
<LI><xtag-item1>Q=2</xtag-item1></LI>
<LI><xtag-item1>CE=2</xtag-item1></LI>
<LI><xtag-item1>CK=7</xtag-item1></LI>
<LI><xtag-item1>D=7</xtag-item1></LI>
<LI><xtag-item1>Q=7</xtag-item1></LI>
<LI><xtag-item1>SR=2</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="HARD0">HARD0</xtag-group-name>
<UL>
<LI><xtag-item1>0=2</xtag-item1></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="HARD1">HARD1</xtag-group-name>
<UL>
<LI><xtag-item1>1=1</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOB">IOB</xtag-group-name>
<UL>
@@ -288,6 +304,8 @@
<LI><xtag-item1>O=3</xtag-item1></LI>
<LI><xtag-item1>PAD=17</xtag-item1></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="IOB_IMUX">IOB_IMUX</xtag-group-name>
<UL>
@@ -309,20 +327,23 @@
</xtag-group>
<xtag-group><xtag-group-name name="LUT5">LUT5</xtag-group-name>
<UL>
<LI><xtag-item1>A3=2</xtag-item1></LI>
<LI><xtag-item1>A5=2</xtag-item1></LI>
<LI><xtag-item1>O5=15</xtag-item1></LI>
<LI><xtag-item1>A1=6</xtag-item1></LI>
<LI><xtag-item1>A2=6</xtag-item1></LI>
<LI><xtag-item1>A3=7</xtag-item1></LI>
<LI><xtag-item1>A4=7</xtag-item1></LI>
<LI><xtag-item1>A5=3</xtag-item1></LI>
<LI><xtag-item1>O5=44</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="LUT6">LUT6</xtag-group-name>
<UL>
<LI><xtag-item1>A1=5</xtag-item1></LI>
<LI><xtag-item1>A2=10</xtag-item1></LI>
<LI><xtag-item1>A3=11</xtag-item1></LI>
<LI><xtag-item1>A4=30</xtag-item1></LI>
<LI><xtag-item1>A5=14</xtag-item1></LI>
<LI><xtag-item1>A6=29</xtag-item1></LI>
<LI><xtag-item1>O6=31</xtag-item1></LI>
<LI><xtag-item1>A1=15</xtag-item1></LI>
<LI><xtag-item1>A2=48</xtag-item1></LI>
<LI><xtag-item1>A3=49</xtag-item1></LI>
<LI><xtag-item1>A4=72</xtag-item1></LI>
<LI><xtag-item1>A5=80</xtag-item1></LI>
<LI><xtag-item1>A6=96</xtag-item1></LI>
<LI><xtag-item1>O6=100</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="PAD">PAD</xtag-group-name>
@@ -332,65 +353,83 @@
</xtag-group>
<xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name>
<UL>
<LI><xtag-item1>CK=30</xtag-item1></LI>
<LI><xtag-item1>D=30</xtag-item1></LI>
<LI><xtag-item1>Q=30</xtag-item1></LI>
<LI><xtag-item1>CE=10</xtag-item1></LI>
<LI><xtag-item1>CK=63</xtag-item1></LI>
<LI><xtag-item1>D=63</xtag-item1></LI>
<LI><xtag-item1>Q=63</xtag-item1></LI>
<LI><xtag-item1>SR=10</xtag-item1></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name>
<UL>
<LI><xtag-item1>A4=5</xtag-item1></LI>
<LI><xtag-item1>A6=4</xtag-item1></LI>
<LI><xtag-item1>A5=6</xtag-item1></LI>
<LI><xtag-item1>A6=10</xtag-item1></LI>
<LI><xtag-item1>AMUX=6</xtag-item1></LI>
<LI><xtag-item1>AQ=5</xtag-item1></LI>
<LI><xtag-item1>B4=4</xtag-item1></LI>
<LI><xtag-item1>B6=3</xtag-item1></LI>
<LI><xtag-item1>B5=6</xtag-item1></LI>
<LI><xtag-item1>B6=9</xtag-item1></LI>
<LI><xtag-item1>BMUX=6</xtag-item1></LI>
<LI><xtag-item1>BQ=4</xtag-item1></LI>
<LI><xtag-item1>C4=3</xtag-item1></LI>
<LI><xtag-item1>C6=3</xtag-item1></LI>
<LI><xtag-item1>CIN=3</xtag-item1></LI>
<LI><xtag-item1>C5=6</xtag-item1></LI>
<LI><xtag-item1>C6=9</xtag-item1></LI>
<LI><xtag-item1>CIN=8</xtag-item1></LI>
<LI><xtag-item1>CLK=5</xtag-item1></LI>
<LI><xtag-item1>COUT=3</xtag-item1></LI>
<LI><xtag-item1>CMUX=6</xtag-item1></LI>
<LI><xtag-item1>COUT=8</xtag-item1></LI>
<LI><xtag-item1>CQ=3</xtag-item1></LI>
<LI><xtag-item1>D4=3</xtag-item1></LI>
<LI><xtag-item1>D6=3</xtag-item1></LI>
<LI><xtag-item1>D5=5</xtag-item1></LI>
<LI><xtag-item1>D6=9</xtag-item1></LI>
<LI><xtag-item1>DMUX=6</xtag-item1></LI>
<LI><xtag-item1>DQ=3</xtag-item1></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name>
<UL>
<LI><xtag-item1>A=1</xtag-item1></LI>
<LI><xtag-item1>A2=2</xtag-item1></LI>
<LI><xtag-item1>A3=3</xtag-item1></LI>
<LI><xtag-item1>A4=5</xtag-item1></LI>
<LI><xtag-item1>A5=4</xtag-item1></LI>
<LI><xtag-item1>A6=6</xtag-item1></LI>
<LI><xtag-item1>A=2</xtag-item1></LI>
<LI><xtag-item1>A1=3</xtag-item1></LI>
<LI><xtag-item1>A2=12</xtag-item1></LI>
<LI><xtag-item1>A3=12</xtag-item1></LI>
<LI><xtag-item1>A4=14</xtag-item1></LI>
<LI><xtag-item1>A5=12</xtag-item1></LI>
<LI><xtag-item1>A6=12</xtag-item1></LI>
<LI><xtag-item1>AMUX=1</xtag-item1></LI>
<LI><xtag-item1>AQ=5</xtag-item1></LI>
<LI><xtag-item1>B1=1</xtag-item1></LI>
<LI><xtag-item1>B2=2</xtag-item1></LI>
<LI><xtag-item1>B3=4</xtag-item1></LI>
<LI><xtag-item1>B4=4</xtag-item1></LI>
<LI><xtag-item1>B5=4</xtag-item1></LI>
<LI><xtag-item1>B6=4</xtag-item1></LI>
<LI><xtag-item1>BMUX=1</xtag-item1></LI>
<LI><xtag-item1>BQ=4</xtag-item1></LI>
<LI><xtag-item1>C1=2</xtag-item1></LI>
<LI><xtag-item1>C2=3</xtag-item1></LI>
<LI><xtag-item1>C3=3</xtag-item1></LI>
<LI><xtag-item1>C4=3</xtag-item1></LI>
<LI><xtag-item1>C5=3</xtag-item1></LI>
<LI><xtag-item1>C6=3</xtag-item1></LI>
<LI><xtag-item1>CLK=5</xtag-item1></LI>
<LI><xtag-item1>CQ=3</xtag-item1></LI>
<LI><xtag-item1>D1=2</xtag-item1></LI>
<LI><xtag-item1>D2=3</xtag-item1></LI>
<LI><xtag-item1>D3=3</xtag-item1></LI>
<LI><xtag-item1>D4=3</xtag-item1></LI>
<LI><xtag-item1>D5=3</xtag-item1></LI>
<LI><xtag-item1>D6=3</xtag-item1></LI>
<LI><xtag-item1>DQ=3</xtag-item1></LI>
<LI><xtag-item1>AQ=12</xtag-item1></LI>
<LI><xtag-item1>B=5</xtag-item1></LI>
<LI><xtag-item1>B1=8</xtag-item1></LI>
<LI><xtag-item1>B2=14</xtag-item1></LI>
<LI><xtag-item1>B3=14</xtag-item1></LI>
<LI><xtag-item1>B4=14</xtag-item1></LI>
<LI><xtag-item1>B5=14</xtag-item1></LI>
<LI><xtag-item1>B6=14</xtag-item1></LI>
<LI><xtag-item1>BMUX=2</xtag-item1></LI>
<LI><xtag-item1>BQ=9</xtag-item1></LI>
<LI><xtag-item1>C=2</xtag-item1></LI>
<LI><xtag-item1>C1=5</xtag-item1></LI>
<LI><xtag-item1>C2=14</xtag-item1></LI>
<LI><xtag-item1>C3=14</xtag-item1></LI>
<LI><xtag-item1>C4=15</xtag-item1></LI>
<LI><xtag-item1>C5=15</xtag-item1></LI>
<LI><xtag-item1>C6=15</xtag-item1></LI>
<LI><xtag-item1>CE=4</xtag-item1></LI>
<LI><xtag-item1>CLK=17</xtag-item1></LI>
<LI><xtag-item1>CMUX=3</xtag-item1></LI>
<LI><xtag-item1>CQ=13</xtag-item1></LI>
<LI><xtag-item1>D=4</xtag-item1></LI>
<LI><xtag-item1>D1=3</xtag-item1></LI>
<LI><xtag-item1>D2=11</xtag-item1></LI>
<LI><xtag-item1>D3=12</xtag-item1></LI>
<LI><xtag-item1>D4=14</xtag-item1></LI>
<LI><xtag-item1>D5=16</xtag-item1></LI>
<LI><xtag-item1>D6=18</xtag-item1></LI>
<LI><xtag-item1>DMUX=2</xtag-item1></LI>
<LI><xtag-item1>DQ=14</xtag-item1></LI>
<LI><xtag-item1>SR=4</xtag-item1></LI>
</UL>
</TD>
<TD>
@@ -409,6 +448,15 @@
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx16-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
</xtag-section></UL></TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'><xtag-section name="RunStatistics"><TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=8><B>Software Quality</B></TD></TR><TR ALIGN=LEFT><TD COLSPAN=8><B>Run Statistics</B></TD></TR><TR ALIGN=CENTER BGCOLOR='#FFFF99'><TD><B>Program Name</B></TD><TD><B>Runs Started</B></TD><TD><B>Runs Finished</B></TD><TD><B>Errors</B></TD><TD><B>Fatal Errors</B></TD><TD><B>Internal Errors</B></TD><TD><B>Exceptions</B></TD><TD><B>Core Dumps</B></TD></TR>
@@ -425,8 +473,8 @@
</tr>
<tr>
<td><xtag-program-name>bitgen</xtag-program-name></td>
<td><xtag-total-run-started>24</xtag-total-run-started></td>
<td><xtag-total-run-finished>24</xtag-total-run-finished></td>
<td><xtag-total-run-started>25</xtag-total-run-started></td>
<td><xtag-total-run-finished>25</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@@ -435,8 +483,8 @@
</tr>
<tr>
<td><xtag-program-name>map</xtag-program-name></td>
<td><xtag-total-run-started>29</xtag-total-run-started></td>
<td><xtag-total-run-finished>24</xtag-total-run-finished></td>
<td><xtag-total-run-started>30</xtag-total-run-started></td>
<td><xtag-total-run-finished>25</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@@ -445,8 +493,8 @@
</tr>
<tr>
<td><xtag-program-name>ngdbuild</xtag-program-name></td>
<td><xtag-total-run-started>29</xtag-total-run-started></td>
<td><xtag-total-run-finished>29</xtag-total-run-finished></td>
<td><xtag-total-run-started>30</xtag-total-run-started></td>
<td><xtag-total-run-finished>30</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@@ -455,8 +503,8 @@
</tr>
<tr>
<td><xtag-program-name>par</xtag-program-name></td>
<td><xtag-total-run-started>24</xtag-total-run-started></td>
<td><xtag-total-run-finished>24</xtag-total-run-finished></td>
<td><xtag-total-run-started>25</xtag-total-run-started></td>
<td><xtag-total-run-finished>25</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@@ -465,8 +513,8 @@
</tr>
<tr>
<td><xtag-program-name>trce</xtag-program-name></td>
<td><xtag-total-run-started>24</xtag-total-run-started></td>
<td><xtag-total-run-finished>24</xtag-total-run-finished></td>
<td><xtag-total-run-started>25</xtag-total-run-started></td>
<td><xtag-total-run-finished>25</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@@ -475,8 +523,8 @@
</tr>
<tr>
<td><xtag-program-name>xst</xtag-program-name></td>
<td><xtag-total-run-started>56</xtag-total-run-started></td>
<td><xtag-total-run-finished>56</xtag-total-run-finished></td>
<td><xtag-total-run-started>60</xtag-total-run-started></td>
<td><xtag-total-run-finished>60</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@@ -510,7 +558,7 @@
</TR><TR><TD><xtag-design-property-name>PROP_intProjectCreationTimestamp</xtag-design-property-name>=<xtag-design-property-value>2022-06-01T11:23:26</xtag-design-property-value></TD>
<TD><xtag-design-property-name>PROP_intWbtProjectID</xtag-design-property-name>=<xtag-design-property-value>C59F24DEFAA841F7B8F7FB3A62750569</xtag-design-property-value></TD>
</TR><TR><TD><xtag-process-property-name>PROP_intWbtProjectIteration</xtag-process-property-name>=<xtag-process-property-value>1</xtag-process-property-value></TD>
</TR><TR><TD><xtag-process-property-name>PROP_intWbtProjectIteration</xtag-process-property-name>=<xtag-process-property-value>2</xtag-process-property-value></TD>
<TD><xtag-design-property-name>PROP_intWorkingDirLocWRTProjDir</xtag-design-property-name>=<xtag-design-property-value>Same</xtag-design-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_intWorkingDirUsed</xtag-design-property-name>=<xtag-design-property-value>No</xtag-design-property-value></TD>

2
webtalk.log
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@@ -4,7 +4,7 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Project Information
--------------------
ProjectID=C59F24DEFAA841F7B8F7FB3A62750569
ProjectIteration=1
ProjectIteration=2
WebTalk Summary
----------------

6
webtalk_pn.xml
View File

@@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Wed Jun 01 11:28:48 2022">
<application name="pn" timeStamp="Wed Jun 01 12:11:37 2022">
<section name="Project Information" visible="false">
<property name="ProjectID" value="C59F24DEFAA841F7B8F7FB3A62750569" type="project"/>
<property name="ProjectIteration" value="1" type="project"/>
<property name="ProjectIteration" value="2" type="project"/>
<property name="ProjectFile" value="C:/Users/Gabriel/Xilinx/Aula20220601/Aula20220601.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2022-06-01T11:23:26" type="project"/>
</section>
@@ -25,7 +25,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2022-06-01T11:23:26" type="design"/>
<property name="PROP_intWbtProjectID" value="C59F24DEFAA841F7B8F7FB3A62750569" type="design"/>
<property name="PROP_intWbtProjectIteration" value="1" type="process"/>
<property name="PROP_intWbtProjectIteration" value="2" type="process"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_AutoTop" value="true" type="design"/>

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