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LimaBR 4c7dc5090b Add Registers.vhdl
2023-02-27 13:29:58 -03:00
.gitignore
Initial commit
2023-02-07 18:59:37 -03:00
ALU_P379.vhdl
ALU working with all opcodes but load untested
2023-02-27 10:09:03 -03:00
constraints.ucf
ALU with load from data bus
2023-02-27 10:34:14 -03:00
main.vhdl
Remove examples
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README.md
Initial commit
2023-02-07 18:59:37 -03:00
Registers.vhdl
Add Registers.vhdl
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sevseg.vhdl
SevSeg with example
2023-02-07 21:53:39 -03:00
XC3S400.xise
16 registers with example
2023-02-27 13:20:48 -03:00

README.md

XC3S400

Digilent Nexys XC3S400 FPGA development board Xilinx ISE project

Description
Digilent Nexys XC3S400 FPGA development board Xilinx ISE project
Readme 126 KiB
Languages
VHDL 100%