EloDigi/Nexys
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

ALU com soma e subtração

Browse Source
This commit is contained in:
Gabriel Lima
2022-06-23 00:36:11 -03:00
parent aaa603c190
commit 9b5c128aa9
52 changed files with 646 additions and 992 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
Nexys.gise
View File

@@ -105,7 +105,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1655952458" xil_pn:in_ck="-8374071784366320205" xil_pn:name="TRANEXT_xstsynthesize_spartan3" xil_pn:prop_ck="2459494193501034712" xil_pn:start_ts="1655952448">
<transform xil_pn:end_ts="1655955268" xil_pn:in_ck="8464776891497536823" xil_pn:name="TRANEXT_xstsynthesize_spartan3" xil_pn:prop_ck="2459494193501034712" xil_pn:start_ts="1655955259">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@@ -128,7 +128,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1655952467" xil_pn:in_ck="-2514159984226061873" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="9188148234492361378" xil_pn:start_ts="1655952459">
<transform xil_pn:end_ts="1655955276" xil_pn:in_ck="-2514159984226061873" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="9188148234492361378" xil_pn:start_ts="1655955270">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
@@ -137,7 +137,7 @@
<outfile xil_pn:name="main.ngd"/>
<outfile xil_pn:name="main_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1655952472" xil_pn:in_ck="-2514159984226061872" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="6918683465102363066" xil_pn:start_ts="1655952467">
<transform xil_pn:end_ts="1655955280" xil_pn:in_ck="-2514159984226061872" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="6918683465102363066" xil_pn:start_ts="1655955276">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
@@ -150,7 +150,7 @@
<outfile xil_pn:name="main_summary.xml"/>
<outfile xil_pn:name="main_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1655952483" xil_pn:in_ck="7462214627228477673" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="8251173951899154272" xil_pn:start_ts="1655952472">
<transform xil_pn:end_ts="1655955288" xil_pn:in_ck="7462214627228477673" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="8251173951899154272" xil_pn:start_ts="1655955280">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@@ -165,7 +165,7 @@
<outfile xil_pn:name="main_pad.txt"/>
<outfile xil_pn:name="main_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1655952492" xil_pn:in_ck="4774924121320" xil_pn:name="TRANEXT_bitFile_spartan3" xil_pn:prop_ck="4026351017656627060" xil_pn:start_ts="1655952485">
<transform xil_pn:end_ts="1655955296" xil_pn:in_ck="4774924121320" xil_pn:name="TRANEXT_bitFile_spartan3" xil_pn:prop_ck="4026351017656627060" xil_pn:start_ts="1655955289">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
@@ -185,7 +185,7 @@
<outfile xil_pn:name="_impactbatch.log"/>
<outfile xil_pn:name="ise_impact.cmd"/>
</transform>
<transform xil_pn:end_ts="1655952483" xil_pn:in_ck="-2514159984226062004" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1655952479">
<transform xil_pn:end_ts="1655955288" xil_pn:in_ck="-2514159984226062004" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1655955284">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>

4
Nexys.xise
View File

@@ -28,6 +28,10 @@
</file>
<file xil_pn:name="CONTBIN_4BIT.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="58"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ULA_P379.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="59"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
</files>

67
ULA_P379.vhd Normal file
View File

@@ -0,0 +1,67 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:59:13 06/22/2022
-- Design Name:
-- Module Name: ULA_P379 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ULA_P379 is
Port ( ULA1 : in STD_LOGIC_VECTOR (3 downto 0);
ULA2 : in STD_LOGIC_VECTOR (3 downto 0);
OE : in STD_LOGIC;
OPCODE: in STD_LOGIC_VECTOR (3 downto 0);
CARRY : out STD_LOGIC;
OUTPUT : out STD_LOGIC_VECTOR (3 downto 0));
end ULA_P379;
architecture Behavioral of ULA_P379 is
signal OUTPUT_ALL: std_logic_vector (3 downto 0);
begin
process(OPCODE)
begin
case OPCODE is
when "0000" => output_all <= ULA1 + ULA2; --soma
when "0001" => output_all <= ULA1 - ULA2; --subtra<72><61>o
when others => output_all <= "ZZZZ";
end case;
end process;
process(OE)
begin
case OE is
when '1' => OUTPUT <= output_all;
when others => OUTPUT <= "ZZZZ";
end case;
end process;
end Behavioral;

2
_ngo/netlist.lst
View File

@@ -1,2 +1,2 @@
C:\Users\Gabriel\Xilinx\Nexys\main.ngc 1655952457
C:\Users\Gabriel\Xilinx\Nexys\main.ngc 1655955266
OK

11
_xmsgs/map.xmsgs
View File

@@ -5,16 +5,7 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="LIT" num="243" delta="old" >Logical network <arg fmt="%s" index="1">BUT&lt;3&gt;_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="395" delta="old" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">11</arg> more times for the following (max. 5 shown):
<arg fmt="%s" index="3">BUT&lt;2&gt;_IBUF,
BUT&lt;1&gt;_IBUF,
BUT&lt;0&gt;_IBUF,
SW&lt;7&gt;_IBUF,
SW&lt;6&gt;_IBUF</arg>
To see the details of these <arg fmt="%s" index="4">info</arg> messages, please use the -detail switch.
<msg type="info" file="LIT" num="243" delta="old" >Logical network <arg fmt="%s" index="1">CLK_IBUF</arg> has no load.
</msg>
<msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set.

45
_xmsgs/par.xmsgs
View File

@@ -8,53 +8,14 @@
<msg type="info" file="Par" num="282" delta="old" >No user timing constraints were detected or you have set the option to ignore timing constraints (&quot;par -x&quot;). Place and Route will run in &quot;Performance Evaluation Mode&quot; to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to &quot;std&quot;. For best performance, set the effort level to &quot;high&quot;.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">SW&lt;1&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">CLK_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">BUT&lt;2&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">SW&lt;2&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">BUT&lt;3&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">SW&lt;3&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">SW&lt;4&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">SW&lt;5&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">SW&lt;6&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">SW&lt;7&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">BUT&lt;0&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">SW&lt;0&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">BUT&lt;1&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Route" num="455" delta="new" >CLK Net:<arg fmt="%s" index="1">contaux&lt;24&gt;</arg> may have excessive skew because
<arg fmt="%d" index="2">3</arg> CLK pins and <arg fmt="%d" index="3">2</arg> NON_CLK pins failed to route using a CLK template.
</msg>
<msg type="info" file="Timing" num="2761" delta="old" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg>
<msg type="warning" file="ParHelpers" num="361" delta="old" >There are <arg fmt="%d" index="1">12</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
<msg type="warning" file="ParHelpers" num="361" delta="new" >There are <arg fmt="%d" index="1">1</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
</msg>
<msg type="warning" file="Par" num="283" delta="old" >There are <arg fmt="%d" index="1">12</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
<msg type="warning" file="Par" num="283" delta="new" >There are <arg fmt="%d" index="1">1</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
</msg>

2
_xmsgs/pn_parser.xmsgs
View File

@@ -8,7 +8,7 @@
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;C:/Users/Gabriel/Xilinx/Nexys/main.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;C:/Users/Gabriel/Xilinx/Nexys/ULA_P379.vhd&quot; into library work</arg>
</msg>
</messages>

39
_xmsgs/xst.xmsgs
View File

@@ -5,49 +5,30 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">BUT</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
<msg type="warning" file="Xst" num="753" delta="old" >&quot;<arg fmt="%s" index="1">C:/Users/Gabriel/Xilinx/Nexys/main.vhd</arg>&quot; line <arg fmt="%d" index="2">60</arg>: Unconnected output port &apos;<arg fmt="%s" index="3">CARRY</arg>&apos; of component &apos;<arg fmt="%s" index="4">ULA_P379</arg>&apos;.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">SW</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
<msg type="warning" file="Xst" num="819" delta="old" >&quot;<arg fmt="%s" index="1">C:/Users/Gabriel/Xilinx/Nexys/ULA_P379.vhd</arg>&quot; line <arg fmt="%d" index="2">49</arg>: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<arg fmt="%s" index="3">&lt;ULA1&gt;, &lt;ULA2&gt;</arg>
</msg>
<msg type="warning" file="Xst" num="646" delta="new" >Signal &lt;<arg fmt="%s" index="1">codigoserial</arg>&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="819" delta="new" >&quot;<arg fmt="%s" index="1">C:/Users/Gabriel/Xilinx/Nexys/ULA_P379.vhd</arg>&quot; line <arg fmt="%d" index="2">58</arg>: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<arg fmt="%s" index="3">&lt;OUTPUT_ALL&gt;</arg>
</msg>
<msg type="warning" file="Xst" num="646" delta="new" >Signal &lt;<arg fmt="%s" index="1">clk745ms</arg>&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1305" delta="old" >Output &lt;<arg fmt="%s" index="1">CARRY</arg>&gt; is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
</msg>
<msg type="warning" file="Xst" num="646" delta="new" >Signal &lt;<arg fmt="%s" index="1">clk100k</arg>&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="646" delta="old" >Signal &lt;<arg fmt="%s" index="1">clk745ms</arg>&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1780" delta="new" >Signal &lt;<arg fmt="%s" index="1">EO&lt;1&gt;</arg>&gt; is never used or assigned. This unconnected signal will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="646" delta="old" >Signal &lt;<arg fmt="%s" index="1">clk1490ms</arg>&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="646" delta="new" >Signal &lt;<arg fmt="%s" index="1">EO&lt;0&gt;</arg>&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="646" delta="old" >Signal &lt;<arg fmt="%s" index="1">clk100k</arg>&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_25</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">main</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_26</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">main</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_27</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">main</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_28</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">main</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_29</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">main</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_30</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">main</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">contaux_31</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">main</arg>&gt;.
</msg>
<msg type="info" file="Xst" num="2169" delta="new" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
<msg type="info" file="Xst" num="1767" delta="new" >HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
</msg>
</messages>

2
main.bgn
View File

@@ -5,7 +5,7 @@ C:\Xilinx\14.7\ISE_DS\ISE\.
"main" is an NCD, version 3.2, device xc3s400, package ft256, speed -4
Opened constraints file main.pcf.
Wed Jun 22 23:48:08 2022
Thu Jun 23 00:34:51 2022
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:6 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g HswapenPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g DCMShutdown:Disable -g DCIUpdateMode:AsRequired -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Match_cycle:Auto -g Security:None -g DonePipe:No -g DriveDone:No main.ncd

BIN
main.bit
View File

Binary file not shown.

4
main.bld
View File

@@ -27,10 +27,10 @@ NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Total memory usage is 153812 kilobytes
Total memory usage is 153044 kilobytes
Writing NGD file "main.ngd" ...
Total REAL time to NGDBUILD completion: 4 sec
Total REAL time to NGDBUILD completion: 3 sec
Total CPU time to NGDBUILD completion: 3 sec
Writing NGDBUILD log file "main.bld"...

17
main.cmd_log
View File

@@ -76,3 +76,20 @@ map -intstyle ise -p xc3s400-ft256-4 -cm area -ir off -pr off -c 100 -o main_map
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf constraints.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/Users/Gabriel/Xilinx/Nexys/main.xst" -ofn "C:/Users/Gabriel/Xilinx/Nexys/main.syr"
xst -intstyle ise -ifn "C:/Users/Gabriel/Xilinx/Nexys/main.xst" -ofn "C:/Users/Gabriel/Xilinx/Nexys/main.syr"
xst -intstyle ise -ifn "C:/Users/Gabriel/Xilinx/Nexys/main.xst" -ofn "C:/Users/Gabriel/Xilinx/Nexys/main.syr"
xst -intstyle ise -ifn "C:/Users/Gabriel/Xilinx/Nexys/main.xst" -ofn "C:/Users/Gabriel/Xilinx/Nexys/main.syr"
xst -intstyle ise -ifn "C:/Users/Gabriel/Xilinx/Nexys/main.xst" -ofn "C:/Users/Gabriel/Xilinx/Nexys/main.syr"
xst -intstyle ise -ifn "C:/Users/Gabriel/Xilinx/Nexys/main.xst" -ofn "C:/Users/Gabriel/Xilinx/Nexys/main.syr"
xst -intstyle ise -ifn "C:/Users/Gabriel/Xilinx/Nexys/main.xst" -ofn "C:/Users/Gabriel/Xilinx/Nexys/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc constraints.ucf -p xc3s400-ft256-4 main.ngc main.ngd
map -intstyle ise -p xc3s400-ft256-4 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf constraints.ucf
xst -intstyle ise -ifn "C:/Users/Gabriel/Xilinx/Nexys/main.xst" -ofn "C:/Users/Gabriel/Xilinx/Nexys/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc constraints.ucf -p xc3s400-ft256-4 main.ngc main.ngd
map -intstyle ise -p xc3s400-ft256-4 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf constraints.ucf
bitgen -intstyle ise -f main.ut main.ncd

2
main.drc
View File

@@ -1,7 +1,7 @@
Release 14.7 Drc P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Wed Jun 22 23:48:08 2022
Thu Jun 23 00:34:51 2022
drc -z main.ncd main.pcf

2
main.ncd
View File

File diff suppressed because one or more lines are too long

2
main.ngc
View File

File diff suppressed because one or more lines are too long

2
main.ngd
View File

File diff suppressed because one or more lines are too long

2
main.ngr
View File

File diff suppressed because one or more lines are too long

10
main.pad
View File

@@ -1,7 +1,7 @@
Release 14.7 - par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Wed Jun 22 23:47:57 2022
Thu Jun 23 00:34:44 2022
# NOTE: This file is designed to be imported into a spreadsheet program
@@ -190,9 +190,9 @@ L8|||VCCO_5|||5|||||any******||||
L9|||VCCO_4|||4|||||any******||||
L10|||VCCO_4|||4|||||any******||||
L11|||GND||||||||||||
L12|LEDS<3>|IOB|IO_L23P_3/VREF_3|OUTPUT|LVCMOS25*|3|12|SLOW|NONE**|||LOCATED|NO|NONE|
L13|LEDS<1>|IOB|IO_L21N_3|OUTPUT|LVCMOS25*|3|12|SLOW|NONE**|||LOCATED|NO|NONE|
L14|LEDS<0>|IOB|IO_L22P_3|OUTPUT|LVCMOS25*|3|12|SLOW|NONE**|||LOCATED|NO|NONE|
L12|LEDS<3>|IOB|IO_L23P_3/VREF_3|TRISTATE|LVCMOS25*|3|12|SLOW|NONE**|||LOCATED|NO|NONE|
L13|LEDS<1>|IOB|IO_L21N_3|TRISTATE|LVCMOS25*|3|12|SLOW|NONE**|||LOCATED|NO|NONE|
L14|LEDS<0>|IOB|IO_L22P_3|TRISTATE|LVCMOS25*|3|12|SLOW|NONE**|||LOCATED|NO|NONE|
L15|SW<4>|IOB|IO_L22N_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
L16|||VCCAUX||||||||2.5||||
M1||DIFFM|IO_L20P_6|UNUSED||6|||||||||
@@ -208,7 +208,7 @@ M10||DIFFS|IO_L29N_4|UNUSED||4|||||||||
M11||DIFFS|IO_L27N_4/DIN/D0|UNUSED||4|||||||||
M12|||VCCINT||||||||1.2||||
M13|LEDS<5>|IOB|IO_L21P_3|OUTPUT|LVCMOS25*|3|12|SLOW|NONE**|||LOCATED|NO|NONE|
M14|LEDS<2>|IOB|IO_L19N_3|OUTPUT|LVCMOS25*|3|12|SLOW|NONE**|||LOCATED|NO|NONE|
M14|LEDS<2>|IOB|IO_L19N_3|TRISTATE|LVCMOS25*|3|12|SLOW|NONE**|||LOCATED|NO|NONE|
M15|SW<6>|IOB|IO_L20P_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
M16|SW<5>|IOB|IO_L20N_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
N1||DIFFM|IO_L17P_6/VREF_6|UNUSED||6|||||||||

121
main.par
View File

@@ -1,7 +1,7 @@
Release 14.7 par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
GABRIEL-E5400:: Wed Jun 22 23:47:53 2022
GABRIEL-E5400:: Thu Jun 23 00:34:42 2022
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
@@ -24,11 +24,10 @@ Device speed data version: "PRODUCTION 1.39 2013-10-13".
Device Utilization Summary:
Number of BUFGMUXs 1 out of 8 12%
Number of External IOBs 21 out of 173 12%
Number of LOCed IOBs 21 out of 21 100%
Number of Slices 16 out of 3584 1%
Number of Slices 6 out of 3584 1%
Number of SLICEMs 0 out of 1792 0%
@@ -41,55 +40,42 @@ Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 1 secs
Finished initial Timing Analysis. REAL time: 1 secs
WARNING:Par:288 - The signal SW<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal BUT<2>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal SW<2>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal BUT<3>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal SW<3>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal SW<4>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal SW<5>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal SW<6>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal SW<7>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal BUT<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal SW<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal BUT<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal CLK_IBUF has no load. PAR will not attempt to route this signal.
Starting Placer
Total REAL time at the beginning of Placer: 1 secs
Total CPU time at the beginning of Placer: 1 secs
Total CPU time at the beginning of Placer: 0 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:3f5e9004) REAL time: 1 secs
Phase 1.1 Initial Placement Analysis (Checksum:d14ee789) REAL time: 1 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:3f5e9004) REAL time: 1 secs
Phase 2.7 Design Feasibility Check (Checksum:d14ee789) REAL time: 1 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:3f5e9004) REAL time: 1 secs
Phase 3.31 Local Placement Optimization (Checksum:d14ee789) REAL time: 1 secs
Phase 4.2 Initial Clock and IO Placement
Phase 4.2 Initial Clock and IO Placement (Checksum:53ea11e2) REAL time: 1 secs
Phase 4.2 Initial Clock and IO Placement (Checksum:d14ee789) REAL time: 1 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:53ea11e2) REAL time: 1 secs
Phase 5.36 Local Placement Optimization (Checksum:d14ee789) REAL time: 1 secs
Phase 6.8 Global Placement
..
..
Phase 6.8 Global Placement (Checksum:489bd2ed) REAL time: 2 secs
Phase 6.8 Global Placement (Checksum:b574629) REAL time: 1 secs
Phase 7.5 Local Placement Optimization
Phase 7.5 Local Placement Optimization (Checksum:489bd2ed) REAL time: 2 secs
Phase 7.5 Local Placement Optimization (Checksum:b574629) REAL time: 1 secs
Phase 8.18 Placement Optimization
Phase 8.18 Placement Optimization (Checksum:66a511b6) REAL time: 2 secs
Phase 8.18 Placement Optimization (Checksum:c5b2b89) REAL time: 1 secs
Phase 9.5 Local Placement Optimization
Phase 9.5 Local Placement Optimization (Checksum:66a511b6) REAL time: 2 secs
Phase 9.5 Local Placement Optimization (Checksum:c5b2b89) REAL time: 1 secs
Total REAL time to Placer completion: 2 secs
Total CPU time to Placer completion: 2 secs
Total REAL time to Placer completion: 1 secs
Total CPU time to Placer completion: 1 secs
Writing design to file main.ncd
@@ -97,32 +83,26 @@ Writing design to file main.ncd
Starting Router
Phase 1 : 79 unrouted; REAL time: 3 secs
Phase 1 : 50 unrouted; REAL time: 1 secs
Phase 2 : 64 unrouted; REAL time: 3 secs
Phase 2 : 50 unrouted; REAL time: 1 secs
Phase 3 : 1 unrouted; REAL time: 3 secs
Phase 3 : 4 unrouted; REAL time: 1 secs
Phase 4 : 3 unrouted; (Par is working to improve performance) REAL time: 3 secs
Phase 4 : 4 unrouted; (Par is working to improve performance) REAL time: 1 secs
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 1 secs
Updating file: main.ncd with current fully routed design.
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 1 secs
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 1 secs
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 1 secs
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
WARNING:Route:455 - CLK Net:contaux<24> may have excessive skew because
3 CLK pins and 2 NON_CLK pins failed to route using a CLK template.
Total REAL time to Router completion: 3 secs
Total CPU time to Router completion: 3 secs
Total REAL time to Router completion: 1 secs
Total CPU time to Router completion: 1 secs
Partition Implementation Status
-------------------------------
@@ -133,67 +113,26 @@ Partition Implementation Status
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| CLK_BUFGP | BUFGMUX6| No | 13 | 0.001 | 1.015 |
+---------------------+--------------+------+------+------------+-------------+
| contaux<24> | Local| | 5 | 0.763 | 1.860 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0)
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net CLK | SETUP | N/A| 4.645ns| N/A| 0
_BUFGP | HOLD | 1.311ns| | 0| 0
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net con | SETUP | N/A| 2.642ns| N/A| 0
taux<24> | HOLD | 0.097ns| | 0| 0
----------------------------------------------------------------------------------------------------------
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 12 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 4 secs
Total CPU time to PAR completion: 3 secs
Total REAL time to PAR completion: 2 secs
Total CPU time to PAR completion: 2 secs
Peak Memory Usage: 248 MB
Peak Memory Usage: 244 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 15
Number of warning messages: 3
Number of info messages: 1
Writing design to file main.ncd

3
main.pcf
View File

@@ -1,5 +1,5 @@
//! **************************************************************************
// Written by: Map P.20131013 on Wed Jun 22 23:47:50 2022
// Written by: Map P.20131013 on Thu Jun 23 00:34:39 2022
//! **************************************************************************
SCHEMATIC START;
@@ -24,6 +24,5 @@ COMP "CLK" LOCATE = SITE "A8" LEVEL 1;
COMP "BUT<0>" LOCATE = SITE "J13" LEVEL 1;
COMP "SW<0>" LOCATE = SITE "N15" LEVEL 1;
COMP "BUT<1>" LOCATE = SITE "K14" LEVEL 1;
NET "CLK_BUFGP/IBUFG" BEL "CLK_BUFGP/BUFG.GCLKMUX" USELOCALCONNECT;
SCHEMATIC END;

2
main.prj
View File

@@ -1,2 +1,2 @@
vhdl work "CONTBIN_4BIT.vhd"
vhdl work "ULA_P379.vhd"
vhdl work "main.vhd"

2
main.ptwx
View File

@@ -329,4 +329,4 @@
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net CLK_BUFGP</twConstName><twConstData type="SETUP" best="4.645" units="ns" score="0"/><twConstData type="HOLD" slack="1.311" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net contaux&lt;24&gt;</twConstName><twConstData type="SETUP" best="2.642" units="ns" score="0"/><twConstData type="HOLD" slack="0.097" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="8">0</twUnmetConstCnt><twInfo anchorID="9">INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</twInfo></twSumRpt></twBody></twReport>
<twReport><twBody><twSumRpt></twSumRpt></twBody></twReport>

237
main.syr
View File

@@ -104,28 +104,33 @@ Slice Utilization Ratio Delta : 5
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/Users/Gabriel/Xilinx/Nexys/CONTBIN_4BIT.vhd" in Library work.
Architecture behavioral of Entity contbin_4bit is up to date.
Compiling vhdl file "C:/Users/Gabriel/Xilinx/Nexys/ULA_P379.vhd" in Library work.
Entity <ula_p379> compiled.
Entity <ula_p379> (Architecture <behavioral>) compiled.
Compiling vhdl file "C:/Users/Gabriel/Xilinx/Nexys/main.vhd" in Library work.
Entity <main> compiled.
Entity <main> (Architecture <behavioral>) compiled.
Architecture behavioral of Entity main is up to date.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <main> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <CONTBIN_4BIT> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <ULA_P379> in library <work> (architecture <behavioral>).
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <main> in library <work> (Architecture <behavioral>).
WARNING:Xst:753 - "C:/Users/Gabriel/Xilinx/Nexys/main.vhd" line 60: Unconnected output port 'CARRY' of component 'ULA_P379'.
Entity <main> analyzed. Unit <main> generated.
Analyzing Entity <CONTBIN_4BIT> in library <work> (Architecture <behavioral>).
Entity <CONTBIN_4BIT> analyzed. Unit <CONTBIN_4BIT> generated.
Analyzing Entity <ULA_P379> in library <work> (Architecture <behavioral>).
WARNING:Xst:819 - "C:/Users/Gabriel/Xilinx/Nexys/ULA_P379.vhd" line 49: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<ULA1>, <ULA2>
WARNING:Xst:819 - "C:/Users/Gabriel/Xilinx/Nexys/ULA_P379.vhd" line 58: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<OUTPUT_ALL>
Entity <ULA_P379> analyzed. Unit <ULA_P379> generated.
=========================================================================
@@ -134,42 +139,43 @@ Entity <CONTBIN_4BIT> analyzed. Unit <CONTBIN_4BIT> generated.
Performing bidirectional port resolution...
Synthesizing Unit <CONTBIN_4BIT>.
Related source file is "C:/Users/Gabriel/Xilinx/Nexys/CONTBIN_4BIT.vhd".
Found 4-bit up counter for signal <cont>.
Synthesizing Unit <ULA_P379>.
Related source file is "C:/Users/Gabriel/Xilinx/Nexys/ULA_P379.vhd".
WARNING:Xst:1305 - Output <CARRY> is never assigned. Tied to value 0.
Found 4-bit tristate buffer for signal <OUTPUT_ALL>.
Found 4-bit addsub for signal <OUTPUT_ALL$share0000>.
Summary:
inferred 1 Counter(s).
Unit <CONTBIN_4BIT> synthesized.
inferred 1 Adder/Subtractor(s).
inferred 4 Tristate(s).
Unit <ULA_P379> synthesized.
Synthesizing Unit <main>.
Related source file is "C:/Users/Gabriel/Xilinx/Nexys/main.vhd".
WARNING:Xst:647 - Input <BUT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <SW> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <codigoserial> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <clk745ms> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <clk1490ms> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <clk100k> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <EO<1>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <EO<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Found 2-bit tristate buffer for signal <LEDS<1:0>>.
Found 4-bit tristate buffer for signal <LEDS<3:0>>.
Found 16-bit down counter for signal <cont100k>.
Found 32-bit up counter for signal <contaux>.
Summary:
inferred 2 Counter(s).
inferred 2 Tristate(s).
inferred 4 Tristate(s).
Unit <main> synthesized.
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Counters : 3
# Adders/Subtractors : 1
4-bit addsub : 1
# Counters : 1
16-bit down counter : 1
32-bit up counter : 1
4-bit up counter : 1
# Tristates : 2
1-bit tristate buffer : 2
# Tristates : 5
1-bit tristate buffer : 4
4-bit tristate buffer : 1
=========================================================================
@@ -182,22 +188,14 @@ Macro Statistics
Advanced HDL Synthesis Report
Macro Statistics
# Counters : 2
32-bit up counter : 1
4-bit up counter : 1
# Adders/Subtractors : 1
4-bit addsub : 1
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
WARNING:Xst:2677 - Node <contaux_25> of sequential type is unconnected in block <main>.
WARNING:Xst:2677 - Node <contaux_26> of sequential type is unconnected in block <main>.
WARNING:Xst:2677 - Node <contaux_27> of sequential type is unconnected in block <main>.
WARNING:Xst:2677 - Node <contaux_28> of sequential type is unconnected in block <main>.
WARNING:Xst:2677 - Node <contaux_29> of sequential type is unconnected in block <main>.
WARNING:Xst:2677 - Node <contaux_30> of sequential type is unconnected in block <main>.
WARNING:Xst:2677 - Node <contaux_31> of sequential type is unconnected in block <main>.
Optimizing unit <main> ...
@@ -210,10 +208,7 @@ Final Macro Processing ...
=========================================================================
Final Register Report
Macro Statistics
# Registers : 29
Flip-Flops : 29
Found no macro
=========================================================================
=========================================================================
@@ -241,23 +236,16 @@ Design Statistics
# IOs : 21
Cell Usage :
# BELS : 80
# BELS : 13
# GND : 1
# INV : 1
# LUT1 : 24
# LUT2 : 1
# LUT3 : 1
# LUT4 : 2
# MUXCY : 24
# VCC : 1
# XORCY : 25
# FlipFlops/Latches : 29
# FD : 28
# FDR : 1
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 8
# OBUF : 8
# LUT3 : 2
# LUT4 : 7
# MUXF5 : 2
# IO Buffers : 20
# IBUF : 12
# OBUF : 4
# OBUFT : 4
=========================================================================
Device utilization summary:
@@ -265,12 +253,10 @@ Device utilization summary:
Selected Device : 3s400ft256-4
Number of Slices: 16 out of 3584 0%
Number of Slice Flip Flops: 29 out of 7168 0%
Number of 4 input LUTs: 29 out of 7168 0%
Number of Slices: 5 out of 3584 0%
Number of 4 input LUTs: 10 out of 7168 0%
Number of IOs: 21
Number of bonded IOBs: 9 out of 173 5%
Number of GCLKs: 1 out of 8 12%
Number of bonded IOBs: 20 out of 173 11%
---------------------------
Partition Resource Summary:
@@ -290,13 +276,7 @@ NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
CLK | BUFGP | 25 |
contaux_24 | NONE(CLOS0/cont_1) | 4 |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
@@ -306,133 +286,48 @@ Timing Summary:
---------------
Speed Grade: -4
Minimum period: 5.426ns (Maximum Frequency: 184.298MHz)
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: 8.932ns
Maximum combinational path delay: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 13.538ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'CLK'
Clock period: 5.426ns (frequency: 184.298MHz)
Total number of paths / destination ports: 325 / 25
Timing constraint: Default path analysis
Total number of paths / destination ports: 64 / 4
-------------------------------------------------------------------------
Delay: 5.426ns (Levels of Logic = 25)
Source: contaux_1 (FF)
Destination: contaux_24 (FF)
Source Clock: CLK rising
Destination Clock: CLK rising
Delay: 13.538ns (Levels of Logic = 6)
Source: BUT<0> (PAD)
Destination: LEDS<3> (PAD)
Data Path: contaux_1 to contaux_24
Data Path: BUT<0> to LEDS<3>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 1 0.720 1.140 contaux_1 (contaux_1)
LUT1:I0->O 1 0.551 0.000 Mcount_contaux_cy<1>_rt (Mcount_contaux_cy<1>_rt)
MUXCY:S->O 1 0.500 0.000 Mcount_contaux_cy<1> (Mcount_contaux_cy<1>)
MUXCY:CI->O 1 0.064 0.000 Mcount_contaux_cy<2> (Mcount_contaux_cy<2>)
MUXCY:CI->O 1 0.064 0.000 Mcount_contaux_cy<3> (Mcount_contaux_cy<3>)
MUXCY:CI->O 1 0.064 0.000 Mcount_contaux_cy<4> (Mcount_contaux_cy<4>)
MUXCY:CI->O 1 0.064 0.000 Mcount_contaux_cy<5> (Mcount_contaux_cy<5>)
MUXCY:CI->O 1 0.064 0.000 Mcount_contaux_cy<6> (Mcount_contaux_cy<6>)
MUXCY:CI->O 1 0.064 0.000 Mcount_contaux_cy<7> (Mcount_contaux_cy<7>)
MUXCY:CI->O 1 0.064 0.000 Mcount_contaux_cy<8> (Mcount_contaux_cy<8>)
MUXCY:CI->O 1 0.064 0.000 Mcount_contaux_cy<9> (Mcount_contaux_cy<9>)
MUXCY:CI->O 1 0.064 0.000 Mcount_contaux_cy<10> (Mcount_contaux_cy<10>)
MUXCY:CI->O 1 0.064 0.000 Mcount_contaux_cy<11> (Mcount_contaux_cy<11>)
MUXCY:CI->O 1 0.064 0.000 Mcount_contaux_cy<12> (Mcount_contaux_cy<12>)
MUXCY:CI->O 1 0.064 0.000 Mcount_contaux_cy<13> (Mcount_contaux_cy<13>)
MUXCY:CI->O 1 0.064 0.000 Mcount_contaux_cy<14> (Mcount_contaux_cy<14>)
MUXCY:CI->O 1 0.064 0.000 Mcount_contaux_cy<15> (Mcount_contaux_cy<15>)
MUXCY:CI->O 1 0.064 0.000 Mcount_contaux_cy<16> (Mcount_contaux_cy<16>)
MUXCY:CI->O 1 0.064 0.000 Mcount_contaux_cy<17> (Mcount_contaux_cy<17>)
MUXCY:CI->O 1 0.064 0.000 Mcount_contaux_cy<18> (Mcount_contaux_cy<18>)
MUXCY:CI->O 1 0.064 0.000 Mcount_contaux_cy<19> (Mcount_contaux_cy<19>)
MUXCY:CI->O 1 0.064 0.000 Mcount_contaux_cy<20> (Mcount_contaux_cy<20>)
MUXCY:CI->O 1 0.064 0.000 Mcount_contaux_cy<21> (Mcount_contaux_cy<21>)
MUXCY:CI->O 1 0.064 0.000 Mcount_contaux_cy<22> (Mcount_contaux_cy<22>)
MUXCY:CI->O 0 0.064 0.000 Mcount_contaux_cy<23> (Mcount_contaux_cy<23>)
XORCY:CI->O 1 0.904 0.000 Mcount_contaux_xor<24> (Result<24>)
FD:D 0.203 contaux_24
IBUF:I->O 1 0.821 1.140 BUT_0_IBUF (BUT_0_IBUF)
LUT4:I0->O 4 0.551 0.917 ULA0/OUTPUT_ALL_cmp_eq00001 (ULA0/OUTPUT_ALL_cmp_eq0000)
MUXF5:S->O 2 0.621 1.072 ULA0/Maddsub_OUTPUT_ALL_share0000_cy<1>1_f5 (ULA0/Maddsub_OUTPUT_ALL_share0000_cy<1>)
LUT4:I1->O 1 0.551 0.869 ULA0/Maddsub_OUTPUT_ALL_share0000_xor<3>11_SW0 (N2)
LUT3:I2->O 1 0.551 0.801 ULA0/Maddsub_OUTPUT_ALL_share0000_xor<3>11 (LEDS_3_OBUFT)
OBUFT:I->O 5.644 LEDS_3_OBUFT (LEDS<3>)
----------------------------------------
Total 5.426ns (4.286ns logic, 1.140ns route)
(79.0% logic, 21.0% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'contaux_24'
Clock period: 2.734ns (frequency: 365.764MHz)
Total number of paths / destination ports: 10 / 4
-------------------------------------------------------------------------
Delay: 2.734ns (Levels of Logic = 1)
Source: CLOS0/cont_0 (FF)
Destination: CLOS0/cont_2 (FF)
Source Clock: contaux_24 rising
Destination Clock: contaux_24 rising
Data Path: CLOS0/cont_0 to CLOS0/cont_2
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDR:C->Q 5 0.720 1.260 CLOS0/cont_0 (CLOS0/cont_0)
LUT3:I0->O 1 0.551 0.000 CLOS0/Mcount_cont_xor<2>11 (Result<2>1)
FD:D 0.203 CLOS0/cont_2
----------------------------------------
Total 2.734ns (1.474ns logic, 1.260ns route)
(53.9% logic, 46.1% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 7.367ns (Levels of Logic = 1)
Source: contaux_24 (FF)
Destination: LEDS<1> (PAD)
Source Clock: CLK rising
Data Path: contaux_24 to LEDS<1>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 6 0.720 1.003 contaux_24 (contaux_24)
OBUF:I->O 5.644 LEDS_1_OBUF (LEDS<1>)
----------------------------------------
Total 7.367ns (6.364ns logic, 1.003ns route)
(86.4% logic, 13.6% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'contaux_24'
Total number of paths / destination ports: 4 / 1
-------------------------------------------------------------------------
Offset: 8.932ns (Levels of Logic = 2)
Source: CLOS0/cont_3 (FF)
Destination: LEDS<0> (PAD)
Source Clock: contaux_24 rising
Data Path: CLOS0/cont_3 to LEDS<0>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 2 0.720 1.216 CLOS0/cont_3 (CLOS0/cont_3)
LUT4:I0->O 1 0.551 0.801 LEDS_0_mux00001 (LEDS_0_OBUF)
OBUF:I->O 5.644 LEDS_0_OBUF (LEDS<0>)
----------------------------------------
Total 8.932ns (6.915ns logic, 2.017ns route)
(77.4% logic, 22.6% route)
Total 13.538ns (8.739ns logic, 4.799ns route)
(64.6% logic, 35.4% route)
=========================================================================
Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 6.86 secs
Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 5.27 secs
-->
Total memory usage is 257880 kilobytes
Total memory usage is 258520 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 14 ( 0 filtered)
Number of warnings : 7 ( 0 filtered)
Number of infos : 1 ( 0 filtered)

59
main.twr
View File

@@ -40,31 +40,56 @@ Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock CLK to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
LEDS<1> | 10.564(R)|CLK_BUFGP | 0.000|
------------+------------+------------------+--------+
Clock to Setup on destination clock CLK
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK | 4.645| | | |
---------------+---------+---------+---------+---------+
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
BUT<0> |LEDS<1> | 10.331|
BUT<0> |LEDS<2> | 11.511|
BUT<0> |LEDS<3> | 11.195|
BUT<1> |LEDS<0> | 7.852|
BUT<1> |LEDS<1> | 9.650|
BUT<1> |LEDS<2> | 10.830|
BUT<1> |LEDS<3> | 10.514|
BUT<2> |LEDS<0> | 8.073|
BUT<2> |LEDS<1> | 9.534|
BUT<2> |LEDS<2> | 10.714|
BUT<2> |LEDS<3> | 10.398|
BUT<3> |LEDS<0> | 8.097|
BUT<3> |LEDS<1> | 9.582|
BUT<3> |LEDS<2> | 10.762|
BUT<3> |LEDS<3> | 10.446|
SW<0> |LEDS<0> | 8.612|
SW<0> |LEDS<1> | 9.383|
SW<0> |LEDS<2> | 10.563|
SW<0> |LEDS<3> | 10.247|
SW<1> |LEDS<1> | 9.811|
SW<1> |LEDS<2> | 10.991|
SW<1> |LEDS<3> | 10.675|
SW<2> |LEDS<2> | 9.360|
SW<2> |LEDS<3> | 9.243|
SW<3> |LEDS<3> | 8.522|
SW<4> |LEDS<0> | 7.926|
SW<4> |LEDS<1> | 8.721|
SW<4> |LEDS<2> | 9.901|
SW<4> |LEDS<3> | 9.585|
SW<5> |LEDS<1> | 9.215|
SW<5> |LEDS<2> | 10.395|
SW<5> |LEDS<3> | 10.079|
SW<6> |LEDS<2> | 8.829|
SW<6> |LEDS<3> | 8.633|
SW<7> |LEDS<3> | 8.581|
---------------+---------------+---------+
Analysis completed Wed Jun 22 23:48:01 2022
Analysis completed Thu Jun 23 00:34:46 2022
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 144 MB
Peak Memory Usage: 142 MB

4
main.twx
View File

File diff suppressed because one or more lines are too long

17
main.unroutes
View File

@@ -1,24 +1,13 @@
Release 14.7 - par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Wed Jun 22 23:47:57 2022
Thu Jun 23 00:34:44 2022
All signals are completely routed.
WARNING:ParHelpers:361 - There are 12 loadless signals in this design. This design will cause Bitgen to issue DRC
WARNING:ParHelpers:361 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC
warnings.
BUT<0>_IBUF
BUT<1>_IBUF
BUT<2>_IBUF
BUT<3>_IBUF
SW<0>_IBUF
SW<1>_IBUF
SW<2>_IBUF
SW<3>_IBUF
SW<4>_IBUF
SW<5>_IBUF
SW<6>_IBUF
SW<7>_IBUF
CLK_IBUF

45
main.vhd
View File

@@ -21,7 +21,6 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
@@ -46,50 +45,24 @@ signal cont100k: std_logic_vector (15 downto 0);
signal clk100k: std_logic;
signal contaux: std_logic_vector (31 downto 0);
signal clk745ms, clk1490ms: std_logic;
signal EO: std_logic_vector (1 downto 0);
signal codigoserial: std_logic_vector (7 downto 0);
signal bitatual: std_logic_vector (3 downto 0);
component CONTBCD_C port( CLK, CLR, UP, EN: in std_logic;
ENOUT: out std_logic;
Q: out std_logic_vector(3 downto 0)
);
end component;
component CONTBIN_4BIT port( CLK, CLR, UP, EN: in std_logic;
ENOUT: out std_logic;
Q: out std_logic_vector(3 downto 0)
);
component ULA_P379
Port ( ULA1 : in STD_LOGIC_VECTOR (3 downto 0);
ULA2 : in STD_LOGIC_VECTOR (3 downto 0);
OE : in STD_LOGIC;
OPCODE: in STD_LOGIC_VECTOR (3 downto 0);
CARRY : out STD_LOGIC;
OUTPUT : out STD_LOGIC_VECTOR (3 downto 0));
end component;
begin
CLOS0: CONTBIN_4BIT port map (CLK=>clk1490ms, CLR=>'0', UP=>'1', EN=>'1', ENOUT=>EO(0), Q=>bitatual(3 downto 0));
ULA0: ULA_P379 port map (ULA1=>SW(7 downto 4), ULA2=>SW(3 downto 0), OE=>'1', OPCODE=>BUT, OUTPUT=>LEDS(3 downto 0));
LEDS <= "LLLLLLZZ";
LEDS <= "LLLLZZZZ";
CLK100k <= cont100k(7);
clk745ms <= contaux(23);
clk1490ms <= contaux(24);
LEDS(1) <= clk1490ms;
codigoserial <= "10110101";
process (bitatual)
begin
--LEDS(0) <= codigoserial(to_integer(unsigned(bitatual)));
case bitatual is
when "0000" => LEDS(0) <= codigoserial(0);
when "0001" => LEDS(0) <= codigoserial(1);
when "0010" => LEDS(0) <= codigoserial(2);
when "0011" => LEDS(0) <= codigoserial(3);
when "0100" => LEDS(0) <= codigoserial(4);
when "0101" => LEDS(0) <= codigoserial(5);
when "0110" => LEDS(0) <= codigoserial(6);
when "0111" => LEDS(0) <= codigoserial(7);
when others => LEDS(0) <= '0';
end case;
end process;
process (CLK)
begin

2
main_guide.ncd
View File

File diff suppressed because one or more lines are too long

22
main_map.map
View File

@@ -9,7 +9,7 @@ Target Device : xc3s400
Target Package : ft256
Target Speed : -4
Mapper Version : spartan3 -- $Revision: 1.55 $
Mapped Date : Wed Jun 22 23:47:48 2022
Mapped Date : Thu Jun 23 00:34:38 2022
Mapping design into LUTs...
Running directed packing...
@@ -24,24 +24,16 @@ Design Summary:
Number of errors: 0
Number of warnings: 0
Logic Utilization:
Number of Slice Flip Flops: 29 out of 7,168 1%
Number of 4 input LUTs: 5 out of 7,168 1%
Number of 4 input LUTs: 10 out of 7,168 1%
Logic Distribution:
Number of occupied Slices: 16 out of 3,584 1%
Number of Slices containing only related logic: 16 out of 16 100%
Number of Slices containing unrelated logic: 0 out of 16 0%
Number of occupied Slices: 6 out of 3,584 1%
Number of Slices containing only related logic: 6 out of 6 100%
Number of Slices containing unrelated logic: 0 out of 6 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 29 out of 7,168 1%
Number used as logic: 5
Number used as a route-thru: 24
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
Total Number of 4 input LUTs: 10 out of 7,168 1%
Number of bonded IOBs: 21 out of 173 12%
Number of BUFGMUXs: 1 out of 8 12%
Average Fanout of Non-Clock Nets: 0.96
Average Fanout of Non-Clock Nets: 2.19
Peak Memory Usage: 237 MB
Total REAL time to MAP completion: 1 secs

38
main_map.mrp
View File

@@ -9,31 +9,23 @@ Target Device : xc3s400
Target Package : ft256
Target Speed : -4
Mapper Version : spartan3 -- $Revision: 1.55 $
Mapped Date : Wed Jun 22 23:47:48 2022
Mapped Date : Thu Jun 23 00:34:38 2022
Design Summary
--------------
Number of errors: 0
Number of warnings: 0
Logic Utilization:
Number of Slice Flip Flops: 29 out of 7,168 1%
Number of 4 input LUTs: 5 out of 7,168 1%
Number of 4 input LUTs: 10 out of 7,168 1%
Logic Distribution:
Number of occupied Slices: 16 out of 3,584 1%
Number of Slices containing only related logic: 16 out of 16 100%
Number of Slices containing unrelated logic: 0 out of 16 0%
Number of occupied Slices: 6 out of 3,584 1%
Number of Slices containing only related logic: 6 out of 6 100%
Number of Slices containing unrelated logic: 0 out of 6 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 29 out of 7,168 1%
Number used as logic: 5
Number used as a route-thru: 24
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
Total Number of 4 input LUTs: 10 out of 7,168 1%
Number of bonded IOBs: 21 out of 173 12%
Number of BUFGMUXs: 1 out of 8 12%
Average Fanout of Non-Clock Nets: 0.96
Average Fanout of Non-Clock Nets: 2.19
Peak Memory Usage: 237 MB
Total REAL time to MAP completion: 1 secs
@@ -81,15 +73,7 @@ Section 2 - Warnings
Section 3 - Informational
-------------------------
INFO:LIT:243 - Logical network BUT<3>_IBUF has no load.
INFO:LIT:395 - The above info message is repeated 11 more times for the
following (max. 5 shown):
BUT<2>_IBUF,
BUT<1>_IBUF,
BUT<0>_IBUF,
SW<7>_IBUF,
SW<6>_IBUF
To see the details of these info messages, please use the -detail switch.
INFO:LIT:243 - Logical network CLK_IBUF has no load.
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
@@ -97,7 +81,7 @@ INFO:LIT:244 - All of the single ended outputs in this design are using slew
Section 4 - Removed Logic Summary
---------------------------------
2 block(s) optimized away
1 block(s) optimized away
Section 5 - Removed Logic
-------------------------
@@ -105,10 +89,6 @@ Section 5 - Removed Logic
Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 6 - IOB Properties
--------------------------

2
main_map.ncd
View File

File diff suppressed because one or more lines are too long

2
main_map.ngm
View File

File diff suppressed because one or more lines are too long

19
main_map.xrpt
View File

@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Map" timeStamp="Wed Jun 22 23:47:50 2022">
<application stringID="Map" timeStamp="Thu Jun 23 00:34:39 2022">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@@ -74,11 +74,8 @@
<item stringID="MAP_TOTAL_CPU_TIME" value="1 secs "/>
</section>
<section stringID="MAP_SLICE_REPORTING">
<item AVAILABLE="7168" dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="29"/>
<item AVAILABLE="7168" dataType="int" label="Number of 4 input LUTs" stringID="MAP_NUM_4_INPUT_LUT" value="29">
<item dataType="int" label="Number of route-thrus" stringID="MAP_NUM_LUT_RT" value="24"/>
</item>
<item AVAILABLE="3584" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="16">
<item AVAILABLE="7168" dataType="int" label="Number of 4 input LUTs" stringID="MAP_NUM_4_INPUT_LUT" value="10"/>
<item AVAILABLE="3584" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="6">
<item dataType="int" label="Number of Slices containing unrelated logic" stringID="MAP_NUM_SLICE_UNRELATED" value="0"/>
</item>
</section>
@@ -96,9 +93,7 @@
<item AVAILABLE="120" dataType="int" stringID="MAP_NUM_DIFFS" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_DIFFS" value="0"/>
</section>
<section stringID="MAP_HARD_IP_REPORTING">
<item AVAILABLE="8" dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="1"/>
</section>
<section stringID="MAP_HARD_IP_REPORTING"/>
<section stringID="MAP_MACRO_RPM_REPORTING">
<item dataType="int" stringID="MAP_HARD_MACROS" value="0"/>
<item dataType="int" stringID="MAP_RPMS" value="0"/>
@@ -261,16 +256,14 @@
</section>
<section stringID="MAP_RPM_MACROS">
<section stringID="MAP_SHAPE_SECTION">
<item dataType="int" stringID="MAP_NUM_SHAPE" value="1"/>
<item dataType="int" stringID="MAP_NUM_SHAPE" value="0"/>
</section>
</section>
<section stringID="MAP_GUIDE_REPORT"/>
<section stringID="MAP_AREA_GROUPS_PARTITIONS"/>
<section stringID="MAP_TIMING_REPORT"/>
<section stringID="MAP_CONFIGURATION_STRING_DETAILS"/>
<section stringID="MAP_GENERAL_CONFIG_DATA">
<item stringID="MAP_DISABLE_ATTR" value="LOW"/>
</section>
<section stringID="MAP_GENERAL_CONFIG_DATA"/>
<section stringID="MAP_CONTROL_SET_INFORMATION"/>
</task>
</application>

44
main_ngdbuild.xrpt
View File

@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Wed Jun 22 23:47:45 2022">
<application stringID="NgdBuild" timeStamp="Thu Jun 23 00:34:35 2022">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@@ -66,36 +66,24 @@
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
</section>
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_BUFGP" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="28"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="24"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="24"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="8"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="25"/>
</section>
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="28"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="12"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="24"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="24"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="8"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="25"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="7"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF5" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="4"/>
</section>
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="13"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="7"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF5" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="4"/>
</section>
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
<section stringID="NGDBUILD_CORE_INSTANCES"/>

10
main_pad.csv
View File

@@ -1,7 +1,7 @@
#Release 14.7 - par P.20131013 (nt64)
#Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
#Wed Jun 22 23:47:57 2022
#Thu Jun 23 00:34:44 2022
#
## NOTE: This file is designed to be imported into a spreadsheet program
@@ -190,9 +190,9 @@ L8,,,VCCO_5,,,5,,,,,any******,,,,
L9,,,VCCO_4,,,4,,,,,any******,,,,
L10,,,VCCO_4,,,4,,,,,any******,,,,
L11,,,GND,,,,,,,,,,,,
L12,LEDS<3>,IOB,IO_L23P_3/VREF_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,LOCATED,NO,NONE,
L13,LEDS<1>,IOB,IO_L21N_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,LOCATED,NO,NONE,
L14,LEDS<0>,IOB,IO_L22P_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,LOCATED,NO,NONE,
L12,LEDS<3>,IOB,IO_L23P_3/VREF_3,TRISTATE,LVCMOS25*,3,12,SLOW,NONE**,,,LOCATED,NO,NONE,
L13,LEDS<1>,IOB,IO_L21N_3,TRISTATE,LVCMOS25*,3,12,SLOW,NONE**,,,LOCATED,NO,NONE,
L14,LEDS<0>,IOB,IO_L22P_3,TRISTATE,LVCMOS25*,3,12,SLOW,NONE**,,,LOCATED,NO,NONE,
L15,SW<4>,IOB,IO_L22N_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
L16,,,VCCAUX,,,,,,,,2.5,,,,
M1,,DIFFM,IO_L20P_6,UNUSED,,6,,,,,,,,,
@@ -208,7 +208,7 @@ M10,,DIFFS,IO_L29N_4,UNUSED,,4,,,,,,,,,
M11,,DIFFS,IO_L27N_4/DIN/D0,UNUSED,,4,,,,,,,,,
M12,,,VCCINT,,,,,,,,1.2,,,,
M13,LEDS<5>,IOB,IO_L21P_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,LOCATED,NO,NONE,
M14,LEDS<2>,IOB,IO_L19N_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,LOCATED,NO,NONE,
M14,LEDS<2>,IOB,IO_L19N_3,TRISTATE,LVCMOS25*,3,12,SLOW,NONE**,,,LOCATED,NO,NONE,
M15,SW<6>,IOB,IO_L20P_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
M16,SW<5>,IOB,IO_L20N_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
N1,,DIFFM,IO_L17P_6/VREF_6,UNUSED,,6,,,,,,,,,
1 #Release 14.7 - par P.20131013 (nt64)
2 #Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
3 #Wed Jun 22 23:47:57 2022 #Thu Jun 23 00:34:44 2022
4 #
5 ## NOTE: This file is designed to be imported into a spreadsheet program
6 # such as Microsoft Excel for viewing, printing and sorting. The |
7 # character is used as the data field separator. This file is also designed
190 L11,,,GND,,,,,,,,,,,,
191 L12,LEDS<3>,IOB,IO_L23P_3/VREF_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,LOCATED,NO,NONE, L12,LEDS<3>,IOB,IO_L23P_3/VREF_3,TRISTATE,LVCMOS25*,3,12,SLOW,NONE**,,,LOCATED,NO,NONE,
192 L13,LEDS<1>,IOB,IO_L21N_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,LOCATED,NO,NONE, L13,LEDS<1>,IOB,IO_L21N_3,TRISTATE,LVCMOS25*,3,12,SLOW,NONE**,,,LOCATED,NO,NONE,
193 L14,LEDS<0>,IOB,IO_L22P_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,LOCATED,NO,NONE, L14,LEDS<0>,IOB,IO_L22P_3,TRISTATE,LVCMOS25*,3,12,SLOW,NONE**,,,LOCATED,NO,NONE,
194 L15,SW<4>,IOB,IO_L22N_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
195 L16,,,VCCAUX,,,,,,,,2.5,,,,
196 M1,,DIFFM,IO_L20P_6,UNUSED,,6,,,,,,,,,
197 M2,,DIFFS,IO_L20N_6,UNUSED,,6,,,,,,,,,
198 M3,,DIFFM,IO_L19P_6,UNUSED,,6,,,,,,,,,
208 M13,LEDS<5>,IOB,IO_L21P_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,LOCATED,NO,NONE,
209 M14,LEDS<2>,IOB,IO_L19N_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,LOCATED,NO,NONE, M14,LEDS<2>,IOB,IO_L19N_3,TRISTATE,LVCMOS25*,3,12,SLOW,NONE**,,,LOCATED,NO,NONE,
210 M15,SW<6>,IOB,IO_L20P_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
211 M16,SW<5>,IOB,IO_L20N_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
212 N1,,DIFFM,IO_L17P_6/VREF_6,UNUSED,,6,,,,,,,,,
213 N2,,DIFFS,IO_L17N_6,UNUSED,,6,,,,,,,,,
214 N3,,DIFFM,IO_L16P_6,UNUSED,,6,,,,,,,,,

10
main_pad.txt
View File

@@ -1,7 +1,7 @@
Release 14.7 - par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Wed Jun 22 23:47:57 2022
Thu Jun 23 00:34:44 2022
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
@@ -191,9 +191,9 @@ Pinout by Pin Number:
|L9 | | |VCCO_4 | | |4 | | | | |any******| | | |
|L10 | | |VCCO_4 | | |4 | | | | |any******| | | |
|L11 | | |GND | | | | | | | | | | | |
|L12 |LEDS<3> |IOB |IO_L23P_3/VREF_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|L13 |LEDS<1> |IOB |IO_L21N_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|L14 |LEDS<0> |IOB |IO_L22P_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|L12 |LEDS<3> |IOB |IO_L23P_3/VREF_3 |TRISTATE |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|L13 |LEDS<1> |IOB |IO_L21N_3 |TRISTATE |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|L14 |LEDS<0> |IOB |IO_L22P_3 |TRISTATE |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|L15 |SW<4> |IOB |IO_L22N_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
|L16 | | |VCCAUX | | | | | | | |2.5 | | | |
|M1 | |DIFFM |IO_L20P_6 |UNUSED | |6 | | | | | | | | |
@@ -209,7 +209,7 @@ Pinout by Pin Number:
|M11 | |DIFFS |IO_L27N_4/DIN/D0 |UNUSED | |4 | | | | | | | | |
|M12 | | |VCCINT | | | | | | | |1.2 | | | |
|M13 |LEDS<5> |IOB |IO_L21P_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|M14 |LEDS<2> |IOB |IO_L19N_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|M14 |LEDS<2> |IOB |IO_L19N_3 |TRISTATE |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|M15 |SW<6> |IOB |IO_L20P_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
|M16 |SW<5> |IOB |IO_L20N_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
|N1 | |DIFFM |IO_L17P_6/VREF_6 |UNUSED | |6 | | | | | | | | |

50
main_par.xrpt
View File

@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="par" timeStamp="Wed Jun 22 23:47:54 2022">
<application stringID="par" timeStamp="Thu Jun 23 00:34:43 2022">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@@ -62,49 +62,21 @@
<item AVAILABLE="173" dataType="int" label="Number of External IOBs" stringID="PAR_EXTERNAL_IOB" value="21">
<item AVAILABLE="21" dataType="int" label="Number of LOCed IOBs" stringID="PAR_LOC_IOB" value="21"/>
</item>
<item AVAILABLE="3584" dataType="int" stringID="PAR_SLICES" value="16"></item>
<item AVAILABLE="3584" dataType="int" stringID="PAR_SLICES" value="6"></item>
</section>
</task>
<task stringID="PAR_PAR">
<section stringID="PAR_DESIGN_SUMMARY">
<item stringID="PAR_REAL_TIME_COMPLETION_ROUTER" value="3 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="3 secs "/>
<item stringID="PAR_REAL_TIME_COMPLETION_ROUTER" value="1 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="1 secs "/>
<item dataType="int" stringID="PAR_UNROUTES" value="0"/>
<item dataType="float" stringID="PAR_TIMING_SCORE" value="0.000000"/>
<item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="4 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="3 secs "/>
<item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="2 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="2 secs "/>
</section>
</task>
<task stringID="PAR_par">
<section stringID="PAR_DLY_CLK_REPORT"/>
<section stringID="PAR_CLOCK_REPORT">
<table stringID="PAR_CLOCK_TABLE">
<column label="Clock Net" stringID="CLOCK_NET"/>
<column label="Routed" stringID="ROUTED"/>
<column label="Resource" stringID="RESOURCE"/>
<column label="Locked" stringID="LOCKED"/>
<column label="Fanout" stringID="FANOUT"/>
<column label="Net Skew(ns)" stringID="NET_SKEW"/>
<column label="Max Delay(ns)" stringID="MAX_DELAY"/>
<row stringID="row" value="1">
<item label="Clock Net" stringID="CLOCK_NET" value="CLK_BUFGP"/>
<item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="BUFGMUX6"/>
<item label="Locked" stringID="LOCKED" value="No"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="13.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.001000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.015000"/>
</row>
<row stringID="row" value="2">
<item label="Clock Net" stringID="CLOCK_NET" value="contaux&lt;24>"/>
<item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="Local"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="5.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.763000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.860000"/>
</row>
</table>
</section>
<section stringID="PAR_PAD_PIN_REPORT">
<table stringID="PAR_PINOUT_BY_PIN_NUMBER">
<column label="Pin&#xA;Number" sort="smart" stringID="Pin_Number"/>
@@ -1233,7 +1205,7 @@
<item label="Signal&#xA;Name" stringID="Signal_Name" value="LEDS&lt;3>"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L23P_3/VREF_3"/>
<item stringID="Direction" value="OUTPUT"/>
<item stringID="Direction" value="TRISTATE"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
@@ -1248,7 +1220,7 @@
<item label="Signal&#xA;Name" stringID="Signal_Name" value="LEDS&lt;1>"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L21N_3"/>
<item stringID="Direction" value="OUTPUT"/>
<item stringID="Direction" value="TRISTATE"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
@@ -1263,7 +1235,7 @@
<item label="Signal&#xA;Name" stringID="Signal_Name" value="LEDS&lt;0>"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L22P_3"/>
<item stringID="Direction" value="OUTPUT"/>
<item stringID="Direction" value="TRISTATE"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
@@ -1389,7 +1361,7 @@
<item label="Signal&#xA;Name" stringID="Signal_Name" value="LEDS&lt;2>"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L19N_3"/>
<item stringID="Direction" value="OUTPUT"/>
<item stringID="Direction" value="TRISTATE"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
@@ -1881,7 +1853,7 @@
<section stringID="PAR_UNROUTES_REPORT">
<item dataType="int" stringID="PAR_UNROUTED_NETS" value="0"/>
<item dataType="int" stringID="PAR_TOTAL_SOURCELESS_NETS" value="0"/>
<item dataType="int" stringID="PAR_TOTAL_LOADLESS_NETS" value="12"/>
<item dataType="int" stringID="PAR_TOTAL_LOADLESS_NETS" value="1"/>
</section>
</task>
</application>

66
main_summary.html
View File

@@ -2,7 +2,7 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>main Project Status (06/22/2022 - 23:48:12)</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>main Project Status (06/23/2022 - 00:34:56)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>Nexys.xise</TD>
@@ -25,7 +25,7 @@ No Errors</TD>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\_xmsgs/*.xmsgs?&DataKey=Warning'>29 Warnings (15 new)</A></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\_xmsgs/*.xmsgs?&DataKey=Warning'>10 Warnings (3 new)</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
@@ -38,8 +38,7 @@ No Errors</TD>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>
<A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\main.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
@@ -59,68 +58,44 @@ System Settings</A>
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Flip Flops</TD>
<TD ALIGN=RIGHT>29</TD>
<TD ALIGN=RIGHT>7,168</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of 4 input LUTs</TD>
<TD ALIGN=RIGHT>5</TD>
<TD ALIGN=RIGHT>10</TD>
<TD ALIGN=RIGHT>7,168</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
<TD ALIGN=RIGHT>16</TD>
<TD ALIGN=RIGHT>6</TD>
<TD ALIGN=RIGHT>3,584</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of Slices containing only related logic</TD>
<TD ALIGN=RIGHT>16</TD>
<TD ALIGN=RIGHT>16</TD>
<TD ALIGN=RIGHT>6</TD>
<TD ALIGN=RIGHT>6</TD>
<TD ALIGN=RIGHT>100%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of Slices containing unrelated logic</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>16</TD>
<TD ALIGN=RIGHT>6</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Total Number of 4 input LUTs</TD>
<TD ALIGN=RIGHT>29</TD>
<TD ALIGN=RIGHT>10</TD>
<TD ALIGN=RIGHT>7,168</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
<TD ALIGN=RIGHT>5</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as a route-thru</TD>
<TD ALIGN=RIGHT>24</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\main_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
<TD ALIGN=RIGHT>21</TD>
<TD ALIGN=RIGHT>173</TD>
<TD ALIGN=RIGHT>12%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFGMUXs</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>8</TD>
<TD ALIGN=RIGHT>12%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
<TD ALIGN=RIGHT>0.96</TD>
<TD ALIGN=RIGHT>2.19</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
@@ -145,8 +120,7 @@ System Settings</A>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
<TD>
<A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\main.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
<TD>&nbsp;</TD>
<TD BGCOLOR='#FFFF99'><B>&nbsp;</B></TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TABLE>
@@ -157,21 +131,21 @@ System Settings</A>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\main.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Jun 22 23:47:37 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\_xmsgs/xst.xmsgs?&DataKey=Warning'>14 Warnings (14 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\_xmsgs/xst.xmsgs?&DataKey=Info'>1 Info (1 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\main.bld'>Translation Report</A></TD><TD>Current</TD><TD>Wed Jun 22 23:47:45 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\main_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Wed Jun 22 23:47:50 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\_xmsgs/map.xmsgs?&DataKey=Info'>4 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\main.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Wed Jun 22 23:47:57 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\_xmsgs/par.xmsgs?&DataKey=Warning'>15 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\_xmsgs/par.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\main.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Thu Jun 23 00:34:26 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\_xmsgs/xst.xmsgs?&DataKey=Warning'>7 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\_xmsgs/xst.xmsgs?&DataKey=Info'>1 Info (1 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\main.bld'>Translation Report</A></TD><TD>Current</TD><TD>Thu Jun 23 00:34:35 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\main_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Thu Jun 23 00:34:39 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\_xmsgs/map.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\main.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Thu Jun 23 00:34:44 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\_xmsgs/par.xmsgs?&DataKey=Warning'>3 Warnings (2 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\_xmsgs/par.xmsgs?&DataKey=Info'>1 Info (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\main.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Wed Jun 22 23:48:01 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\_xmsgs/trce.xmsgs?&DataKey=Info'>6 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\main.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Wed Jun 22 23:48:10 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\_xmsgs/bitgen.xmsgs?&DataKey=Info'>1 Info (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\main.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Thu Jun 23 00:34:46 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\_xmsgs/trce.xmsgs?&DataKey=Info'>6 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\main.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Thu Jun 23 00:34:53 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\_xmsgs/bitgen.xmsgs?&DataKey=Info'>1 Info (0 new)</A></TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Jun 22 23:48:10 2022</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Jun 22 23:48:12 2022</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Thu Jun 23 00:34:54 2022</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Gabriel/Xilinx/Nexys\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Thu Jun 23 00:34:55 2022</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 06/22/2022 - 23:48:13</center>
<br><center><b>Date Generated:</b> 06/23/2022 - 00:34:56</center>
</BODY></HTML>

2
main_summary.xml
View File

@@ -4,7 +4,7 @@
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DesignSummary rev="18">
<DesignSummary rev="21">
<CmdHistory>
</CmdHistory>
</DesignSummary>

314
main_usage.xml
View File

@@ -4,126 +4,84 @@
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DeviceUsageSummary rev="18">
<DesignStatistics TimeStamp="Wed Jun 22 23:48:09 2022"><group name="NetStatistics">
<item name="NumNets_Active" rev="18">
<attrib name="value" value="77"/></item>
<item name="NumNets_Gnd" rev="18">
<DeviceUsageSummary rev="21">
<DesignStatistics TimeStamp="Thu Jun 23 00:34:53 2022"><group name="NetStatistics">
<item name="NumNets_Active" rev="21">
<attrib name="value" value="42"/></item>
<item name="NumNets_Gnd" rev="21">
<attrib name="value" value="1"/></item>
<item name="NumNets_Vcc" rev="18">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Active_CLKPIN" rev="18">
<attrib name="value" value="16"/></item>
<item name="NumNodesOfType_Active_CNTRLPIN" rev="18">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Active_DOUBLE" rev="18">
<attrib name="value" value="11"/></item>
<item name="NumNodesOfType_Active_DUMMY" rev="18">
<attrib name="value" value="39"/></item>
<item name="NumNodesOfType_Active_DUMMYESC" rev="18">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Active_GLOBAL" rev="18">
<attrib name="value" value="9"/></item>
<item name="NumNodesOfType_Active_HUNIHEX" rev="18">
<item name="NumNodesOfType_Active_CNTRLPIN" rev="21">
<attrib name="value" value="4"/></item>
<item name="NumNodesOfType_Active_DOUBLE" rev="21">
<attrib name="value" value="24"/></item>
<item name="NumNodesOfType_Active_DUMMY" rev="21">
<attrib name="value" value="36"/></item>
<item name="NumNodesOfType_Active_DUMMYESC" rev="21">
<attrib name="value" value="12"/></item>
<item name="NumNodesOfType_Active_INPUT" rev="21">
<attrib name="value" value="42"/></item>
<item name="NumNodesOfType_Active_IOBOUTPUT" rev="21">
<attrib name="value" value="12"/></item>
<item name="NumNodesOfType_Active_OMUX" rev="21">
<attrib name="value" value="10"/></item>
<item name="NumNodesOfType_Active_OUTPUT" rev="21">
<attrib name="value" value="8"/></item>
<item name="NumNodesOfType_Active_PREBXBY" rev="21">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Active_INPUT" rev="18">
<attrib name="value" value="53"/></item>
<item name="NumNodesOfType_Active_IOBOUTPUT" rev="18">
<item name="NumNodesOfType_Active_VFULLHEX" rev="21">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Active_OMUX" rev="18">
<attrib name="value" value="31"/></item>
<item name="NumNodesOfType_Active_OUTPUT" rev="18">
<attrib name="value" value="43"/></item>
<item name="NumNodesOfType_Active_VFULLHEX" rev="18">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Active_VUNIHEX" rev="18">
<attrib name="value" value="3"/></item>
<item name="NumNodesOfType_Gnd_DOUBLE" rev="18">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Gnd_INPUT" rev="18">
<attrib name="value" value="7"/></item>
<item name="NumNodesOfType_Gnd_OMUX" rev="18">
<attrib name="value" value="7"/></item>
<item name="NumNodesOfType_Gnd_OUTPUT" rev="18">
<item name="NumNodesOfType_Active_VUNIHEX" rev="21">
<attrib name="value" value="6"/></item>
<item name="NumNodesOfType_Gnd_PREBXBY" rev="18">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Gnd_INPUT" rev="21">
<attrib name="value" value="4"/></item>
<item name="NumNodesOfType_Gnd_OMUX" rev="21">
<attrib name="value" value="4"/></item>
<item name="NumNodesOfType_Gnd_OUTPUT" rev="21">
<attrib name="value" value="4"/></item>
</group>
<group name="SiteStatistics">
<item name="IOB-DIFFM" rev="18">
<item name="IOB-DIFFM" rev="21">
<attrib name="value" value="12"/></item>
<item name="IOB-DIFFS" rev="18">
<item name="IOB-DIFFS" rev="21">
<attrib name="value" value="9"/></item>
<item name="SLICEL-SLICEM" rev="18">
<attrib name="value" value="15"/></item>
<item name="SLICEL-SLICEM" rev="21">
<attrib name="value" value="2"/></item>
</group>
<group name="MiscellaneousStatistics">
<item name="AGG_BONDED_IO" rev="17">
<item name="AGG_BONDED_IO" rev="20">
<attrib name="value" value="21"/></item>
<item name="AGG_IO" rev="17">
<item name="AGG_IO" rev="20">
<attrib name="value" value="21"/></item>
<item name="AGG_SLICE" rev="17">
<attrib name="value" value="16"/></item>
<item name="NUM_4_INPUT_LUT" rev="17">
<attrib name="value" value="29"/></item>
<item name="NUM_BONDED_IOB" rev="17">
<item name="AGG_SLICE" rev="20">
<attrib name="value" value="6"/></item>
<item name="NUM_4_INPUT_LUT" rev="20">
<attrib name="value" value="10"/></item>
<item name="NUM_BONDED_IOB" rev="20">
<attrib name="value" value="21"/></item>
<item name="NUM_BUFGMUX" rev="17">
<attrib name="value" value="1"/></item>
<item name="NUM_CYMUX" rev="17">
<attrib name="value" value="24"/></item>
<item name="NUM_LUT_RT" rev="17">
<attrib name="value" value="24"/></item>
<item name="NUM_SLICEL" rev="17">
<attrib name="value" value="16"/></item>
<item name="NUM_SLICE_FF" rev="17">
<attrib name="value" value="29"/></item>
<item name="NUM_XOR" rev="17">
<attrib name="value" value="25"/></item>
<item name="NUM_SLICEL" rev="20">
<attrib name="value" value="6"/></item>
</group>
</DesignStatistics>
<DeviceUsage TimeStamp="Wed Jun 22 23:48:09 2022"><group name="SiteSummary">
<item name="BUFGMUX" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="BUFGMUX_GCLKMUX" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="BUFGMUX_GCLK_BUFFER" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="IOB" rev="18">
<DeviceUsage TimeStamp="Thu Jun 23 00:34:53 2022"><group name="SiteSummary">
<item name="IOB" rev="21">
<attrib name="total" value="1000000"/><attrib name="used" value="21"/></item>
<item name="IOB_INBUF" rev="18">
<item name="IOB_INBUF" rev="21">
<attrib name="total" value="1000000"/><attrib name="used" value="13"/></item>
<item name="IOB_OUTBUF" rev="18">
<item name="IOB_OUTBUF" rev="21">
<attrib name="total" value="1000000"/><attrib name="used" value="8"/></item>
<item name="IOB_PAD" rev="18">
<item name="IOB_PAD" rev="21">
<attrib name="total" value="1000000"/><attrib name="used" value="21"/></item>
<item name="SLICEL" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="16"/></item>
<item name="SLICEL_C1VDD" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="SLICEL_CYMUXF" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="12"/></item>
<item name="SLICEL_CYMUXG" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="12"/></item>
<item name="SLICEL_F" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="15"/></item>
<item name="SLICEL_FFX" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="14"/></item>
<item name="SLICEL_FFY" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="15"/></item>
<item name="SLICEL_G" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="14"/></item>
<item name="SLICEL_GNDF" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="11"/></item>
<item name="SLICEL_GNDG" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="12"/></item>
<item name="SLICEL_XORF" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="13"/></item>
<item name="SLICEL_XORG" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="12"/></item>
<item name="SLICEL" rev="21">
<attrib name="total" value="1000000"/><attrib name="used" value="6"/></item>
<item name="SLICEL_F" rev="21">
<attrib name="total" value="1000000"/><attrib name="used" value="4"/></item>
<item name="SLICEL_F5MUX" rev="21">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="SLICEL_G" rev="21">
<attrib name="total" value="1000000"/><attrib name="used" value="6"/></item>
</group>
</DeviceUsage>
<ReportConfigData TimeStamp="Wed Jun 22 23:48:09 2022"><group name="SLICEL_CYMUXF">
<ReportConfigData TimeStamp="Thu Jun 23 00:34:53 2022"><group name="SLICEL_CYMUXF">
<item name="0" rev="18">
<attrib name="0" value="12"/><attrib name="0_INV" value="0"/></item>
<item name="1" rev="18">
@@ -134,20 +92,14 @@
<attrib name="0" value="12"/><attrib name="0_INV" value="0"/></item>
</group>
<group name="SLICEL">
<item name="BX" rev="18">
<attrib name="BX_INV" value="0"/><attrib name="BX" value="1"/></item>
<item name="BY" rev="18">
<attrib name="BY" value="1"/><attrib name="BY_INV" value="0"/></item>
<item name="CIN" rev="18">
<attrib name="CIN_INV" value="0"/><attrib name="CIN" value="12"/></item>
<item name="CLK" rev="18">
<attrib name="CLK" value="16"/><attrib name="CLK_INV" value="0"/></item>
<item name="SR" rev="18">
<attrib name="SR" value="1"/><attrib name="SR_INV" value="0"/></item>
<item name="BX" rev="21">
<attrib name="BX_INV" value="0"/><attrib name="BX" value="2"/></item>
</group>
<group name="IOB_OUTBUF">
<item name="IN" rev="18">
<item name="IN" rev="21">
<attrib name="IN_INV" value="0"/><attrib name="IN" value="8"/></item>
<item name="TRI" rev="21">
<attrib name="TRI_INV" value="0"/><attrib name="TRI" value="4"/></item>
</group>
<group name="SLICEL_FFX">
<item name="CK" rev="18">
@@ -190,27 +142,29 @@
<attrib name="S_INV" value="1"/><attrib name="S" value="0"/></item>
</group>
<group name="SLICEL_F5MUX">
<item name="S0" rev="10">
<attrib name="S0" value="1"/><attrib name="S0_INV" value="0"/></item>
<item name="S0" rev="21">
<attrib name="S0" value="2"/><attrib name="S0_INV" value="0"/></item>
</group>
<group name="IOB_PAD">
<item name="DRIVEATTRBOX" rev="18">
<item name="DRIVEATTRBOX" rev="21">
<attrib name="12" value="8"/></item>
<item name="IOATTRBOX" rev="18">
<item name="IOATTRBOX" rev="21">
<attrib name="LVCMOS25" value="21"/></item>
<item name="SLEW" rev="18">
<item name="SLEW" rev="21">
<attrib name="SLOW" value="8"/></item>
</group>
<group name="IOB">
<item name="O1" rev="18">
<item name="O1" rev="21">
<attrib name="O1_INV" value="0"/><attrib name="O1" value="8"/></item>
<item name="T1" rev="21">
<attrib name="T1_INV" value="0"/><attrib name="T1" value="4"/></item>
</group>
<group name="BUFGMUX">
<item name="S" rev="18">
<attrib name="S_INV" value="1"/><attrib name="S" value="0"/></item>
</group>
</ReportConfigData>
<ReportPinData TimeStamp="Wed Jun 22 23:48:09 2022"><group name="SLICEL_CYMUXF">
<ReportPinData TimeStamp="Thu Jun 23 00:34:53 2022"><group name="SLICEL_CYMUXF">
<item name="0" rev="18">
<attrib name="value" value="12"/></item>
<item name="1" rev="18">
@@ -237,49 +191,41 @@
<attrib name="value" value="1"/></item>
</group>
<group name="SLICEL">
<item name="BX" rev="18">
<attrib name="value" value="1"/></item>
<item name="BY" rev="18">
<attrib name="value" value="1"/></item>
<item name="CIN" rev="18">
<attrib name="value" value="12"/></item>
<item name="CLK" rev="18">
<attrib name="value" value="16"/></item>
<item name="COUT" rev="18">
<attrib name="value" value="12"/></item>
<item name="F1" rev="18">
<attrib name="value" value="15"/></item>
<item name="F2" rev="18">
<item name="BX" rev="21">
<attrib name="value" value="2"/></item>
<item name="F3" rev="18">
<attrib name="value" value="2"/></item>
<item name="F4" rev="18">
<attrib name="value" value="2"/></item>
<item name="G1" rev="18">
<attrib name="value" value="14"/></item>
<item name="G2" rev="18">
<attrib name="value" value="2"/></item>
<item name="G3" rev="18">
<attrib name="value" value="1"/></item>
<item name="SR" rev="18">
<attrib name="value" value="1"/></item>
<item name="X" rev="18">
<attrib name="value" value="1"/></item>
<item name="XQ" rev="18">
<attrib name="value" value="14"/></item>
<item name="YQ" rev="18">
<attrib name="value" value="15"/></item>
<item name="F1" rev="21">
<attrib name="value" value="4"/></item>
<item name="F2" rev="21">
<attrib name="value" value="4"/></item>
<item name="F3" rev="21">
<attrib name="value" value="4"/></item>
<item name="F4" rev="21">
<attrib name="value" value="3"/></item>
<item name="G1" rev="21">
<attrib name="value" value="6"/></item>
<item name="G2" rev="21">
<attrib name="value" value="6"/></item>
<item name="G3" rev="21">
<attrib name="value" value="5"/></item>
<item name="G4" rev="21">
<attrib name="value" value="4"/></item>
<item name="X" rev="21">
<attrib name="value" value="4"/></item>
<item name="Y" rev="21">
<attrib name="value" value="4"/></item>
</group>
<group name="IOB_OUTBUF">
<item name="IN" rev="18">
<item name="IN" rev="21">
<attrib name="value" value="8"/></item>
<item name="OUT" rev="18">
<item name="OUT" rev="21">
<attrib name="value" value="8"/></item>
<item name="TRI" rev="21">
<attrib name="value" value="4"/></item>
</group>
<group name="IOB_INBUF">
<item name="IN" rev="18">
<item name="IN" rev="21">
<attrib name="value" value="13"/></item>
<item name="OUT" rev="18">
<item name="OUT" rev="21">
<attrib name="value" value="13"/></item>
</group>
<group name="SLICEL_FFX">
@@ -329,26 +275,28 @@
<attrib name="value" value="1"/></item>
</group>
<group name="SLICEL_F5MUX">
<item name="F" rev="10">
<attrib name="value" value="1"/></item>
<item name="G" rev="10">
<attrib name="value" value="1"/></item>
<item name="OUT" rev="10">
<attrib name="value" value="1"/></item>
<item name="S0" rev="10">
<attrib name="value" value="1"/></item>
<item name="F" rev="21">
<attrib name="value" value="2"/></item>
<item name="G" rev="21">
<attrib name="value" value="2"/></item>
<item name="OUT" rev="21">
<attrib name="value" value="2"/></item>
<item name="S0" rev="21">
<attrib name="value" value="2"/></item>
</group>
<group name="IOB_PAD">
<item name="PAD" rev="18">
<item name="PAD" rev="21">
<attrib name="value" value="21"/></item>
</group>
<group name="IOB">
<item name="I" rev="18">
<item name="I" rev="21">
<attrib name="value" value="13"/></item>
<item name="O1" rev="18">
<item name="O1" rev="21">
<attrib name="value" value="8"/></item>
<item name="PAD" rev="18">
<item name="PAD" rev="21">
<attrib name="value" value="21"/></item>
<item name="T1" rev="21">
<attrib name="value" value="4"/></item>
</group>
<group name="SLICEL_C1VDD">
<item name="1" rev="18">
@@ -363,26 +311,28 @@
<attrib name="value" value="1"/></item>
</group>
<group name="SLICEL_F">
<item name="A1" rev="18">
<attrib name="value" value="15"/></item>
<item name="A2" rev="18">
<attrib name="value" value="2"/></item>
<item name="A3" rev="18">
<attrib name="value" value="2"/></item>
<item name="A4" rev="18">
<attrib name="value" value="2"/></item>
<item name="D" rev="18">
<attrib name="value" value="15"/></item>
<item name="A1" rev="21">
<attrib name="value" value="4"/></item>
<item name="A2" rev="21">
<attrib name="value" value="4"/></item>
<item name="A3" rev="21">
<attrib name="value" value="4"/></item>
<item name="A4" rev="21">
<attrib name="value" value="3"/></item>
<item name="D" rev="21">
<attrib name="value" value="4"/></item>
</group>
<group name="SLICEL_G">
<item name="A1" rev="18">
<attrib name="value" value="14"/></item>
<item name="A2" rev="18">
<attrib name="value" value="2"/></item>
<item name="A3" rev="18">
<attrib name="value" value="1"/></item>
<item name="D" rev="18">
<attrib name="value" value="14"/></item>
<item name="A1" rev="21">
<attrib name="value" value="6"/></item>
<item name="A2" rev="21">
<attrib name="value" value="6"/></item>
<item name="A3" rev="21">
<attrib name="value" value="5"/></item>
<item name="A4" rev="21">
<attrib name="value" value="4"/></item>
<item name="D" rev="21">
<attrib name="value" value="6"/></item>
</group>
<group name="SLICEL_GNDF">
<item name="0" rev="18">

2
main_vhdl.prj
View File

@@ -1,2 +1,2 @@
vhdl work "C:\Users\Gabriel\Xilinx\Nexys\CONTBIN_4BIT.vhd"
vhdl work "C:\Users\Gabriel\Xilinx\Nexys\ULA_P379.vhd"
vhdl work "C:\Users\Gabriel\Xilinx\Nexys\main.vhd"

55
main_xst.xrpt
View File

@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Wed Jun 22 23:47:30 2022">
<application stringID="Xst" timeStamp="Thu Jun 23 00:34:21 2022">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@@ -106,24 +106,18 @@
<item DEFAULT="0%" label="-slice_utilization_ratio_maxmargin" stringID="XST_SLICEUTILIZATIONRATIOMAXMARGIN" value="5"/>
</section>
<section stringID="XST_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_COUNTERS" value="3">
<item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="1"></item>
<item dataType="int" stringID="XST_COUNTERS" value="1">
<item dataType="int" stringID="XST_16BIT_DOWN_COUNTER" value="1"/>
<item dataType="int" stringID="XST_4BIT_UP_COUNTER" value="1"/>
</item>
<item dataType="int" stringID="XST_TRISTATES" value="2">
<item dataType="int" stringID="XST_1BIT_TRISTATE_BUFFER" value="2"/>
<item dataType="int" stringID="XST_TRISTATES" value="5">
<item dataType="int" stringID="XST_1BIT_TRISTATE_BUFFER" value="4"/>
</item>
</section>
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_COUNTERS" value="2">
<item dataType="int" stringID="XST_4BIT_UP_COUNTER" value="1"/>
</item>
</section>
<section stringID="XST_FINAL_REGISTER_REPORT">
<item dataType="int" stringID="XST_REGISTERS" value="29">
<item dataType="int" stringID="XST_FLIPFLOPS" value="29"/>
</item>
<item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="1"></item>
</section>
<section stringID="XST_FINAL_REGISTER_REPORTFOUND_NO_MACRO"/>
<section stringID="XST_PARTITION_REPORT">
<section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
@@ -141,44 +135,33 @@
<item stringID="XST_IOS" value="21"/>
</section>
<section stringID="XST_CELL_USAGE">
<item dataType="int" stringID="XST_BELS" value="80">
<item dataType="int" stringID="XST_BELS" value="13">
<item dataType="int" stringID="XST_GND" value="1"/>
<item dataType="int" stringID="XST_INV" value="1"/>
<item dataType="int" stringID="XST_LUT1" value="24"/>
<item dataType="int" stringID="XST_LUT2" value="1"/>
<item dataType="int" stringID="XST_LUT3" value="1"/>
<item dataType="int" stringID="XST_LUT4" value="2"/>
<item dataType="int" stringID="XST_MUXCY" value="24"/>
<item dataType="int" stringID="XST_VCC" value="1"/>
<item dataType="int" stringID="XST_XORCY" value="25"/>
<item dataType="int" stringID="XST_LUT3" value="2"/>
<item dataType="int" stringID="XST_LUT4" value="7"/>
<item dataType="int" stringID="XST_MUXF5" value="2"/>
</item>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="29">
<item dataType="int" stringID="XST_FD" value="28"/>
<item dataType="int" stringID="XST_FDR" value="1"/>
</item>
<item dataType="int" stringID="XST_CLOCK_BUFFERS" value="1">
<item dataType="int" stringID="XST_BUFGP" value="1"/>
</item>
<item dataType="int" stringID="XST_IO_BUFFERS" value="8">
<item dataType="int" stringID="XST_OBUF" value="8"/>
<item dataType="int" stringID="XST_IO_BUFFERS" value="20">
<item dataType="int" stringID="XST_IBUF" value="12"/>
<item dataType="int" stringID="XST_OBUF" value="4"/>
<item dataType="int" stringID="XST_OBUFT" value="4"/>
</item>
</section>
</section>
<section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
<item stringID="XST_SELECTED_DEVICE" value="3s400ft256-4"/>
<item AVAILABLE="3584" dataType="int" label="Number of Slices" stringID="XST_NUMBER_OF_SLICES" value="16"/>
<item AVAILABLE="7168" dataType="int" label="Number of Slice Flip Flops" stringID="XST_NUMBER_OF_SLICE_FLIP_FLOPS" value="29"/>
<item AVAILABLE="7168" dataType="int" label="Number of 4 input LUTs" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="29"/>
<item AVAILABLE="3584" dataType="int" label="Number of Slices" stringID="XST_NUMBER_OF_SLICES" value="5"/>
<item AVAILABLE="7168" dataType="int" label="Number of 4 input LUTs" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="10"/>
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="21"/>
<item AVAILABLE="173" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="9"/>
<item AVAILABLE="8" dataType="int" label="Number of GCLKs" stringID="XST_NUMBER_OF_GCLKS" value="1"/>
<item AVAILABLE="173" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="20"/>
</section>
<section stringID="XST_PARTITION_RESOURCE_SUMMARY">
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
</section>
<section stringID="XST_ERRORS_STATISTICS">
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="14"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="7"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="1"/>
</section>
</application>

249
usage_statistics_webtalk.html
View File

@@ -17,7 +17,7 @@
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project ID (random number)</B></TD>
<TD><xtag-property name="RandomID">bd16c3ee05c44948bef10dae3c70184a</xtag-property>.<xtag-property name="ProjectID">37E34B403210454999E9696C4C0C3A46</xtag-property>.<xtag-property name="ProjectIteration">9</xtag-property></TD>
<TD><xtag-property name="RandomID">bd16c3ee05c44948bef10dae3c70184a</xtag-property>.<xtag-property name="ProjectID">37E34B403210454999E9696C4C0C3A46</xtag-property>.<xtag-property name="ProjectIteration">11</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Package:</B></TD>
<TD><xtag-property name="TargetPackage">ft256</xtag-property></TD>
</TR>
@@ -29,7 +29,7 @@
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Date Generated</B></TD>
<TD><xtag-property name="Date Generated">2022-06-22T23:48:10</xtag-property></TD>
<TD><xtag-property name="Date Generated">2022-06-23T00:34:54</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Tool Flow</B></TD>
<TD><xtag-property name="ToolFlow">ISE</xtag-property></TD>
</TR>
@@ -55,10 +55,9 @@
<TR ALIGN=CENTER BGCOLOR='#FFFF99'><TD><B>Macro Statistics</B></TD><TD><B>Miscellaneous Statistics</B></TD><TD><B>Net Statistics</B></TD><TD><B>Site Usage</B></TD></TR><TR VALIGN=TOP>
<xtag-section name="MacroStatistics">
<TD>
<xtag-group><xtag-group-name name="Counters=2">Counters=2</xtag-group-name>
<xtag-group><xtag-group-name name="Adders/Subtractors=1">Adders/Subtractors=1</xtag-group-name>
<UL>
<LI><xtag-item1>32-bit up counter=1</xtag-item1></LI>
<LI><xtag-item1>4-bit up counter=1</xtag-item1></LI>
<LI><xtag-item1>4-bit addsub=1</xtag-item1></LI>
</UL>
</xtag-group>
</TD>
@@ -69,49 +68,39 @@
<UL>
<LI><xtag-item1>AGG_BONDED_IO=21</xtag-item1></LI>
<LI><xtag-item1>AGG_IO=21</xtag-item1></LI>
<LI><xtag-item1>AGG_SLICE=16</xtag-item1></LI>
<LI><xtag-item1>NUM_4_INPUT_LUT=29</xtag-item1></LI>
<LI><xtag-item1>AGG_SLICE=6</xtag-item1></LI>
<LI><xtag-item1>NUM_4_INPUT_LUT=10</xtag-item1></LI>
<LI><xtag-item1>NUM_BONDED_IOB=21</xtag-item1></LI>
<LI><xtag-item1>NUM_BUFGMUX=1</xtag-item1></LI>
<LI><xtag-item1>NUM_CYMUX=24</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT=24</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEL=16</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_FF=29</xtag-item1></LI>
<LI><xtag-item1>NUM_XOR=25</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEL=6</xtag-item1></LI>
</UL>
</xtag-group>
</TD>
<TD>
<xtag-group><xtag-group-name name="NetStatistics">NetStatistics</xtag-group-name>
<UL>
<LI><xtag-item1>NumNets_Active=77</xtag-item1></LI>
<LI><xtag-item1>NumNets_Active=42</xtag-item1></LI>
<LI><xtag-item1>NumNets_Gnd=1</xtag-item1></LI>
<LI><xtag-item1>NumNets_Vcc=1</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=16</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CNTRLPIN=1</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=11</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DUMMY=39</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DUMMYESC=1</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=9</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_HUNIHEX=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_INPUT=53</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBOUTPUT=1</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OMUX=31</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=43</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CNTRLPIN=4</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=24</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DUMMY=36</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DUMMYESC=12</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_INPUT=42</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBOUTPUT=12</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OMUX=10</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=8</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PREBXBY=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_VFULLHEX=1</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_VUNIHEX=3</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_DOUBLE=1</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_INPUT=7</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_OMUX=7</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_OUTPUT=6</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_PREBXBY=1</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_VUNIHEX=6</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_INPUT=4</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_OMUX=4</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_OUTPUT=4</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SiteStatistics">SiteStatistics</xtag-group-name>
<UL>
<LI><xtag-item1>IOB-DIFFM=12</xtag-item1></LI>
<LI><xtag-item1>IOB-DIFFS=9</xtag-item1></LI>
<LI><xtag-item1>SLICEL-SLICEM=15</xtag-item1></LI>
<LI><xtag-item1>SLICEL-SLICEM=2</xtag-item1></LI>
</UL>
</xtag-group>
</TD>
@@ -120,25 +109,14 @@
<TD>
<xtag-group><xtag-group-name name="SiteSummary">SiteSummary</xtag-group-name>
<UL>
<LI><xtag-item2>BUFGMUX=1</xtag-item2></LI>
<LI><xtag-item2>BUFGMUX_GCLKMUX=1</xtag-item2></LI>
<LI><xtag-item2>BUFGMUX_GCLK_BUFFER=1</xtag-item2></LI>
<LI><xtag-item2>IOB=21</xtag-item2></LI>
<LI><xtag-item2>IOB_INBUF=13</xtag-item2></LI>
<LI><xtag-item2>IOB_OUTBUF=8</xtag-item2></LI>
<LI><xtag-item2>IOB_PAD=21</xtag-item2></LI>
<LI><xtag-item2>SLICEL=16</xtag-item2></LI>
<LI><xtag-item2>SLICEL_C1VDD=1</xtag-item2></LI>
<LI><xtag-item2>SLICEL_CYMUXF=12</xtag-item2></LI>
<LI><xtag-item2>SLICEL_CYMUXG=12</xtag-item2></LI>
<LI><xtag-item2>SLICEL_F=15</xtag-item2></LI>
<LI><xtag-item2>SLICEL_FFX=14</xtag-item2></LI>
<LI><xtag-item2>SLICEL_FFY=15</xtag-item2></LI>
<LI><xtag-item2>SLICEL_G=14</xtag-item2></LI>
<LI><xtag-item2>SLICEL_GNDF=11</xtag-item2></LI>
<LI><xtag-item2>SLICEL_GNDG=12</xtag-item2></LI>
<LI><xtag-item2>SLICEL_XORF=13</xtag-item2></LI>
<LI><xtag-item2>SLICEL_XORG=12</xtag-item2></LI>
<LI><xtag-item2>SLICEL=6</xtag-item2></LI>
<LI><xtag-item2>SLICEL_F=4</xtag-item2></LI>
<LI><xtag-item2>SLICEL_F5MUX=2</xtag-item2></LI>
<LI><xtag-item2>SLICEL_G=6</xtag-item2></LI>
</UL>
</xtag-group>
</TD>
@@ -162,12 +140,16 @@
<xtag-group><xtag-group-name name="IOB">IOB</xtag-group-name>
<UL>
<LI><xtag-item3>O1=[O1_INV:0] [O1:8]</xtag-item3></LI>
<LI><xtag-item3>T1=[T1_INV:0] [T1:4]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOB_OUTBUF">IOB_OUTBUF</xtag-group-name>
<UL>
<LI><xtag-item3>IN=[IN_INV:0] [IN:8]</xtag-item3></LI>
<LI><xtag-item3>TRI=[TRI_INV:0] [TRI:4]</xtag-item3></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="IOB_PAD">IOB_PAD</xtag-group-name>
<UL>
@@ -175,16 +157,10 @@
<LI><xtag-item3>IOATTRBOX=[LVCMOS25:21]</xtag-item3></LI>
<LI><xtag-item3>SLEW=[SLOW:8]</xtag-item3></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name>
<UL>
<LI><xtag-item3>BX=[BX_INV:0] [BX:1]</xtag-item3></LI>
<LI><xtag-item3>BY=[BY:1] [BY_INV:0]</xtag-item3></LI>
<LI><xtag-item3>CIN=[CIN_INV:0] [CIN:12]</xtag-item3></LI>
<LI><xtag-item3>CLK=[CLK:16] [CLK_INV:0]</xtag-item3></LI>
<LI><xtag-item3>SR=[SR:1] [SR_INV:0]</xtag-item3></LI>
<LI><xtag-item3>BX=[BX_INV:0] [BX:2]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_CYMUXF">SLICEL_CYMUXF</xtag-group-name>
@@ -192,17 +168,17 @@
<LI><xtag-item3>0=[0:12] [0_INV:0]</xtag-item3></LI>
<LI><xtag-item3>1=[1_INV:0] [1:12]</xtag-item3></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_CYMUXG">SLICEL_CYMUXG</xtag-group-name>
<UL>
<LI><xtag-item3>0=[0:12] [0_INV:0]</xtag-item3></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_F5MUX">SLICEL_F5MUX</xtag-group-name>
<UL>
<LI><xtag-item3>S0=[S0:1] [S0_INV:0]</xtag-item3></LI>
<LI><xtag-item3>S0=[S0:2] [S0_INV:0]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_FFX">SLICEL_FFX</xtag-group-name>
@@ -267,6 +243,7 @@
<LI><xtag-item1>I=13</xtag-item1></LI>
<LI><xtag-item1>O1=8</xtag-item1></LI>
<LI><xtag-item1>PAD=21</xtag-item1></LI>
<LI><xtag-item1>T1=4</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOB_INBUF">IOB_INBUF</xtag-group-name>
@@ -279,7 +256,10 @@
<UL>
<LI><xtag-item1>IN=8</xtag-item1></LI>
<LI><xtag-item1>OUT=8</xtag-item1></LI>
<LI><xtag-item1>TRI=4</xtag-item1></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="IOB_PAD">IOB_PAD</xtag-group-name>
<UL>
@@ -288,25 +268,18 @@
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name>
<UL>
<LI><xtag-item1>BX=1</xtag-item1></LI>
<LI><xtag-item1>BY=1</xtag-item1></LI>
<LI><xtag-item1>CIN=12</xtag-item1></LI>
<LI><xtag-item1>CLK=16</xtag-item1></LI>
<LI><xtag-item1>COUT=12</xtag-item1></LI>
<LI><xtag-item1>F1=15</xtag-item1></LI>
<LI><xtag-item1>F2=2</xtag-item1></LI>
<LI><xtag-item1>F3=2</xtag-item1></LI>
<LI><xtag-item1>F4=2</xtag-item1></LI>
<LI><xtag-item1>G1=14</xtag-item1></LI>
<LI><xtag-item1>G2=2</xtag-item1></LI>
<LI><xtag-item1>G3=1</xtag-item1></LI>
<LI><xtag-item1>SR=1</xtag-item1></LI>
<LI><xtag-item1>X=1</xtag-item1></LI>
<LI><xtag-item1>XQ=14</xtag-item1></LI>
<LI><xtag-item1>YQ=15</xtag-item1></LI>
<LI><xtag-item1>BX=2</xtag-item1></LI>
<LI><xtag-item1>F1=4</xtag-item1></LI>
<LI><xtag-item1>F2=4</xtag-item1></LI>
<LI><xtag-item1>F3=4</xtag-item1></LI>
<LI><xtag-item1>F4=3</xtag-item1></LI>
<LI><xtag-item1>G1=6</xtag-item1></LI>
<LI><xtag-item1>G2=6</xtag-item1></LI>
<LI><xtag-item1>G3=5</xtag-item1></LI>
<LI><xtag-item1>G4=4</xtag-item1></LI>
<LI><xtag-item1>X=4</xtag-item1></LI>
<LI><xtag-item1>Y=4</xtag-item1></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_C1VDD">SLICEL_C1VDD</xtag-group-name>
<UL>
@@ -325,6 +298,8 @@
<LI><xtag-item1>OUT=12</xtag-item1></LI>
<LI><xtag-item1>S0=12</xtag-item1></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_CYMUXG">SLICEL_CYMUXG</xtag-group-name>
<UL>
@@ -336,22 +311,20 @@
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_F">SLICEL_F</xtag-group-name>
<UL>
<LI><xtag-item1>A1=15</xtag-item1></LI>
<LI><xtag-item1>A2=2</xtag-item1></LI>
<LI><xtag-item1>A3=2</xtag-item1></LI>
<LI><xtag-item1>A4=2</xtag-item1></LI>
<LI><xtag-item1>D=15</xtag-item1></LI>
<LI><xtag-item1>A1=4</xtag-item1></LI>
<LI><xtag-item1>A2=4</xtag-item1></LI>
<LI><xtag-item1>A3=4</xtag-item1></LI>
<LI><xtag-item1>A4=3</xtag-item1></LI>
<LI><xtag-item1>D=4</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_F5MUX">SLICEL_F5MUX</xtag-group-name>
<UL>
<LI><xtag-item1>F=1</xtag-item1></LI>
<LI><xtag-item1>G=1</xtag-item1></LI>
<LI><xtag-item1>OUT=1</xtag-item1></LI>
<LI><xtag-item1>S0=1</xtag-item1></LI>
<LI><xtag-item1>F=2</xtag-item1></LI>
<LI><xtag-item1>G=2</xtag-item1></LI>
<LI><xtag-item1>OUT=2</xtag-item1></LI>
<LI><xtag-item1>S0=2</xtag-item1></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_FFX">SLICEL_FFX</xtag-group-name>
<UL>
@@ -367,13 +340,16 @@
<LI><xtag-item1>Q=15</xtag-item1></LI>
<LI><xtag-item1>SR=1</xtag-item1></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_G">SLICEL_G</xtag-group-name>
<UL>
<LI><xtag-item1>A1=14</xtag-item1></LI>
<LI><xtag-item1>A2=2</xtag-item1></LI>
<LI><xtag-item1>A3=1</xtag-item1></LI>
<LI><xtag-item1>D=14</xtag-item1></LI>
<LI><xtag-item1>A1=6</xtag-item1></LI>
<LI><xtag-item1>A2=6</xtag-item1></LI>
<LI><xtag-item1>A3=5</xtag-item1></LI>
<LI><xtag-item1>A4=4</xtag-item1></LI>
<LI><xtag-item1>D=6</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_GNDF">SLICEL_GNDF</xtag-group-name>
@@ -399,8 +375,6 @@
<LI><xtag-item1>1=12</xtag-item1></LI>
<LI><xtag-item1>O=12</xtag-item1></LI>
</UL>
</TD>
<TD>
</xtag-group>
</TD>
</xtag-section>
@@ -486,6 +460,23 @@
<LI><xtag-cmdline>par -w -intstyle ise -ol high -t 1 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc3s400-ft256-4 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc3s400-ft256-4 -cm area -ir off -pr off -c 100 -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -t 1 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc3s400-ft256-4 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc3s400-ft256-4 -cm area -ir off -pr off -c 100 -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -t 1 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
</xtag-section></UL></TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'><xtag-section name="RunStatistics"><TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=8><B>Software Quality</B></TD></TR><TR ALIGN=LEFT><TD COLSPAN=8><B>Run Statistics</B></TD></TR><TR ALIGN=CENTER BGCOLOR='#FFFF99'><TD><B>Program Name</B></TD><TD><B>Runs Started</B></TD><TD><B>Runs Finished</B></TD><TD><B>Errors</B></TD><TD><B>Fatal Errors</B></TD><TD><B>Internal Errors</B></TD><TD><B>Exceptions</B></TD><TD><B>Core Dumps</B></TD></TR>
@@ -502,8 +493,8 @@
</tr>
<tr>
<td><xtag-program-name>bitgen</xtag-program-name></td>
<td><xtag-total-run-started>54</xtag-total-run-started></td>
<td><xtag-total-run-finished>54</xtag-total-run-finished></td>
<td><xtag-total-run-started>55</xtag-total-run-started></td>
<td><xtag-total-run-finished>55</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@@ -512,8 +503,8 @@
</tr>
<tr>
<td><xtag-program-name>map</xtag-program-name></td>
<td><xtag-total-run-started>58</xtag-total-run-started></td>
<td><xtag-total-run-finished>53</xtag-total-run-finished></td>
<td><xtag-total-run-started>60</xtag-total-run-started></td>
<td><xtag-total-run-finished>55</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@@ -522,8 +513,8 @@
</tr>
<tr>
<td><xtag-program-name>ngdbuild</xtag-program-name></td>
<td><xtag-total-run-started>58</xtag-total-run-started></td>
<td><xtag-total-run-finished>58</xtag-total-run-finished></td>
<td><xtag-total-run-started>60</xtag-total-run-started></td>
<td><xtag-total-run-finished>60</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@@ -532,8 +523,8 @@
</tr>
<tr>
<td><xtag-program-name>par</xtag-program-name></td>
<td><xtag-total-run-started>53</xtag-total-run-started></td>
<td><xtag-total-run-finished>53</xtag-total-run-finished></td>
<td><xtag-total-run-started>55</xtag-total-run-started></td>
<td><xtag-total-run-finished>55</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@@ -542,8 +533,8 @@
</tr>
<tr>
<td><xtag-program-name>trce</xtag-program-name></td>
<td><xtag-total-run-started>53</xtag-total-run-started></td>
<td><xtag-total-run-finished>53</xtag-total-run-finished></td>
<td><xtag-total-run-started>55</xtag-total-run-started></td>
<td><xtag-total-run-finished>55</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@@ -552,8 +543,8 @@
</tr>
<tr>
<td><xtag-program-name>xst</xtag-program-name></td>
<td><xtag-total-run-started>118</xtag-total-run-started></td>
<td><xtag-total-run-finished>118</xtag-total-run-finished></td>
<td><xtag-total-run-started>126</xtag-total-run-started></td>
<td><xtag-total-run-finished>126</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@@ -591,7 +582,7 @@ Help files</xtag-group-name></B></TD></TR>
<TD><xtag-design-property-name>PROP_intProjectCreationTimestamp</xtag-design-property-name>=<xtag-design-property-value>2022-06-22T20:20:13</xtag-design-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_intWbtProjectID</xtag-design-property-name>=<xtag-design-property-value>37E34B403210454999E9696C4C0C3A46</xtag-design-property-value></TD>
<TD><xtag-process-property-name>PROP_intWbtProjectIteration</xtag-process-property-name>=<xtag-process-property-value>9</xtag-process-property-value></TD>
<TD><xtag-process-property-name>PROP_intWbtProjectIteration</xtag-process-property-name>=<xtag-process-property-value>11</xtag-process-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_intWorkingDirLocWRTProjDir</xtag-design-property-name>=<xtag-design-property-value>Same</xtag-design-property-value></TD>
<TD><xtag-design-property-name>PROP_intWorkingDirUsed</xtag-design-property-name>=<xtag-design-property-value>No</xtag-design-property-value></TD>
@@ -609,53 +600,35 @@ Help files</xtag-group-name></B></TD></TR>
<TD><xtag-design-property-name>PROP_PreferredLanguage</xtag-design-property-name>=<xtag-design-property-value>VHDL</xtag-design-property-value></TD>
</TR><TR><TD><xtag-source-property-name>FILE_UCF</xtag-source-property-name>=<xtag-source-property-value>1</xtag-source-property-value></TD>
<TD><xtag-source-property-name>FILE_VHDL</xtag-source-property-name>=<xtag-source-property-value>3</xtag-source-property-value></TD>
<TD><xtag-source-property-name>FILE_VHDL</xtag-source-property-name>=<xtag-source-property-value>4</xtag-source-property-value></TD>
</TR></xtag-section></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="UnisimStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Unisim Statistics</B></TD></TR>
<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_PRE_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFGP</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FD</xtag-preunisim-param-name>=<xtag-preunisim-param-value>28</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDR</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_GND</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_INV</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>24</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_IBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>12</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT2</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT3</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT3</xtag-preunisim-param-name>=<xtag-preunisim-param-value>2</xtag-preunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT4</xtag-preunisim-param-name>=<xtag-preunisim-param-value>2</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>24</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>8</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_VCC</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT4</xtag-preunisim-param-name>=<xtag-preunisim-param-value>7</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXF5</xtag-preunisim-param-name>=<xtag-preunisim-param-value>2</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>4</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUFT</xtag-preunisim-param-name>=<xtag-preunisim-param-value>4</xtag-preunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_XORCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>25</xtag-preunisim-param-value></TD>
<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_POST_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_BUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FD</xtag-postunisim-param-name>=<xtag-postunisim-param-value>28</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDR</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_GND</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>12</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_INV</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>24</xtag-postunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>13</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT2</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT3</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT4</xtag-postunisim-param-name>=<xtag-postunisim-param-value>2</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>24</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT3</xtag-postunisim-param-name>=<xtag-postunisim-param-value>2</xtag-postunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>8</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_VCC</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_XORCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>25</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT4</xtag-postunisim-param-name>=<xtag-postunisim-param-value>7</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXF5</xtag-postunisim-param-name>=<xtag-postunisim-param-value>2</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>4</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUFT</xtag-postunisim-param-name>=<xtag-postunisim-param-value>4</xtag-postunisim-param-value></TD>
</TR>
</xtag-section></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="XstCommandLineOptions">

2
webtalk.log
View File

@@ -4,7 +4,7 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Project Information
--------------------
ProjectID=37E34B403210454999E9696C4C0C3A46
ProjectIteration=9
ProjectIteration=11
WebTalk Summary
----------------

8
webtalk_pn.xml
View File

@@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Wed Jun 22 23:47:52 2022">
<application name="pn" timeStamp="Thu Jun 23 00:34:41 2022">
<section name="Project Information" visible="false">
<property name="ProjectID" value="37E34B403210454999E9696C4C0C3A46" type="project"/>
<property name="ProjectIteration" value="9" type="project"/>
<property name="ProjectIteration" value="11" type="project"/>
<property name="ProjectFile" value="C:/Users/Gabriel/Xilinx/Nexys/Nexys.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2022-06-22T20:20:13" type="project"/>
</section>
@@ -24,7 +24,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2022-06-22T20:20:13" type="design"/>
<property name="PROP_intWbtProjectID" value="37E34B403210454999E9696C4C0C3A46" type="design"/>
<property name="PROP_intWbtProjectIteration" value="9" type="process"/>
<property name="PROP_intWbtProjectIteration" value="11" type="process"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_AutoTop" value="true" type="design"/>
@@ -36,7 +36,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_DevSpeed" value="-4" type="design"/>
<property name="PROP_PreferredLanguage" value="VHDL" type="design"/>
<property name="FILE_UCF" value="1" type="source"/>
<property name="FILE_VHDL" value="3" type="source"/>
<property name="FILE_VHDL" value="4" type="source"/>
</section>
</application>
</document>

BIN
xlnx_auto_0_xdb/cst.xbcd
View File

Binary file not shown.

6
xst/work/hdllib.ref
View File

@@ -1,6 +1,8 @@
EN contbin_4bit NULL C:/Users/Gabriel/Xilinx/Nexys/CONTBIN_4BIT.vhd sub00/vhpl04 1655952451
AR main behavioral C:/Users/Gabriel/Xilinx/Nexys/main.vhd sub00/vhpl01 1655952454
EN main NULL C:/Users/Gabriel/Xilinx/Nexys/main.vhd sub00/vhpl00 1655952453
AR main behavioral C:/Users/Gabriel/Xilinx/Nexys/main.vhd sub00/vhpl01 1655955265
EN ula_p379 NULL C:/Users/Gabriel/Xilinx/Nexys/ULA_P379.vhd sub00/vhpl06 1655955262
EN main NULL C:/Users/Gabriel/Xilinx/Nexys/main.vhd sub00/vhpl00 1655955264
EN contbcd_c NULL C:/Users/Gabriel/Xilinx/Nexys/CONTBCD_C.vhd sub00/vhpl02 1655944967
AR ula_p379 behavioral C:/Users/Gabriel/Xilinx/Nexys/ULA_P379.vhd sub00/vhpl07 1655955263
AR contbin_4bit behavioral C:/Users/Gabriel/Xilinx/Nexys/CONTBIN_4BIT.vhd sub00/vhpl05 1655952452
AR contbcd_c comportamento C:/Users/Gabriel/Xilinx/Nexys/CONTBCD_C.vhd sub00/vhpl03 1655944968

20
xst/work/hdpdeps.ref
View File

@@ -1,4 +1,4 @@
V3 10
V3 13
FL C:/Users/Gabriel/Xilinx/Nexys/CONTBCD_C.vhd 2022/06/22.21:42:00 P.20131013
EN work/CONTBCD_C 1655944967 FL C:/Users/Gabriel/Xilinx/Nexys/CONTBCD_C.vhd \
PB ieee/std_logic_1164 1381692176 PB ieee/std_logic_arith 1381692177 \
@@ -11,10 +11,16 @@ EN work/CONTBIN_4BIT 1655952451 FL C:/Users/Gabriel/Xilinx/Nexys/CONTBIN_4BIT.vh
PB ieee/STD_LOGIC_UNSIGNED 1381692179
AR work/CONTBIN_4BIT/Behavioral 1655952452 \
FL C:/Users/Gabriel/Xilinx/Nexys/CONTBIN_4BIT.vhd EN work/CONTBIN_4BIT 1655952451
FL C:/Users/Gabriel/Xilinx/Nexys/main.vhd 2022/06/22.23:47:26 P.20131013
EN work/main 1655952453 FL C:/Users/Gabriel/Xilinx/Nexys/main.vhd \
FL C:/Users/Gabriel/Xilinx/Nexys/main.vhd 2022/06/23.00:30:43 P.20131013
EN work/main 1655955264 FL C:/Users/Gabriel/Xilinx/Nexys/main.vhd \
PB ieee/std_logic_1164 1381692176 PB ieee/std_logic_arith 1381692177 \
PB ieee/STD_LOGIC_UNSIGNED 1381692179 PB ieee/NUMERIC_STD 1381692181
AR work/main/Behavioral 1655952454 \
FL C:/Users/Gabriel/Xilinx/Nexys/main.vhd EN work/main 1655952453 \
CP CONTBIN_4BIT
PB ieee/STD_LOGIC_UNSIGNED 1381692179
AR work/main/Behavioral 1655955265 \
FL C:/Users/Gabriel/Xilinx/Nexys/main.vhd EN work/main 1655955264 \
CP ULA_P379
FL C:/Users/Gabriel/Xilinx/Nexys/ULA_P379.vhd 2022/06/23.00:34:09 P.20131013
EN work/ULA_P379 1655955262 FL C:/Users/Gabriel/Xilinx/Nexys/ULA_P379.vhd \
PB ieee/std_logic_1164 1381692176 PB ieee/std_logic_arith 1381692177 \
PB ieee/STD_LOGIC_UNSIGNED 1381692179
AR work/ULA_P379/Behavioral 1655955263 \
FL C:/Users/Gabriel/Xilinx/Nexys/ULA_P379.vhd EN work/ULA_P379 1655955262

BIN
xst/work/sub00/vhpl00.vho
View File

Binary file not shown.

BIN
xst/work/sub00/vhpl01.vho
View File

Binary file not shown.

BIN
xst/work/sub00/vhpl06.vho Normal file
View File

Binary file not shown.

BIN
xst/work/sub00/vhpl07.vho Normal file
View File

Binary file not shown.