45 lines
1.1 KiB
VHDL
45 lines
1.1 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity ULA_P379 is
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Port ( ULA1 : in STD_LOGIC_VECTOR (3 downto 0);
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ULA2 : in STD_LOGIC_VECTOR (3 downto 0);
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OE : in STD_LOGIC;
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OPCODE: in STD_LOGIC_VECTOR (3 downto 0);
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CARRY : out STD_LOGIC;
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OUTPUT : out STD_LOGIC_VECTOR (3 downto 0));
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end ULA_P379;
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architecture Behavioral of ULA_P379 is
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signal OUTPUT_ALL: std_logic_vector (3 downto 0);
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begin
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process(OPCODE)
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begin
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case OPCODE is
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when "0000" => output_all <= ULA1 + ULA2;
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when "0001" => output_all <= ULA1 - ULA2;
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when "0010" => output_all <= ULA1 and ULA2;
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when "0011" => output_all <= ULA1 nand ULA2;
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when "0100" => output_all <= ULA1 or ULA2;
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when "0101" => output_all <= ULA1 xor ULA2;
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when "0111" => output_all <= not ULA1;
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when others => output_all <= "ZZZZ";
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end case;
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end process;
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process(OE)
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begin
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case OE is
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when '1' => OUTPUT <= output_all;
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when others => OUTPUT <= "ZZZZ";
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end case;
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end process;
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end Behavioral;
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