EloDigi/Bluetooth_VHDL
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

ULA

Browse Source
This commit is contained in:
Gabriel Lima
2023-04-26 11:57:02 -03:00
parent 7943706b2e
commit 5c2a575512
3 changed files with 62 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
Bluetooth_VHDL.xise
View File

@@ -20,10 +20,14 @@
</file>
<file xil_pn:name="main.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="display.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="ULA_P379.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="56"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
</files>
@@ -101,6 +105,7 @@
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>

44
ULA_P379.vhd Normal file
View File

@@ -0,0 +1,44 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ULA_P379 is
Port ( ULA1 : in STD_LOGIC_VECTOR (3 downto 0);
ULA2 : in STD_LOGIC_VECTOR (3 downto 0);
OE : in STD_LOGIC;
OPCODE: in STD_LOGIC_VECTOR (3 downto 0);
CARRY : out STD_LOGIC;
OUTPUT : out STD_LOGIC_VECTOR (3 downto 0));
end ULA_P379;
architecture Behavioral of ULA_P379 is
signal OUTPUT_ALL: std_logic_vector (3 downto 0);
begin
process(OPCODE)
begin
case OPCODE is
when "0000" => output_all <= ULA1 + ULA2;
when "0001" => output_all <= ULA1 - ULA2;
when "0010" => output_all <= ULA1 and ULA2;
when "0011" => output_all <= ULA1 nand ULA2;
when "0100" => output_all <= ULA1 or ULA2;
when "0101" => output_all <= ULA1 xor ULA2;
when "0111" => output_all <= not ULA1;
when others => output_all <= "ZZZZ";
end case;
end process;
process(OE)
begin
case OE is
when '1' => OUTPUT <= output_all;
when others => OUTPUT <= "ZZZZ";
end case;
end process;
end Behavioral;

14
main.vhdl
View File

@@ -43,7 +43,16 @@ end main;
architecture Behavioral of main is
component display port( NUM7, NUM6, NUM5, NUM4, NUM3, NUM2, NUM1, NUM0: in std_logic_vector(3 downto 0);
CLK: in std_logic; CS, Dout: out std_logic); end component;
CLK: in std_logic; CS, Dout: out std_logic); end component;
component ULA_P379
Port ( ULA1 : in STD_LOGIC_VECTOR (3 downto 0);
ULA2 : in STD_LOGIC_VECTOR (3 downto 0);
OE : in STD_LOGIC;
OPCODE: in STD_LOGIC_VECTOR (3 downto 0);
CARRY : out STD_LOGIC;
OUTPUT : out STD_LOGIC_VECTOR (3 downto 0));
end component;
signal num7,num6,num5,num4,num3,num2,num1,num0: std_logic_vector(3 downto 0);
signal clkdisp,cs,din: std_logic;
signal cont100k, contaux: std_logic_vector(23 downto 0);
@@ -117,7 +126,6 @@ begin
num4 <= num3;
num5 <= num4;
num6 <= num5;
num7 <= num6;
end if;
end if;
end if;
@@ -125,6 +133,8 @@ end process;
UDISP: display port map (num7 => num7,num6 => num6,num5 => num5,num4 => num4,num3 => num3,num2 => num2,
num1 => num1,num0 => num0,clk => clkdisp,cs => cs,dout => din);
ULA: ULA_P379 port map (ULA1 => NUM0, ULA2 => NUM1, OE => '1', OPCODE => NUM2, CARRY => GPIO(7), OUTPUT => NUM7);
clkdisp <= contaux(5); -- 421875 Hz
GPIO(0) <= clkdisp;