222 lines
7.1 KiB
VHDL
222 lines
7.1 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity textovhdl is
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Port ( CLK27MHz : in STD_LOGIC;
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LEDS : out STD_LOGIC_VECTOR (3 downto 0);
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BUT : in STD_LOGIC_VECTOR (3 downto 0);
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DIPSW : in STD_LOGIC_VECTOR (3 downto 0);
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GPIO : inout STD_LOGIC_VECTOR (7 downto 0)
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);
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end textovhdl;
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architecture comportamento of textovhdl is
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signal cont100k,contaux: std_logic_vector(23 downto 0);
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signal CLK100k,clk621ms,clk25k: std_logic;
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signal clkdisp,cs,din: std_logic;
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signal num7,num6,num5,num4,num3,num2,num1,num0: std_logic_vector(3 downto 0);
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signal microfone, toggleled, andcontzero: std_logic;
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signal EOmicro: std_logic_vector(4 downto 0);
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signal contmicro, ffmicro: std_logic_vector (19 downto 0);
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signal bLeds: std_logic_vector (3 downto 0);
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component display port( NUM7, NUM6, NUM5, NUM4, NUM3, NUM2, NUM1, NUM0: in std_logic_vector(3 downto 0);
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CLK: in std_logic;
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CS, Dout: out std_logic
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);
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end component;
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component CONTBCD_C port( CLK, CLR, UP, EN: in std_logic;
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ENOUT: out std_logic;
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Q: out std_logic_vector(3 downto 0)
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);
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end component;
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begin
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GPIO <= "ZZZZZZZZ";
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LEDS <= "ZZZZ";
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UC0: CONTBCD_C port map (CLK=>clk100k, CLR=>microfone, UP=>'1', EN=>(not contmicro(19)), ENout=>EOmicro(0), Q=>contmicro(3 downto 0));
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UC1: CONTBCD_C port map (CLK=>clk100k, CLR=>microfone, UP=>'1', EN=>EOmicro(0), ENout=>EOmicro(1), Q=>contmicro(7 downto 4));
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UC2: CONTBCD_C port map (CLK=>clk100k, CLR=>microfone, UP=>'1', EN=>EOmicro(1), ENout=>EOmicro(2), Q=>contmicro(11 downto 8));
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UC3: CONTBCD_C port map (CLK=>clk100k, CLR=>microfone, UP=>'1', EN=>EOmicro(2), ENout=>EOmicro(3), Q=>contmicro(15 downto 12));
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UC4: CONTBCD_C port map (CLK=>clk100k, CLR=>microfone, UP=>'1', EN=>EOmicro(3), ENout=>EOmicro(4), Q=>contmicro(19 downto 16));
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andcontzero <= '1' when contmicro="00000000000000000000" else '0';
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process (clk100k)
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begin
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if (clk100k'event and clk100k = '1') then
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ffmicro <= contmicro;
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toggleled <= andcontzero and (not ffmicro(18)) and ffmicro(17);
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end if;
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end process;
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process (toggleled)
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begin
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if (toggleled'event and toggleled = '1') then
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bLeds <= not bLeds;
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end if;
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end process;
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UDISP: display port map(num7=>num7, num6=>num6, num5=>num5, num4=>num4, num3=>num3, num2=>num2,
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num1=>num1, num0=>num0, clk=>clkdisp, cs=>cs, dout=>din);
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process(CLK27MHz)
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begin
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if(CLK27MHz'event and CLK27MHz = '1') then
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if (cont100k = "000000000000000000000000") then cont100k <= "000000000000000100001101";
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else cont100k <= cont100k-"000000000000000000000001";
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end if;
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contaux <= contaux + "000000000000000000000001";
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end if;
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end process;
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CLK100k <= cont100k(8);
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CLK25k <= contaux(9);
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clk621ms <= contaux(23); -- aprox. 1,6 Hz
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clkdisp <= contaux(5); -- 421875 Hz
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GPIO(0) <= clkdisp;
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GPIO(1) <= cs;
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GPIO(2) <= din;
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microfone <= GPIO(6);
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LEDS(3) <= microfone;
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LEDS(0) <= bLeds(0);
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LEDS(2) <= toggleled;
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LEDS(1) <= andcontzero;
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end comportamento;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity CONTBCD_C is
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port (CLK, CLR, UP, EN: in std_logic;
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ENOUT: out std_logic;
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Q: out std_logic_vector(3 downto 0)
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);
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end CONTBCD_C;
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architecture comportamento of CONTBCD_C is
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signal cont, proxcont: std_logic_vector (3 downto 0);
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begin
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Q <= cont;
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-- proxcont <= cont + "0001" when (EN+UP)="11" else
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-- cont - "0001" when (EN+UP)="10" else
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proxcont <= "0000" when (cont = "1001" and EN = '1' and UP = '1') else
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"1001" when (cont = "0000" and EN = '1' and UP = '0') else
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cont+(not UP & not UP & not UP & '1') when EN='1' else
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cont;
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ENOUT <= '1' when (EN = '1' and UP = '1' and cont = "1001") else
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'1' when (EN = '1' and UP = '0' and cont = "0000") else
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'0';
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process (CLK, CLR)
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begin
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if (CLR = '1') then
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cont <= "0000";
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elsif (CLK'event and CLK = '1') then
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cont <= proxcont;
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end if;
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end process;
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end comportamento;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity display is --Implementao do componente Display
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port( NUM7, NUM6, NUM5, NUM4, NUM3, NUM2, NUM1, NUM0: in std_logic_vector(3 downto 0);
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CLK: in std_logic;
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CS, Dout: out std_logic);
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end display;
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architecture comportamento of display is
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--Declarao e inicializao das variveis---------------------
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signal EN: std_logic_vector(8 downto 0):="000000000"; --ontador de 9 bits
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signal palavra, proxpalavra: std_logic_vector(15 downto 0):="0000000000000000"; --palavra na fila de bits e proxpalavra
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signal proxnum, proxdisplay: std_logic_vector(3 downto 0); --sinais de controle de algarismo e posicao do display
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signal Dis: std_logic_vector(2 downto 0); --Sinal da posicao da posicao a partir do contador de 9 bits
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signal proxfig,Fig: std_logic_vector(1 downto 0):="00"; --Sinal que pega o bit mais significativo e o sexto bit, para a logica de configuraao da palavra
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signal configur: std_logic:='0';
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---------------------------------------------------------------
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begin
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Dis<=EN(7 downto 5); --Posicao do display baseada no contador de 9 bits
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proxnum <= NUM1 when Dis="001" else
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NUM2 when Dis="010" else
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NUM3 when Dis="011" else
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NUM4 when Dis="100" else
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NUM5 when Dis="101" else
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NUM6 when Dis="110" else
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NUM7 when Dis="111" else
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NUM0;
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proxdisplay <= "0010" when Dis="001" else
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"0011" when Dis="010" else
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"0100" when Dis="011" else
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"0101" when Dis="100" else
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"0110" when Dis="101" else
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"0111" when Dis="110" else
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"1000" when Dis="111" else
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"0001";
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proxpalavra<= "0000110000000001" when (configur = '0' and Dis = "000") else -- modo normal
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"0000101111111111" when (configur = '0' and Dis = "001") else -- scan todos
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"0000101000001111" when (configur = '0' and Dis = "010") else -- intensidade
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"0000100111111111" when (configur = '0' and Dis = "011") else -- BCD
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--"1111111111111111" when (configur = '0' and Dis = "100") else
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--"0000001100000111";
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--"0000001101010101";
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--"0000"&"0001"&"01010111";
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"0000"&proxdisplay&"0000"&proxnum;
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process(CLK) --Processo que atualiza os valores do componente
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begin
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if(CLK'event and CLK='0') then -- As configuraes de proximo estado podem ser feitas a qualquer momento
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EN<=EN+"000000001";
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configur <= EN(8) or configur;
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if(EN(4) = '0') then --Coloca a proxpalavra na fila de bits no "final" do CS='1'
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palavra<=proxpalavra;
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else
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palavra<=palavra(14 downto 0)&'0'; --Coloca o proximo bit da fila no bus a cada clock quando CS='0'
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-- palavra<='0'&palavra(15 downto 1); --Coloca o proximo bit da fila no bus a cada clock quando CS='0'
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end if;
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end if;
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end process;
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Dout<=palavra(15); --Bus: sinal sendo passado para o display
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-- Dout<=palavra(0); --Bus: sinal sendo passado para o display
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CS <= not EN(4); --Sinal CS que controla a habilitao da escrita no display
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end comportamento;
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