353 lines
12 KiB
VHDL
353 lines
12 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity textovhdl is
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Port ( CLK27MHz : in STD_LOGIC;
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LEDS : out STD_LOGIC_VECTOR (3 downto 0);
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BUT : in STD_LOGIC_VECTOR (3 downto 0);
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DIPSW : in STD_LOGIC_VECTOR (3 downto 0);
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GPIO : inout STD_LOGIC_VECTOR (7 downto 0)
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);
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end textovhdl;
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architecture comportamento of textovhdl is
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signal cont100k,contaux: std_logic_vector(23 downto 0);
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signal CLK100k,clk621ms,clk25k: std_logic;
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signal clkdisp,cs,din: std_logic;
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signal num7,num6,num5,num4,num3,num2,num1,num0: std_logic_vector(3 downto 0);
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signal EO: std_logic_vector (7 downto 0);
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signal S_IR, CLR_cont_S: std_logic;
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signal prox_S, atual_S: std_logic_vector(1 downto 0);
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signal Q1ms, Q4ms, Q8ms: std_logic;
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signal proxshift, atualshift, codigo32: std_logic_vector(31 downto 0);
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signal SIshift, ENshift: std_logic;
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signal proxnum7: std_logic_vector( 3 downto 0);
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signal cont32TXIR: std_logic_vector(7 downto 0);
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signal conttimeTXIR: std_logic_vector(11 downto 0);
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signal clkcontbits, clrcontbits, contbitsigual32: std_logic;
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signal EOTX8: std_logic_vector (1 downto 0);
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signal EOTX12: std_logic_vector (2 downto 0);
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signal clr12bits, Q900, Q450, Q55, Q165: std_logic;
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signal loadshift, clkshift, Q0, outir, clk37915: std_logic;
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signal proxTX, atualTX: std_logic_vector(3 downto 0);
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signal proxshift32, atualshift32: std_logic_vector (31 downto 0);
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signal cont37915: std_logic_vector(23 downto 0);
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signal proxCLRCONTBITS, proxCLKCONTBITS, proxCLR12BITS, proxLOADSHIFT, proxCLKSHIFT, proxOUTIR: std_logic;
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component display port( NUM7, NUM6, NUM5, NUM4, NUM3, NUM2, NUM1, NUM0: in std_logic_vector(3 downto 0);
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CLK: in std_logic;
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CS, Dout: out std_logic
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);
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end component;
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component CONTBCD_C port( CLK, CLR, UP, EN: in std_logic;
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ENOUT: out std_logic;
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Q: out std_logic_vector(3 downto 0)
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);
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end component;
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begin
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GPIO <= "ZZZZZZZZ";
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LEDS <= "ZZZZ";
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--contador 8 bits de transmiss<73>o, conta at<61> 32
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UT0: CONTBCD_C port map(CLK => clkcontbits, CLR => clrcontbits, UP => '1', EN => '1', ENOUT => EOTX8(0), Q => cont32TXIR(3 downto 0));
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UT1: CONTBCD_C port map(CLK => clkcontbits, CLR => clrcontbits, UP => '1', EN => EOTX8(0), ENOUT => EOTX8(1), Q => cont32TXIR(7 downto 4));
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contbitsigual32 <= '1' when cont32TXIR="00110010" else '0';
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--contador de 12 bits transmiss<73>o, conta at<61> 900 x 10us
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UT2: CONTBCD_C port map(CLK => clk100k, CLR => clr12bits, UP => '1', EN => '1', ENOUT => EOTX12(0), Q => conttimeTXIR(3 downto 0));
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UT3: CONTBCD_C port map(CLK => clk100k, CLR => clr12bits, UP => '1', EN => EOTX12(0), ENOUT => EOTX12(1), Q => conttimeTXIR(7 downto 4));
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UT4: CONTBCD_C port map(CLK => clk100k, CLR => clr12bits, UP => '1', EN => EOTX12(1), ENOUT => EOTX12(2), Q => conttimeTXIR(11 downto 8));
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Q900 <= '0' when conttimeTXIR(11 downto 8)="1001" else '1';
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Q450 <= '0' when conttimeTXIR(11 downto 4)="01000101" else '1';
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Q55 <= '0' when conttimeTXIR(7 downto 0)="01010101" else '1';
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Q165 <= '0' when conttimeTXIR="000101100101" else '1';
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--shift register
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proxshift32 <= codigo32 when loadshift='1' else '0'&atualshift32(31 downto 1);
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Q0 <= atualshift32(0);
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process (clkshift)
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begin
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if (clkshift'event and clkshift='1') then
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atualshift32 <=proxshift32;
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end if;
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end process;
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--gera 37915Hz
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process(CLK27MHz)
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begin
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if(CLK27MHz'event and CLK27MHz = '1') then
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if (cont37915 = "000000000000000000000000") then cont37915 <= "000000000000000101100011";
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else cont37915 <= cont37915-"000000000000000000000001";
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end if;
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end if;
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end process;
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process(cont37915(8))
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begin
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if(cont37915(8)'event and cont37915(8) = '1') then
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clk37915 <= not clk37915;
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end if;
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end process;
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proxTX <= "000"&BUT(0) when atualTX="0000" else
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"00"&(not BUT(0))&'1' when atualTX="0001" else
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"001"&Q900 when atualTX="0011" else
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"0110" when atualTX="0010" else
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"011"&(not Q450) when atualTX="0110" else
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"1111" when atualTX="0111" else
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"111"&Q55 when atualTX="1111" else
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"1010" when atualTX="1110" else
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"1010" when (atualTX="1010" and Q0='1' and Q165='0') else
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"1010" when (atualTX="1010" and Q0='0' and Q55='0') else
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"1011" when atualTX="1010" else
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contbitsigual32&(not contbitsigual32)&(not contbitsigual32)&'1' when atualTX="1011" else
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"100"&Q55 when atualTX="1001" else
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"0000";
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proxCLRCONTBITS <= '1' when proxTX="0110" else '0';
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proxCLKCONTBITS <= '1' when proxTX="1010" else '0';
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proxCLR12BITS <= '1' when proxTX="0001" else
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'1' when proxTX="0010" else
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'1' when proxTX="0111" else
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'1' when proxTX="1110" else
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'1' when proxTX="1011" else '0';
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proxLOADSHIFT <= '1' when proxTX="0001" else
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'1' when proxTX="0011" else '0';
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proxCLKSHIFT <= '1' when proxTX="0011" else
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'1' when proxTX="1010" else '0';
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proxOUTIR <= '1' when proxTX="0011" else
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'1' when proxTX="0111" else
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'1' when proxTX="1111" else
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'1' when proxTX="1011" else
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'1' when proxTX="1001" else '0';
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UDISP: display port map(num7=>num7, num6=>num6, num5=>num5, num4=>num4, num3=>num3, num2=>num2,
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num1=>num1, num0=>num0, clk=>clkdisp, cs=>cs, dout=>din);
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CLR_cont_S <= atual_S(1) and atual_S(0);
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prox_S <= '0'&(not S_IR) when atual_S="00" else
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"11" when atual_S="01" else
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"10" when atual_S="11" else
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(not S_IR & '0');
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proxshift <= atualshift when ENshift = '0' else
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SIshift & atualshift (31 downto 1);
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process (S_IR)
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begin
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if (S_IR'event and S_IR='0') then
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atualshift <= proxshift;
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end if;
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end process;
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process (Q8ms)
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begin
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if (Q8ms'event and Q8ms='1') then
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codigo32 <= atualshift;
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end if;
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end process;
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process (CLK100k)
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begin
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if (CLK100k'event and CLK100k='1') then
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atual_S <= prox_S;
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num7 <= proxnum7;
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atualTX <= proxTX;
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clrcontbits <= proxCLRCONTBITS;
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clkcontbits <= proxCLKCONTBITS;
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clr12bits <= proxCLR12BITS;
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loadshift <= proxLOADSHIFT;
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clkSHIFT <= proxCLKSHIFT;
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outIR <= proxOUTIR;
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end if;
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end process;
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UC0: CONTBCD_C port map(CLK => CLK100k, CLR => CLR_cont_S, UP => '1', EN => (S_IR and not Q8ms), ENOUT => EO(0), Q => num0);
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UC1: CONTBCD_C port map(CLK => CLK100k, CLR => CLR_cont_S, UP => '1', EN => EO(0), ENOUT => EO(1), Q => num1);
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UC2: CONTBCD_C port map(CLK => CLK100k, CLR => CLR_cont_S, UP => '1', EN => EO(1), ENOUT => EO(2), Q => num2);
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Q1ms <= num2(0);
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Q4ms <= num2(2);
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Q8ms <= num2(3);
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ENshift <= not Q8ms and not Q4ms;
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SIshift <= Q1ms;
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proxnum7 <= "0000" when codigo32(31 downto 24)="11101001" else -- 0 = E9
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"0001" when codigo32(31 downto 24)="11110011" else -- 1 = F3
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"0010" when codigo32(31 downto 24)="11100111" else -- 2 = E7
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"0011" when codigo32(31 downto 24)="10100001" else -- 3 = A1
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"0100" when codigo32(31 downto 24)="11110111" else -- 4 = F7
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"0101" when codigo32(31 downto 24)="11100011" else -- 5 = E3
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"0110" when codigo32(31 downto 24)="10100101" else -- 6 = A5
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"0111" when codigo32(31 downto 24)="10111101" else -- 7 = BD
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"1000" when codigo32(31 downto 24)="10101101" else -- 8 = AD
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"1001" when codigo32(31 downto 24)="10110101" else -- 9 = B5
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num7;
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process(CLK27MHz)
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begin
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if(CLK27MHz'event and CLK27MHz = '1') then
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if (cont100k = "000000000000000000000000") then cont100k <= "000000000000000100001101";
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else cont100k <= cont100k-"000000000000000000000001";
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end if;
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contaux <= contaux + "000000000000000000000001";
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end if;
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end process;
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CLK100k <= cont100k(8);
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CLK25k <= contaux(9);
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clk621ms <= contaux(23); -- aprox. 1,6 Hz
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clkdisp <= contaux(5); -- 421875 Hz
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GPIO(0) <= clkdisp;
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GPIO(1) <= cs;
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GPIO(2) <= din;
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S_IR <= GPIO(4);
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LEDS <= atualTX;
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num6 <= atualTX;
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num5 <= proxTX;
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GPIO(5) <= CLK37915 and OUTIR;
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end comportamento;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity CONTBCD_C is
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port (CLK, CLR, UP, EN: in std_logic;
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ENOUT: out std_logic;
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Q: out std_logic_vector(3 downto 0)
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);
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end CONTBCD_C;
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architecture comportamento of CONTBCD_C is
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signal cont, proxcont: std_logic_vector (3 downto 0);
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begin
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Q <= cont;
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-- proxcont <= cont + "0001" when (EN+UP)="11" else
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-- cont - "0001" when (EN+UP)="10" else
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proxcont <= "0000" when (cont = "1001" and EN = '1' and UP = '1') else
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"1001" when (cont = "0000" and EN = '1' and UP = '0') else
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cont+(not UP & not UP & not UP & '1') when EN='1' else
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cont;
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ENOUT <= '1' when (EN = '1' and UP = '1' and cont = "1001") else
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'1' when (EN = '1' and UP = '0' and cont = "0000") else
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'0';
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process (CLK, CLR)
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begin
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if (CLR = '1') then
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cont <= "0000";
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elsif (CLK'event and CLK = '1') then
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cont <= proxcont;
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end if;
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end process;
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end comportamento;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity display is --Implementao do componente Display
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port( NUM7, NUM6, NUM5, NUM4, NUM3, NUM2, NUM1, NUM0: in std_logic_vector(3 downto 0);
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CLK: in std_logic;
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CS, Dout: out std_logic);
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end display;
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architecture comportamento of display is
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--Declarao e inicializao das variveis---------------------
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signal EN: std_logic_vector(8 downto 0):="000000000"; --ontador de 9 bits
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signal palavra, proxpalavra: std_logic_vector(15 downto 0):="0000000000000000"; --palavra na fila de bits e proxpalavra
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signal proxnum, proxdisplay: std_logic_vector(3 downto 0); --sinais de controle de algarismo e posicao do display
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signal Dis: std_logic_vector(2 downto 0); --Sinal da posicao da posicao a partir do contador de 9 bits
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signal proxfig,Fig: std_logic_vector(1 downto 0):="00"; --Sinal que pega o bit mais significativo e o sexto bit, para a logica de configuraao da palavra
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signal configur: std_logic:='0';
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---------------------------------------------------------------
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begin
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Dis<=EN(7 downto 5); --Posicao do display baseada no contador de 9 bits
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proxnum <= NUM1 when Dis="001" else
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NUM2 when Dis="010" else
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NUM3 when Dis="011" else
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NUM4 when Dis="100" else
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NUM5 when Dis="101" else
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NUM6 when Dis="110" else
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NUM7 when Dis="111" else
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NUM0;
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proxdisplay <= "0010" when Dis="001" else
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"0011" when Dis="010" else
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"0100" when Dis="011" else
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"0101" when Dis="100" else
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"0110" when Dis="101" else
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"0111" when Dis="110" else
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"1000" when Dis="111" else
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"0001";
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proxpalavra<= "0000110000000001" when (configur = '0' and Dis = "000") else -- modo normal
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"0000101111111111" when (configur = '0' and Dis = "001") else -- scan todos
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"0000101000001111" when (configur = '0' and Dis = "010") else -- intensidade
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"0000100111111111" when (configur = '0' and Dis = "011") else -- BCD
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--"1111111111111111" when (configur = '0' and Dis = "100") else
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--"0000001100000111";
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--"0000001101010101";
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--"0000"&"0001"&"01010111";
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"0000"&proxdisplay&"0000"&proxnum;
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process(CLK) --Processo que atualiza os valores do componente
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begin
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if(CLK'event and CLK='0') then -- As configuraes de proximo estado podem ser feitas a qualquer momento
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EN<=EN+"000000001";
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configur <= EN(8) or configur;
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if(EN(4) = '0') then --Coloca a proxpalavra na fila de bits no "final" do CS='1'
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palavra<=proxpalavra;
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else
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palavra<=palavra(14 downto 0)&'0'; --Coloca o proximo bit da fila no bus a cada clock quando CS='0'
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-- palavra<='0'&palavra(15 downto 1); --Coloca o proximo bit da fila no bus a cada clock quando CS='0'
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end if;
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end if;
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end process;
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Dout<=palavra(15); --Bus: sinal sendo passado para o display
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-- Dout<=palavra(0); --Bus: sinal sendo passado para o display
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CS <= not EN(4); --Sinal CS que controla a habilitao da escrita no display
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end comportamento;
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