43 lines
3.1 KiB
XML
43 lines
3.1 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<!-- IMPORTANT: This is an internal file that has been generated
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by the Xilinx ISE software. Any direct editing or
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changes made to this file may result in unpredictable
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behavior or data corruption. It is strongly advised that
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users do not edit the contents of this file. -->
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<messages>
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<msg type="info" file="LIT" num="243" delta="old" >Logical network <arg fmt="%s" index="1">BUT<3>_IBUF</arg> has no load.
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</msg>
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<msg type="info" file="LIT" num="395" delta="old" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">9</arg> more times for the following (max. 5 shown):
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<arg fmt="%s" index="3">BUT<2>_IBUF,
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BUT<1>_IBUF,
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DIPSW<3>_IBUF,
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DIPSW<2>_IBUF,
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DIPSW<1>_IBUF</arg>
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To see the details of these <arg fmt="%s" index="4">info</arg> messages, please use the -detail switch.
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</msg>
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<msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set.
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</msg>
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<msg type="info" file="LIT" num="244" delta="old" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
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</msg>
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<msg type="info" file="Pack" num="1716" delta="old" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)
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</msg>
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<msg type="info" file="Pack" num="1720" delta="old" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts)
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</msg>
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<msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp).
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</msg>
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<msg type="warning" file="Place" num="1109" delta="old" >A clock IOB / BUFGMUX clock component pair have been found that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock IOB component <<arg fmt="%s" index="1">GPIO<4></arg>> is placed at site <<arg fmt="%s" index="2">F15</arg>>. The corresponding BUFG component <<arg fmt="%s" index="3">GPIO_4_IBUF_BUFG</arg>> is placed at site <<arg fmt="%s" index="4">BUFGMUX_X2Y11</arg>>. There is only a select set of IOBs that can use the fast path to the Clocker buffer, and they are not being used. You may want to analyze why this problem exists and correct it. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <<arg fmt="%s" index="5">GPIO<4>.PAD</arg>> allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
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</msg>
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<msg type="info" file="Pack" num="1650" delta="old" >Map created a placed design.
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</msg>
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</messages>
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