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Gabriel Lima
2022-06-10 12:48:36 -03:00
parent 5446987391
commit 24abb7f75e
59 changed files with 9660 additions and 71 deletions
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webtalk_pn.xml Normal file
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<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Fri Jun 10 12:44:48 2022">
<section name="Project Information" visible="false">
<property name="ProjectID" value="870CEC42C91B420AB3E8346AAC208971" type="project"/>
<property name="ProjectIteration" value="6" type="project"/>
<property name="ProjectFile" value="C:/Users/Gabriel/Xilinx/Aula20220603/Aula20220603.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2022-06-03T11:32:48" type="project"/>
</section>
<section name="Project Statistics" visible="true">
<property name="PROP_Board" value="Spartan-6 SP601 Evaluation Platform" type="process"/>
<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
<property name="PROP_FitterReportFormat" value="HTML" type="process"/>
<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
<property name="PROP_SynthTopFile" value="changed" type="process"/>
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
<property name="PROP_UseSmartGuide" value="false" type="design"/>
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2022-06-03T11:32:48" type="design"/>
<property name="PROP_intWbtProjectID" value="870CEC42C91B420AB3E8346AAC208971" type="design"/>
<property name="PROP_intWbtProjectIteration" value="6" type="process"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_xilxBitgStart_IntDone" value="true" type="process"/>
<property name="PROP_AutoTop" value="true" type="design"/>
<property name="PROP_DevFamily" value="Spartan6" type="design"/>
<property name="PROP_DevDevice" value="xc6slx16" type="design"/>
<property name="PROP_DevFamilyPMName" value="spartan6" type="design"/>
<property name="PROP_DevPackage" value="csg324" type="design"/>
<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
<property name="PROP_DevSpeed" value="-2" type="design"/>
<property name="PROP_PreferredLanguage" value="VHDL" type="design"/>
<property name="FILE_UCF" value="1" type="source"/>
<property name="FILE_VHDL" value="1" type="source"/>
</section>
</application>
</document>