167 lines
7.5 KiB
Plaintext
167 lines
7.5 KiB
Plaintext
Release 14.7 Map P.20131013 (nt64)
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Xilinx Map Application Log File for Design 'textovhdl'
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Design Information
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------------------
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Command Line : map -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol
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high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
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-pr off -lc off -power off -o textovhdl_map.ncd textovhdl.ngd textovhdl.pcf
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Target Device : xc6slx16
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Target Package : csg324
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Target Speed : -2
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Mapper Version : spartan6 -- $Revision: 1.55 $
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Mapped Date : Wed Jun 01 13:02:23 2022
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Mapping design into LUTs...
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Running directed packing...
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Running delay-based LUT packing...
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Updating timing models...
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INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
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(.mrp).
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Running timing-driven placement...
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Total REAL time at the beginning of Placer: 5 secs
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Total CPU time at the beginning of Placer: 5 secs
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Phase 1.1 Initial Placement Analysis
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Phase 1.1 Initial Placement Analysis (Checksum:996cd345) REAL time: 5 secs
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Phase 2.7 Design Feasibility Check
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Phase 2.7 Design Feasibility Check (Checksum:996cd345) REAL time: 5 secs
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Phase 3.31 Local Placement Optimization
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Phase 3.31 Local Placement Optimization (Checksum:996cd345) REAL time: 5 secs
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Phase 4.2 Initial Placement for Architecture Specific Features
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.
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WARNING:Place:1109 - A clock IOB / BUFGMUX clock component pair have been found
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that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
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IOB component <GPIO<4>> is placed at site <F15>. The corresponding BUFG
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component <GPIO_4_IBUF_BUFG> is placed at site <BUFGMUX_X3Y6>. There is only
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a select set of IOBs that can use the fast path to the Clocker buffer, and
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they are not being used. You may want to analyze why this problem exists and
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correct it. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE
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constraint was applied on COMP.PIN <GPIO<4>.PAD> allowing your design to
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continue. This constraint disables all clock placer rules related to the
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specified COMP.PIN. The use of this override is highly discouraged as it may
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lead to very poor timing results. It is recommended that this error condition
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be corrected in the design.
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Phase 4.2 Initial Placement for Architecture Specific Features
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(Checksum:e4d73fc) REAL time: 6 secs
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Phase 5.36 Local Placement Optimization
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Phase 5.36 Local Placement Optimization (Checksum:e4d73fc) REAL time: 6 secs
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Phase 6.30 Global Clock Region Assignment
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Phase 6.30 Global Clock Region Assignment (Checksum:e4d73fc) REAL time: 6 secs
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Phase 7.3 Local Placement Optimization
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Phase 7.3 Local Placement Optimization (Checksum:e4d73fc) REAL time: 6 secs
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Phase 8.5 Local Placement Optimization
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Phase 8.5 Local Placement Optimization (Checksum:e4d73fc) REAL time: 6 secs
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Phase 9.8 Global Placement
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......
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......
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Phase 9.8 Global Placement (Checksum:65128a07) REAL time: 6 secs
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Phase 10.5 Local Placement Optimization
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Phase 10.5 Local Placement Optimization (Checksum:65128a07) REAL time: 6 secs
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Phase 11.18 Placement Optimization
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Phase 11.18 Placement Optimization (Checksum:184167b7) REAL time: 7 secs
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Phase 12.5 Local Placement Optimization
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Phase 12.5 Local Placement Optimization (Checksum:184167b7) REAL time: 7 secs
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Phase 13.34 Placement Validation
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Phase 13.34 Placement Validation (Checksum:184167b7) REAL time: 7 secs
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Total REAL time to Placer completion: 7 secs
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Total CPU time to Placer completion: 6 secs
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Running post-placement packing...
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Writing output files...
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Design Summary
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--------------
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Design Summary:
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Number of errors: 0
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Number of warnings: 1
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Slice Logic Utilization:
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Number of Slice Registers: 89 out of 18,224 1%
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Number used as Flip Flops: 89
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Number used as Latches: 0
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Number used as Latch-thrus: 0
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Number used as AND/OR logics: 0
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Number of Slice LUTs: 113 out of 9,112 1%
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Number used as logic: 103 out of 9,112 1%
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Number using O6 output only: 57
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Number using O5 output only: 12
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Number using O5 and O6: 34
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Number used as ROM: 0
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Number used as Memory: 0 out of 2,176 0%
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Number used exclusively as route-thrus: 10
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Number with same-slice register load: 8
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Number with same-slice carry load: 2
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Number with other load: 0
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Slice Logic Distribution:
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Number of occupied Slices: 34 out of 2,278 1%
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Number of MUXCYs used: 44 out of 4,556 1%
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Number of LUT Flip Flop pairs used: 116
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Number with an unused Flip Flop: 40 out of 116 34%
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Number with an unused LUT: 3 out of 116 2%
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Number of fully used LUT-FF pairs: 73 out of 116 62%
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Number of unique control sets: 9
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Number of slice register sites lost
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to control set restrictions: 31 out of 18,224 1%
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A LUT Flip Flop pair for this architecture represents one LUT paired with
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one Flip Flop within a slice. A control set is a unique combination of
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clock, reset, set, and enable signals for a registered element.
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The Slice Logic Distribution report is not meaningful if the design is
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over-mapped for a non-slice resource or if Placement fails.
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IO Utilization:
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Number of bonded IOBs: 21 out of 232 9%
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Number of LOCed IOBs: 21 out of 21 100%
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IOB Flip Flops: 3
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Specific Feature Utilization:
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Number of RAMB16BWERs: 0 out of 32 0%
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Number of RAMB8BWERs: 0 out of 64 0%
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Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
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Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
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Number of BUFG/BUFGMUXs: 3 out of 16 18%
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Number used as BUFGs: 3
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Number used as BUFGMUX: 0
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Number of DCM/DCM_CLKGENs: 0 out of 4 0%
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Number of ILOGIC2/ISERDES2s: 0 out of 248 0%
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Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 248 0%
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Number of OLOGIC2/OSERDES2s: 3 out of 248 1%
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Number used as OLOGIC2s: 3
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Number used as OSERDES2s: 0
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Number of BSCANs: 0 out of 4 0%
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Number of BUFHs: 0 out of 128 0%
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Number of BUFPLLs: 0 out of 8 0%
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Number of BUFPLL_MCBs: 0 out of 4 0%
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Number of DSP48A1s: 0 out of 32 0%
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Number of ICAPs: 0 out of 1 0%
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Number of MCBs: 0 out of 2 0%
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Number of PCILOGICSEs: 0 out of 2 0%
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Number of PLL_ADVs: 0 out of 2 0%
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Number of PMVs: 0 out of 1 0%
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Number of STARTUPs: 0 out of 1 0%
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Number of SUSPEND_SYNCs: 0 out of 1 0%
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Average Fanout of Non-Clock Nets: 2.66
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Peak Memory Usage: 349 MB
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Total REAL time to MAP completion: 7 secs
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Total CPU time to MAP completion: 7 secs
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Mapping completed.
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See MAP report file "textovhdl_map.mrp" for details.
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