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This commit is contained in:
Gabriel Lima
2022-06-01 11:23:59 -03:00
commit 736f3773e5
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38
Aula20220601.xise Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
</files>
<properties>
<property xil_pn:name="Project Description" xil_pn:value=""/>
<property xil_pn:name="Working Directory" xil_pn:value="C:/Users/Gabriel/Xilinx/Aula20220601"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values"/>
<property xil_pn:name="Manual Compile Order" xil_pn:value="false"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false"/>
</properties>
<bindings/>
<libraries/>
</project>

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_xmsgs/pn_parser.xmsgs Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages>
</messages>

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restricoes.ucf Normal file
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NET "GPIO[4]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "GPIO[6]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "CLK27MHz" LOC = V10 ;
NET "GPIO[0]" LOC = N17;
NET "GPIO[1]" LOC = M18;
NET "GPIO[2]" LOC = A3;
NET "GPIO[3]" LOC = L15;
NET "GPIO[4]" LOC = F15;
NET "GPIO[5]" LOC = B4;
NET "GPIO[6]" LOC = F13;
NET "GPIO[7]" LOC = P12;
NET "BUT[0]" LOC = P4;
NET "BUT[1]" LOC = F6;
NET "BUT[2]" LOC = E4;
NET "BUT[3]" LOC = F5;
NET "DIPSW[0]" LOC = D14;
NET "DIPSW[1]" LOC = E12;
NET "DIPSW[2]" LOC = F12;
NET "DIPSW[3]" LOC = V13;
NET "LEDS[0]" LOC = E13;
NET "LEDS[1]" LOC = C14;
NET "LEDS[2]" LOC = C4;
NET "LEDS[3]" LOC = A4;

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textovhdl.vhd Normal file
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity textovhdl is
Port ( CLK27MHz : in STD_LOGIC;
LEDS : out STD_LOGIC_VECTOR (3 downto 0);
BUT : in STD_LOGIC_VECTOR (3 downto 0);
DIPSW : in STD_LOGIC_VECTOR (3 downto 0);
GPIO : inout STD_LOGIC_VECTOR (7 downto 0)
);
end textovhdl;
architecture comportamento of textovhdl is
signal cont100k,contaux: std_logic_vector(23 downto 0);
signal CLK100k,clk621ms,clk25k,clksen: std_logic;
signal clkdisp,cs,din: std_logic;
signal num7,num6,num5,num4,num3,num2,num1,num0: std_logic_vector(3 downto 0);
signal num13,num12,num11,num10: std_logic_vector(3 downto 0);
signal EO: std_logic_vector (7 downto 0);
signal estadoprox, estadoatual: std_logic;
signal echo, trig: std_logic;
component display port( NUM7, NUM6, NUM5, NUM4, NUM3, NUM2, NUM1, NUM0: in std_logic_vector(3 downto 0);
CLK: in std_logic;
CS, Dout: out std_logic
);
end component;
component CONTBCD_C port( CLK, CLR, UP, EN: in std_logic;
ENOUT: out std_logic;
Q: out std_logic_vector(3 downto 0)
);
end component;
begin
GPIO <= "ZZZZZZZZ";
LEDS <= "ZZZZ";
UDISP: display port map(num7=>num7, num6=>num6, num5=>num5, num4=>num4, num3=>num3, num2=>num2,
num1=>num1, num0=>num0, clk=>clkdisp, cs=>cs, dout=>din);
UC0: contbcd_c port map(CLK=>clksen, CLR=>not estadoatual, UP=> '1', EN=>'1', ENOUT=>EO(0), Q=>num0);
UC1: contbcd_c port map(CLK=>clksen, CLR=>not estadoatual, UP=> '1', EN=>EO(0), ENOUT=>EO(1), Q=>num1);
UC2: contbcd_c port map(CLK=>clksen, CLR=>not estadoatual, UP=> '1', EN=>EO(1), ENOUT=>EO(2), Q=>num2);
UC3: contbcd_c port map(CLK=>clksen, CLR=>not estadoatual, UP=> '1', EN=>EO(2), ENOUT=>EO(3), Q=>num3);
UC4: contbcd_c port map(CLK=>clk100k, CLR=>not estadoatual, UP=> '1', EN=>echo, ENOUT=>EO(4), Q=>num10);
UC5: contbcd_c port map(CLK=>clk100k, CLR=>not estadoatual, UP=> '1', EN=>EO(4), ENOUT=>EO(5), Q=>num11);
UC6: contbcd_c port map(CLK=>clk100k, CLR=>not estadoatual, UP=> '1', EN=>EO(5), ENOUT=>EO(6), Q=>num12);
UC7: contbcd_c port map(CLK=>clk100k, CLR=>not estadoatual, UP=> '1', EN=>EO(6), ENOUT=>EO(7), Q=>num13);
trig <= not estadoatual;
estadoprox <= '1' when estadoatual = '0' else not num3(3);
process(echo)
begin
if (echo'event and echo = '0') then
num4 <= num10;
num5 <= num11;
num6 <= num12;
num7 <= num13;
end if;
end process;
process(clk100k)
begin
if (clk100k'event and clk100k = '1') then
estadoatual <= estadoprox;
end if;
end process;
process(CLK27MHz)
begin
if(CLK27MHz'event and CLK27MHz = '1') then
if (cont100k = "000000000000000000000000") then cont100k <= "000000000000000100001101";
else cont100k <= cont100k-"000000000000000000000001";
end if;
contaux <= contaux + "000000000000000000000001";
end if;
end process;
CLK100k <= cont100k(8);
CLK25k <= contaux(9);
clksen <= contaux(7);
clk621ms <= contaux(23); -- aprox. 1,6 Hz
clkdisp <= contaux(5); -- 421875 Hz
GPIO(0) <= clkdisp;
GPIO(1) <= cs;
GPIO(2) <= din;
GPIO(3) <= clkdisp;
GPIO(4) <= cs;
GPIO(5) <= din;
echo <= GPIO(6);
GPIO(7) <= trig;
end comportamento;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CONTBCD_C is
port (CLK, CLR, UP, EN: in std_logic;
ENOUT: out std_logic;
Q: out std_logic_vector(3 downto 0)
);
end CONTBCD_C;
architecture comportamento of CONTBCD_C is
signal cont, proxcont: std_logic_vector (3 downto 0);
begin
Q <= cont;
-- proxcont <= cont + "0001" when (EN+UP)="11" else
-- cont - "0001" when (EN+UP)="10" else
proxcont <= "0000" when (cont = "1001" and EN = '1' and UP = '1') else
"1001" when (cont = "0000" and EN = '1' and UP = '0') else
cont+(not UP & not UP & not UP & '1') when EN='1' else
cont;
ENOUT <= '1' when (EN = '1' and UP = '1' and cont = "1001") else
'1' when (EN = '1' and UP = '0' and cont = "0000") else
'0';
process (CLK, CLR)
begin
if (CLR = '1') then
cont <= "0000";
elsif (CLK'event and CLK = '1') then
cont <= proxcont;
end if;
end process;
end comportamento;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity display is --Implementao do componente Display
port( NUM7, NUM6, NUM5, NUM4, NUM3, NUM2, NUM1, NUM0: in std_logic_vector(3 downto 0);
CLK: in std_logic;
CS, Dout: out std_logic);
end display;
architecture comportamento of display is
--Declarao e inicializao das variveis---------------------
signal EN: std_logic_vector(8 downto 0):="000000000"; --ontador de 9 bits
signal palavra, proxpalavra: std_logic_vector(15 downto 0):="0000000000000000"; --palavra na fila de bits e proxpalavra
signal proxnum, proxdisplay: std_logic_vector(3 downto 0); --sinais de controle de algarismo e posicao do display
signal Dis: std_logic_vector(2 downto 0); --Sinal da posicao da posicao a partir do contador de 9 bits
signal proxfig,Fig: std_logic_vector(1 downto 0):="00"; --Sinal que pega o bit mais significativo e o sexto bit, para a logica de configuraao da palavra
signal configur: std_logic:='0';
---------------------------------------------------------------
begin
Dis<=EN(7 downto 5); --Posicao do display baseada no contador de 9 bits
proxnum <= NUM1 when Dis="001" else
NUM2 when Dis="010" else
NUM3 when Dis="011" else
NUM4 when Dis="100" else
NUM5 when Dis="101" else
NUM6 when Dis="110" else
NUM7 when Dis="111" else
NUM0;
proxdisplay <= "0010" when Dis="001" else
"0011" when Dis="010" else
"0100" when Dis="011" else
"0101" when Dis="100" else
"0110" when Dis="101" else
"0111" when Dis="110" else
"1000" when Dis="111" else
"0001";
proxpalavra<= "0000110000000001" when (configur = '0' and Dis = "000") else -- modo normal
"0000101111111111" when (configur = '0' and Dis = "001") else -- scan todos
"0000101000001111" when (configur = '0' and Dis = "010") else -- intensidade
"0000100111111111" when (configur = '0' and Dis = "011") else -- BCD
--"1111111111111111" when (configur = '0' and Dis = "100") else
--"0000001100000111";
--"0000001101010101";
--"0000"&"0001"&"01010111";
"0000"&proxdisplay&"0000"&proxnum;
process(CLK) --Processo que atualiza os valores do componente
begin
if(CLK'event and CLK='0') then -- As configuraes de proximo estado podem ser feitas a qualquer momento
EN<=EN+"000000001";
configur <= EN(8) or configur;
if(EN(4) = '0') then --Coloca a proxpalavra na fila de bits no "final" do CS='1'
palavra<=proxpalavra;
else
palavra<=palavra(14 downto 0)&'0'; --Coloca o proximo bit da fila no bus a cada clock quando CS='0'
-- palavra<='0'&palavra(15 downto 1); --Coloca o proximo bit da fila no bus a cada clock quando CS='0'
end if;
end if;
end process;
Dout<=palavra(15); --Bus: sinal sendo passado para o display
-- Dout<=palavra(0); --Bus: sinal sendo passado para o display
CS <= not EN(4); --Sinal CS que controla a habilitao da escrita no display
end comportamento;