39 lines
1.7 KiB
XML
39 lines
1.7 KiB
XML
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
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<header>
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<!-- ISE source project file created by Project Navigator. -->
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<!-- -->
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<!-- This file contains project source information including a list of -->
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<!-- project source files, project and process properties. This file, -->
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<!-- along with the project source files, is sufficient to open and -->
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<!-- implement in ISE Project Navigator. -->
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<!-- -->
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<!-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. -->
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</header>
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<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
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<files>
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</files>
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<properties>
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<property xil_pn:name="Project Description" xil_pn:value=""/>
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<property xil_pn:name="Working Directory" xil_pn:value="C:/Users/Gabriel/Xilinx/Aula20220601"/>
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<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL"/>
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<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)"/>
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<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)"/>
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<property xil_pn:name="Preferred Language" xil_pn:value="VHDL"/>
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<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values"/>
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<property xil_pn:name="Manual Compile Order" xil_pn:value="false"/>
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<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93"/>
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<property xil_pn:name="Enable Message Filtering" xil_pn:value="false"/>
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</properties>
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<bindings/>
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<libraries/>
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</project>
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