Thomas Petazzoni 1a21705e73 arch/Config.in.x86: westmere and silvermont were added in gcc 4.9 ...

These were added in gcc commit
d3c11974032e21121a051d423a1d71097edf752f ("Use proper Intel processor
names for -march=/-mtune=") which was merged in gcc 4.9.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>

2022-01-25 08:41:10 +01:00

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arch.mk

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arch.mk.arc

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arch.mk.csky

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arch.mk.riscv

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arch.mk.xtensa

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Config.in

arch/config: Make RISC-V 64-bits MMU optional

2021-10-27 14:39:01 +02:00

Config.in.arc

ARC: Add support for generic HS48 processor

2021-01-16 09:58:26 +01:00

Config.in.arm

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Config.in.csky

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Config.in.m68k

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Config.in.microblaze

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Config.in.mips

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Config.in.nds32

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Config.in.nios2

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Config.in.or1k

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Config.in.powerpc

arch/Config.in.powerpc: Drop PPC601 support

2020-12-15 19:30:03 +01:00

Config.in.riscv

arch/config: Make RISC-V 64-bits MMU optional

2021-10-27 14:39:01 +02:00

Config.in.s390x

arch/Config.in.s390x: drop redundant depends on BR2_s390x

2020-09-30 21:36:07 +02:00

Config.in.sh

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Config.in.sparc

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Config.in.x86

arch/Config.in.x86: westmere and silvermont were added in gcc 4.9

2022-01-25 08:41:10 +01:00

Config.in.xtensa

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