Projetos/SX1280_Dev
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Gabriel Lima
2022-11-14 00:40:26 -05:00
commit 5c34a94ec9
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Hardware/SX1280_Module/Project Outputs for SX1280_Module/Design Rule Check - SX1280_Module.drc Normal file
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Protel Design System Design Rule Check
PCB File : C:\Users\Gabriel\OneDrive\Documentos\TrabalhosPessoais\Projetos\SX1280_Dev\Hardware\SX1280_Module\SX1280_Module.PcbDoc
Date : 2022-11-14
Time : 00:31:54
Processing Rule : Clearance Constraint (Gap=0.254mm) (All),(All)
Rule Violations :0
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0
Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0
Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
Rule Violations :0
Processing Rule : Width Constraint (Min=0.3mm) (Max=1mm) (Preferred=0.8mm) (All)
Rule Violations :0
Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
Rule Violations :0
Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)
Rule Violations :0
Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All)
Rule Violations :0
Processing Rule : Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)
Rule Violations :0
Processing Rule : Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
Rule Violations :0
Processing Rule : Silk to Silk (Clearance=0.254mm) (All),(All)
Rule Violations :0
Processing Rule : Net Antennae (Tolerance=0mm) (All)
Rule Violations :0
Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0
Violations Detected : 0
Waived Violations : 0
Time Elapsed : 00:00:01