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feature/fa
| Author | SHA1 | Date | |
|---|---|---|---|
| 6608412c04 | |||
| 4c7dc5090b | |||
| e8ef7cc2fb | |||
| feffe97c18 | |||
| 2d7743a87d | |||
| 71ee53540b | |||
| b8e388e4eb | |||
| 51c73cd883 | |||
| 0ec5a4663b |
62
ALU_P379.vhdl
Normal file
62
ALU_P379.vhdl
Normal file
@@ -0,0 +1,62 @@
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity ALU_P379 is
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Port ( ALU1 : in STD_LOGIC_VECTOR (7 downto 0);
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LOAD1 : in STD_LOGIC;
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ALU2 : in STD_LOGIC_VECTOR (7 downto 0);
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LOAD2 : in STD_LOGIC;
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OE : in STD_LOGIC;
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OPCODE: in STD_LOGIC_VECTOR (7 downto 0);
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CARRY : out STD_LOGIC;
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OUTPUT : out STD_LOGIC_VECTOR (7 downto 0));
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end ALU_P379;
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architecture Behavioral of ALU_P379 is
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signal OUTPUT_ALL: std_logic_vector (7 downto 0);
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signal ALU1_REG: std_logic_vector (7 downto 0);
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signal ALU2_REG: std_logic_vector (7 downto 0);
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begin
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process(OPCODE)
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begin
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case OPCODE is
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when "00000000" => output_all <= ALU1_REG + ALU2_REG;
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when "00000001" => output_all <= ALU1_REG - ALU2_rEG;
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when "00000010" => output_all <= ALU1_REG and ALU2_REG;
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when "00000011" => output_all <= ALU1_REG nand ALU2_REG;
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when "00000100" => output_all <= ALU1_REG or ALU2_REG;
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when "00000101" => output_all <= ALU1_REG xor ALU2_REG;
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when "00000111" => output_all <= not ALU1_REG;
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when others => output_all <= "ZZZZZZZZ";
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end case;
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end process;
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process(OE)
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begin
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case OE is
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when '1' => OUTPUT <= output_all;
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when others => OUTPUT <= "ZZZZZZZZ";
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end case;
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end process;
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process(LOAD1)
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begin
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if(LOAD1'event and LOAD1 = '1') then
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ALU1_REG <= ALU1;
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end if;
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end process;
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process(LOAD2)
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begin
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if(LOAD2'event and LOAD2 = '1') then
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ALU2_REG <= ALU2;
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end if;
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end process;
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end Behavioral;
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67
Registers.vhdl
Normal file
67
Registers.vhdl
Normal file
@@ -0,0 +1,67 @@
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----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 11:29:57 02/27/2023
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-- Design Name:
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-- Module Name: Registers - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity Registers is
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Port ( DATA : inout STD_LOGIC_VECTOR (7 downto 0);
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OE : in STD_LOGIC_VECTOR (15 downto 0);
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WR : in STD_LOGIC_VECTOR (15 downto 0));
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end Registers;
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architecture Behavioral of Registers is
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type regarray_t is array (15 downto 0) of std_logic_vector (7 downto 0);
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signal regvalues: regarray_t;
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begin
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process(WR)
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begin
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for regindex in 15 downto 0 loop
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if(WR(regindex)'event and WR(regindex) = '1') then
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regvalues(regindex) <= DATA;
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end if;
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end loop;
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end process;
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process(OE)
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begin
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if (OE = "0000000000000000") then
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DATA <= "ZZZZZZZZ";
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end if;
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for regindex in 15 downto 0 loop
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if(OE(regindex) = '1') then
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DATA <= regvalues(regindex);
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end if;
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end loop;
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end process;
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end Behavioral;
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66
XC3S400.xise
66
XC3S400.xise
@@ -17,16 +17,27 @@
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<files>
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<file xil_pn:name="main.vhdl" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
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</file>
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<file xil_pn:name="constraints.ucf" xil_pn:type="FILE_UCF">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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<file xil_pn:name="sevseg.vhdl" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="58"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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</file>
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<file xil_pn:name="ALU_P379.vhdl" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
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</file>
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<file xil_pn:name="Registers.vhdl" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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</file>
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<file xil_pn:name="Opcode descriptions.txt" xil_pn:type="FILE_USERDOC"/>
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</files>
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<properties>
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<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
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@@ -40,8 +51,6 @@
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<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
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<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
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<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
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<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
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@@ -60,13 +69,11 @@
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<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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<property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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<property xil_pn:name="Configuration Rate" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
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<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
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<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
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@@ -77,7 +84,6 @@
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<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
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<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
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<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
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<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
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@@ -86,33 +92,26 @@
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<property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
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<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
|
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<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
|
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<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
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<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
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<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
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<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
|
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<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
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<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
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<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
|
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<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
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<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
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<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
|
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<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
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<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
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<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
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<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
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<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
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<property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
|
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<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
|
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<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
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<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
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<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
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<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
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<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
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<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
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<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
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@@ -136,12 +135,9 @@
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<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
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<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
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<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
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<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
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<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
@@ -159,10 +155,7 @@
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
|
||||
@@ -174,23 +167,20 @@
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="8" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
@@ -221,20 +211,14 @@
|
||||
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="main_map.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="main_timesim.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="main_synthesis.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="main_translate.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
@@ -245,13 +229,10 @@
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
@@ -277,7 +258,6 @@
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
@@ -285,9 +265,7 @@
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
@@ -303,8 +281,6 @@
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
@@ -330,26 +306,20 @@
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-200X" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCI Match (Output Events) virtex2" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
@@ -1,4 +1,6 @@
|
||||
NET "CLK" LOC = A8 ;
|
||||
NET "BUT[0]" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||
NET "BUT[1]" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||
|
||||
NET "SW[0]" LOC = N15;
|
||||
NET "SW[1]" LOC = J16;
|
||||
@@ -23,16 +25,16 @@ NET "BUT[1]" LOC = K14;
|
||||
NET "BUT[2]" LOC = K13;
|
||||
NET "BUT[3]" LOC = K12;
|
||||
|
||||
NET "SEVSEG[0]" LOC = F13;
|
||||
NET "SEVSEG[1]" LOC = E13;
|
||||
NET "SEVSEG[2]" LOC = G15;
|
||||
NET "SEVSEG[3]" LOC = H13;
|
||||
NET "SEVSEG[4]" LOC = J14;
|
||||
NET "SEVSEG[5]" LOC = E14;
|
||||
NET "SEVSEG[6]" LOC = G16;
|
||||
NET "SEVSEG[7]" LOC = H14;
|
||||
NET "SEVSEG_SEGMENTS[0]" LOC = F13;
|
||||
NET "SEVSEG_SEGMENTS[1]" LOC = E13;
|
||||
NET "SEVSEG_SEGMENTS[2]" LOC = G15;
|
||||
NET "SEVSEG_SEGMENTS[3]" LOC = H13;
|
||||
NET "SEVSEG_SEGMENTS[4]" LOC = J14;
|
||||
NET "SEVSEG_SEGMENTS[5]" LOC = E14;
|
||||
NET "SEVSEG_SEGMENTS[6]" LOC = G16;
|
||||
NET "SEVSEG_SEGMENTS[7]" LOC = H14;
|
||||
|
||||
NET "DIGITS[0]" LOC = G14;
|
||||
NET "DIGITS[1]" LOC = G12;
|
||||
NET "DIGITS[2]" LOC = G13;
|
||||
NET "DIGITS[3]" LOC = F12;
|
||||
NET "SEVSEG_DIGITS[0]" LOC = G14;
|
||||
NET "SEVSEG_DIGITS[1]" LOC = G12;
|
||||
NET "SEVSEG_DIGITS[2]" LOC = G13;
|
||||
NET "SEVSEG_DIGITS[3]" LOC = F12;
|
||||
84
main.vhdl
84
main.vhdl
@@ -36,8 +36,8 @@ entity main is
|
||||
LEDS : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
BUT : in STD_LOGIC_VECTOR (3 downto 0);
|
||||
SW : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
SEVSEG : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
DIGITS: out STD_LOGIC_VECTOR (3 downto 0)
|
||||
SEVSEG_SEGMENTS: out STD_LOGIC_VECTOR (7 downto 0);
|
||||
SEVSEG_DIGITS: out STD_LOGIC_VECTOR (3 downto 0)
|
||||
);
|
||||
end main;
|
||||
|
||||
@@ -48,11 +48,78 @@ signal clk100k: std_logic;
|
||||
signal contaux: std_logic_vector (31 downto 0);
|
||||
signal clk745ms, clk1490ms: std_logic;
|
||||
|
||||
signal SEVSEG_UINT16: std_logic_vector (15 downto 0);
|
||||
|
||||
signal DATABUS: std_logic_vector (7 downto 0);
|
||||
signal ADDRBUS: std_logic_vector (7 downto 0);
|
||||
signal FLAG_CARRY: std_logic;
|
||||
|
||||
--fake flash memory
|
||||
type fakeflash_t is array (255 downto 0) of std_logic_vector (31 downto 0);
|
||||
signal program: fakeflash_t;
|
||||
|
||||
component SEVSEG
|
||||
Port ( UINT16 : in STD_LOGIC_VECTOR (15 downto 0);
|
||||
CLK : in STD_LOGIC;
|
||||
SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
DIGITS : out STD_LOGIC_VECTOR (3 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component ALU_P379
|
||||
Port ( ALU1 : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
LOAD1 : in STD_LOGIC;
|
||||
ALU2 : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
LOAD2 : in STD_LOGIC;
|
||||
OE : in STD_LOGIC;
|
||||
OPCODE: in STD_LOGIC_VECTOR (7 downto 0);
|
||||
CARRY : out STD_LOGIC;
|
||||
OUTPUT : out STD_LOGIC_VECTOR (7 downto 0));
|
||||
end component;
|
||||
|
||||
component REGISTERS
|
||||
Port ( DATA : inout STD_LOGIC_VECTOR (7 downto 0);
|
||||
OE : in STD_LOGIC_VECTOR (15 downto 0);
|
||||
WR : in STD_LOGIC_VECTOR (15 downto 0));
|
||||
end component;
|
||||
|
||||
begin
|
||||
|
||||
SEVSEG0: SEVSEG port map ( UINT16 => SEVSEG_UINT16,
|
||||
CLK => contaux(12),
|
||||
SEGMENTS => SEVSEG_SEGMENTS,
|
||||
DIGITS => SEVSEG_DIGITS
|
||||
);
|
||||
|
||||
ALU0: ALU_P379 port map ( ALU1 => DATABUS,
|
||||
LOAD1 => '0', --comes from control logic
|
||||
ALU2 => DATABUS,
|
||||
LOAD2 => '0', --comes from control logic
|
||||
OE => '0', --comes from control logic
|
||||
OPCODE => "00000000", --comes from control logic
|
||||
CARRY => FLAG_CARRY,
|
||||
OUTPUT => DATABUS
|
||||
);
|
||||
|
||||
REGISTERS0: REGISTERS port map ( DATA => DATABUS,
|
||||
OE => "0000000000000000", --comes from control logic
|
||||
WR => "0000000000000000" --comes from control logic
|
||||
);
|
||||
|
||||
--begin fake flash memory
|
||||
program(0) <= "0000" & "0001" & "00000000" & "00001010" & "00000000"; --MOV R0, 0A
|
||||
program(1) <= "0000" & "0001" & "00000001" & "00000111" & "00000000"; --MOV R1, 07
|
||||
program(2) <= "0001" & "0000" & "00000000" & "00000000" & "00000001"; --ALU ADD R0, R1
|
||||
program(3) <= "0000" & "0001" & "00001111" & "00000100" & "00000000"; --MOV R15, 4
|
||||
program(4) <= "0010" & "0000" & "00001111" & "00000000" & "00000000"; --JMP R15
|
||||
--end fake flash memory
|
||||
|
||||
SEVSEG_UINT16 <= ADDRBUS & DATABUS;
|
||||
DATABUS <= "ZZZZZZZZ";
|
||||
LEDS <= "ZZZZZZZZ";
|
||||
SEVSEG <= "ZZZZZZZZ";
|
||||
DIGITS <= "ZZZZ";
|
||||
SEVSEG_SEGMENTS <= "ZZZZZZZZ";
|
||||
SEVSEG_DIGITS <= "ZZZZ";
|
||||
SEVSEG_UINT16 <= "ZZZZ" & "ZZZZ" & "ZZZZ" & "ZZZZ";
|
||||
CLK100k <= cont100k(7);
|
||||
clk745ms <= contaux(23);
|
||||
clk1490ms <= contaux(24);
|
||||
@@ -70,4 +137,13 @@ begin
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (BUT(3))
|
||||
begin
|
||||
if(BUT(3) = '1') then
|
||||
DATABUS <= SW;
|
||||
else
|
||||
DATABUS <= "ZZZZZZZZ";
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
163
sevseg.vhdl
Normal file
163
sevseg.vhdl
Normal file
@@ -0,0 +1,163 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 20:36:54 02/07/2023
|
||||
-- Design Name:
|
||||
-- Module Name: sevseg - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity sevseg is
|
||||
Port ( UINT16 : in STD_LOGIC_VECTOR (15 downto 0);
|
||||
CLK : in STD_LOGIC;
|
||||
SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
DIGITS : out STD_LOGIC_VECTOR (3 downto 0)
|
||||
);
|
||||
end sevseg;
|
||||
|
||||
architecture Behavioral of sevseg is
|
||||
|
||||
signal DIGIT0: std_logic_vector (3 downto 0);
|
||||
signal DIGIT1: std_logic_vector (3 downto 0);
|
||||
signal DIGIT2: std_logic_vector (3 downto 0);
|
||||
signal DIGIT3: std_logic_vector (3 downto 0);
|
||||
|
||||
signal SEGMENTS0: std_logic_vector (7 downto 0);
|
||||
signal SEGMENTS1: std_logic_vector (7 downto 0);
|
||||
signal SEGMENTS2: std_logic_vector (7 downto 0);
|
||||
signal SEGMENTS3: std_logic_vector (7 downto 0);
|
||||
|
||||
signal digitsaux: std_logic_vector (3 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
DIGIT0 <= UINT16 (3 downto 0);
|
||||
DIGIT1 <= UINT16 (7 downto 4);
|
||||
DIGIT2 <= UINT16 (11 downto 8);
|
||||
DIGIT3 <= UINT16 (15 downto 12);
|
||||
DIGITS <= not digitsaux;
|
||||
|
||||
process(UINT16)
|
||||
begin
|
||||
case DIGIT0 is
|
||||
when "0000" => segments0 <= "00111111";
|
||||
when "0001" => segments0 <= "00000110";
|
||||
when "0010" => segments0 <= "01011011";
|
||||
when "0011" => segments0 <= "01001111";
|
||||
when "0100" => segments0 <= "01100110";
|
||||
when "0101" => segments0 <= "01101101";
|
||||
when "0110" => segments0 <= "01111101";
|
||||
when "0111" => segments0 <= "00000111";
|
||||
when "1000" => segments0 <= "01111111";
|
||||
when "1001" => segments0 <= "01101111";
|
||||
when "1010" => segments0 <= "01110111";
|
||||
when "1011" => segments0 <= "01111100";
|
||||
when "1100" => segments0 <= "00111001";
|
||||
when "1101" => segments0 <= "01011110";
|
||||
when "1110" => segments0 <= "01111001";
|
||||
when "1111" => segments0 <= "01110001";
|
||||
when others => segments0 <= "10000000";
|
||||
end case;
|
||||
case DIGIT1 is
|
||||
when "0000" => segments1 <= "00111111";
|
||||
when "0001" => segments1 <= "00000110";
|
||||
when "0010" => segments1 <= "01011011";
|
||||
when "0011" => segments1 <= "01001111";
|
||||
when "0100" => segments1 <= "01100110";
|
||||
when "0101" => segments1 <= "01101101";
|
||||
when "0110" => segments1 <= "01111101";
|
||||
when "0111" => segments1 <= "00000111";
|
||||
when "1000" => segments1 <= "01111111";
|
||||
when "1001" => segments1 <= "01101111";
|
||||
when "1010" => segments1 <= "01110111";
|
||||
when "1011" => segments1 <= "01111100";
|
||||
when "1100" => segments1 <= "00111001";
|
||||
when "1101" => segments1 <= "01011110";
|
||||
when "1110" => segments1 <= "01111001";
|
||||
when "1111" => segments1 <= "01110001";
|
||||
when others => segments1 <= "10000000";
|
||||
end case;
|
||||
case DIGIT2 is
|
||||
when "0000" => segments2 <= "00111111";
|
||||
when "0001" => segments2 <= "00000110";
|
||||
when "0010" => segments2 <= "01011011";
|
||||
when "0011" => segments2 <= "01001111";
|
||||
when "0100" => segments2 <= "01100110";
|
||||
when "0101" => segments2 <= "01101101";
|
||||
when "0110" => segments2 <= "01111101";
|
||||
when "0111" => segments2 <= "00000111";
|
||||
when "1000" => segments2 <= "01111111";
|
||||
when "1001" => segments2 <= "01101111";
|
||||
when "1010" => segments2 <= "01110111";
|
||||
when "1011" => segments2 <= "01111100";
|
||||
when "1100" => segments2 <= "00111001";
|
||||
when "1101" => segments2 <= "01011110";
|
||||
when "1110" => segments2 <= "01111001";
|
||||
when "1111" => segments2 <= "01110001";
|
||||
when others => segments2 <= "10000000";
|
||||
end case;
|
||||
case DIGIT3 is
|
||||
when "0000" => segments3 <= "00111111";
|
||||
when "0001" => segments3 <= "00000110";
|
||||
when "0010" => segments3 <= "01011011";
|
||||
when "0011" => segments3 <= "01001111";
|
||||
when "0100" => segments3 <= "01100110";
|
||||
when "0101" => segments3 <= "01101101";
|
||||
when "0110" => segments3 <= "01111101";
|
||||
when "0111" => segments3 <= "00000111";
|
||||
when "1000" => segments3 <= "01111111";
|
||||
when "1001" => segments3 <= "01101111";
|
||||
when "1010" => segments3 <= "01110111";
|
||||
when "1011" => segments3 <= "01111100";
|
||||
when "1100" => segments3 <= "00111001";
|
||||
when "1101" => segments3 <= "01011110";
|
||||
when "1110" => segments3 <= "01111001";
|
||||
when "1111" => segments3 <= "01110001";
|
||||
when others => segments3 <= "10000000";
|
||||
end case;
|
||||
end process;
|
||||
|
||||
process (CLK)
|
||||
begin
|
||||
if(CLK'event and CLK = '1') then
|
||||
case digitsaux is
|
||||
when "0001" =>
|
||||
digitsaux <= "0010";
|
||||
SEGMENTS <= not segments1;
|
||||
when "0010" =>
|
||||
digitsaux <= "0100";
|
||||
SEGMENTS <= not segments2;
|
||||
when "0100" =>
|
||||
digitsaux <= "1000";
|
||||
SEGMENTS <= not segments3;
|
||||
when others =>
|
||||
digitsaux <= "0001";
|
||||
SEGMENTS <= not segments0;
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
Reference in New Issue
Block a user