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00421335cdbc20097923bb42a1cd10175a7152da
PFC/Code/STM32/Debug/F103C8-PFC.list

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F103C8-PFC.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 0000010c 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00005710 0800010c 0800010c 0001010c 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000260 0800581c 0800581c 0001581c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08005a7c 08005a7c 00020070 2**0
CONTENTS
4 .ARM 00000000 08005a7c 08005a7c 00020070 2**0
CONTENTS
5 .preinit_array 00000000 08005a7c 08005a7c 00020070 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000008 08005a7c 08005a7c 00015a7c 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000008 08005a84 08005a84 00015a84 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 00000070 20000000 08005a8c 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00000834 20000070 08005afc 00020070 2**2
ALLOC
10 ._user_heap_stack 00000604 200008a4 08005afc 000208a4 2**0
ALLOC
11 .ARM.attributes 00000029 00000000 00000000 00020070 2**0
CONTENTS, READONLY
12 .debug_info 00013e06 00000000 00000000 00020099 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 000031e4 00000000 00000000 00033e9f 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 000010c8 00000000 00000000 00037088 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_ranges 00001000 00000000 00000000 00038150 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 0001c271 00000000 00000000 00039150 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00012eeb 00000000 00000000 000553c1 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 00091950 00000000 00000000 000682ac 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000050 00000000 00000000 000f9bfc 2**0
CONTENTS, READONLY
20 .debug_frame 00004c04 00000000 00000000 000f9c4c 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
0800010c <__do_global_dtors_aux>:
800010c: b510 push {r4, lr}
800010e: 4c05 ldr r4, [pc, #20] ; (8000124 <__do_global_dtors_aux+0x18>)
8000110: 7823 ldrb r3, [r4, #0]
8000112: b933 cbnz r3, 8000122 <__do_global_dtors_aux+0x16>
8000114: 4b04 ldr r3, [pc, #16] ; (8000128 <__do_global_dtors_aux+0x1c>)
8000116: b113 cbz r3, 800011e <__do_global_dtors_aux+0x12>
8000118: 4804 ldr r0, [pc, #16] ; (800012c <__do_global_dtors_aux+0x20>)
800011a: f3af 8000 nop.w
800011e: 2301 movs r3, #1
8000120: 7023 strb r3, [r4, #0]
8000122: bd10 pop {r4, pc}
8000124: 20000070 .word 0x20000070
8000128: 00000000 .word 0x00000000
800012c: 08005804 .word 0x08005804
08000130 <frame_dummy>:
8000130: b508 push {r3, lr}
8000132: 4b03 ldr r3, [pc, #12] ; (8000140 <frame_dummy+0x10>)
8000134: b11b cbz r3, 800013e <frame_dummy+0xe>
8000136: 4903 ldr r1, [pc, #12] ; (8000144 <frame_dummy+0x14>)
8000138: 4803 ldr r0, [pc, #12] ; (8000148 <frame_dummy+0x18>)
800013a: f3af 8000 nop.w
800013e: bd08 pop {r3, pc}
8000140: 00000000 .word 0x00000000
8000144: 20000074 .word 0x20000074
8000148: 08005804 .word 0x08005804
0800014c <strcmp>:
800014c: f810 2b01 ldrb.w r2, [r0], #1
8000150: f811 3b01 ldrb.w r3, [r1], #1
8000154: 2a01 cmp r2, #1
8000156: bf28 it cs
8000158: 429a cmpcs r2, r3
800015a: d0f7 beq.n 800014c <strcmp>
800015c: 1ad0 subs r0, r2, r3
800015e: 4770 bx lr
08000160 <strlen>:
8000160: 4603 mov r3, r0
8000162: f813 2b01 ldrb.w r2, [r3], #1
8000166: 2a00 cmp r2, #0
8000168: d1fb bne.n 8000162 <strlen+0x2>
800016a: 1a18 subs r0, r3, r0
800016c: 3801 subs r0, #1
800016e: 4770 bx lr
08000170 <_ZN7ESP8266C1EP20__UART_HandleTypeDef>:
*/
#include "ESP8266.hpp"
#include <cstdio>
ESP8266::ESP8266(UART_HandleTypeDef* huart) : huart(huart){
8000170: b480 push {r7}
8000172: b083 sub sp, #12
8000174: af00 add r7, sp, #0
8000176: 6078 str r0, [r7, #4]
8000178: 6039 str r1, [r7, #0]
800017a: 4a06 ldr r2, [pc, #24] ; (8000194 <_ZN7ESP8266C1EP20__UART_HandleTypeDef+0x24>)
800017c: 687b ldr r3, [r7, #4]
800017e: 601a str r2, [r3, #0]
8000180: 687b ldr r3, [r7, #4]
8000182: 683a ldr r2, [r7, #0]
8000184: f8c3 2110 str.w r2, [r3, #272] ; 0x110
// TODO Auto-generated constructor stub
}
8000188: 687b ldr r3, [r7, #4]
800018a: 4618 mov r0, r3
800018c: 370c adds r7, #12
800018e: 46bd mov sp, r7
8000190: bc80 pop {r7}
8000192: 4770 bx lr
8000194: 08005a18 .word 0x08005a18
08000198 <_ZN7ESP8266D1Ev>:
ESP8266::~ESP8266() {
8000198: b480 push {r7}
800019a: b083 sub sp, #12
800019c: af00 add r7, sp, #0
800019e: 6078 str r0, [r7, #4]
80001a0: 4a04 ldr r2, [pc, #16] ; (80001b4 <_ZN7ESP8266D1Ev+0x1c>)
80001a2: 687b ldr r3, [r7, #4]
80001a4: 601a str r2, [r3, #0]
// TODO Auto-generated destructor stub
}
80001a6: 687b ldr r3, [r7, #4]
80001a8: 4618 mov r0, r3
80001aa: 370c adds r7, #12
80001ac: 46bd mov sp, r7
80001ae: bc80 pop {r7}
80001b0: 4770 bx lr
80001b2: bf00 nop
80001b4: 08005a18 .word 0x08005a18
080001b8 <_ZN7ESP8266D0Ev>:
ESP8266::~ESP8266() {
80001b8: b580 push {r7, lr}
80001ba: b082 sub sp, #8
80001bc: af00 add r7, sp, #0
80001be: 6078 str r0, [r7, #4]
}
80001c0: 6878 ldr r0, [r7, #4]
80001c2: f7ff ffe9 bl 8000198 <_ZN7ESP8266D1Ev>
80001c6: f44f 7105 mov.w r1, #532 ; 0x214
80001ca: 6878 ldr r0, [r7, #4]
80001cc: f004 fdf2 bl 8004db4 <_ZdlPvj>
80001d0: 687b ldr r3, [r7, #4]
80001d2: 4618 mov r0, r3
80001d4: 3708 adds r7, #8
80001d6: 46bd mov sp, r7
80001d8: bd80 pop {r7, pc}
...
080001dc <_ZN7ESP82664initEv>:
void ESP8266::init(){
80001dc: b580 push {r7, lr}
80001de: b082 sub sp, #8
80001e0: af00 add r7, sp, #0
80001e2: 6078 str r0, [r7, #4]
command("AT+CWMODE=1,1\r\n");
80001e4: 490b ldr r1, [pc, #44] ; (8000214 <_ZN7ESP82664initEv+0x38>)
80001e6: 6878 ldr r0, [r7, #4]
80001e8: f000 f81e bl 8000228 <_ZN7ESP82667commandEPKc>
command("AT+CWJAP=\"Gabriel_2G\",\"gabrielwifi\"\r\n");
80001ec: 490a ldr r1, [pc, #40] ; (8000218 <_ZN7ESP82664initEv+0x3c>)
80001ee: 6878 ldr r0, [r7, #4]
80001f0: f000 f81a bl 8000228 <_ZN7ESP82667commandEPKc>
//command("AT+CWLAP\r\n");
command("AT+CIPMUX=1\r\n");
80001f4: 4909 ldr r1, [pc, #36] ; (800021c <_ZN7ESP82664initEv+0x40>)
80001f6: 6878 ldr r0, [r7, #4]
80001f8: f000 f816 bl 8000228 <_ZN7ESP82667commandEPKc>
command("AT+CIPRECVMODE=1\r\n");
80001fc: 4908 ldr r1, [pc, #32] ; (8000220 <_ZN7ESP82664initEv+0x44>)
80001fe: 6878 ldr r0, [r7, #4]
8000200: f000 f812 bl 8000228 <_ZN7ESP82667commandEPKc>
command("AT+CIPSTART=0,\"UDP\",\"239.0.0.1\",10001,11001,0\r\n");
8000204: 4907 ldr r1, [pc, #28] ; (8000224 <_ZN7ESP82664initEv+0x48>)
8000206: 6878 ldr r0, [r7, #4]
8000208: f000 f80e bl 8000228 <_ZN7ESP82667commandEPKc>
}
800020c: bf00 nop
800020e: 3708 adds r7, #8
8000210: 46bd mov sp, r7
8000212: bd80 pop {r7, pc}
8000214: 0800581c .word 0x0800581c
8000218: 0800582c .word 0x0800582c
800021c: 08005854 .word 0x08005854
8000220: 08005864 .word 0x08005864
8000224: 08005878 .word 0x08005878
08000228 <_ZN7ESP82667commandEPKc>:
ESP8266::statusTypeDef ESP8266::command(const char* command) {
8000228: b590 push {r4, r7, lr}
800022a: b083 sub sp, #12
800022c: af00 add r7, sp, #0
800022e: 6078 str r0, [r7, #4]
8000230: 6039 str r1, [r7, #0]
HAL_UART_Transmit(huart, (uint8_t*)command, strlen(command), 100);
8000232: 687b ldr r3, [r7, #4]
8000234: f8d3 4110 ldr.w r4, [r3, #272] ; 0x110
8000238: 6838 ldr r0, [r7, #0]
800023a: f7ff ff91 bl 8000160 <strlen>
800023e: 4603 mov r3, r0
8000240: b29a uxth r2, r3
8000242: 2364 movs r3, #100 ; 0x64
8000244: 6839 ldr r1, [r7, #0]
8000246: 4620 mov r0, r4
8000248: f003 ff3b bl 80040c2 <HAL_UART_Transmit>
return wait_until_ok();
800024c: 6878 ldr r0, [r7, #4]
800024e: f000 f983 bl 8000558 <_ZN7ESP826613wait_until_okEv>
8000252: 4603 mov r3, r0
}
8000254: 4618 mov r0, r3
8000256: 370c adds r7, #12
8000258: 46bd mov sp, r7
800025a: bd90 pop {r4, r7, pc}
0800025c <_ZN7ESP82664sendEPKc>:
ESP8266::statusTypeDef ESP8266::send(const char* data) {
800025c: b590 push {r4, r7, lr}
800025e: b083 sub sp, #12
8000260: af00 add r7, sp, #0
8000262: 6078 str r0, [r7, #4]
8000264: 6039 str r1, [r7, #0]
HAL_UART_Transmit(huart, (uint8_t*)data, strlen(data), 100);
8000266: 687b ldr r3, [r7, #4]
8000268: f8d3 4110 ldr.w r4, [r3, #272] ; 0x110
800026c: 6838 ldr r0, [r7, #0]
800026e: f7ff ff77 bl 8000160 <strlen>
8000272: 4603 mov r3, r0
8000274: b29a uxth r2, r3
8000276: 2364 movs r3, #100 ; 0x64
8000278: 6839 ldr r1, [r7, #0]
800027a: 4620 mov r0, r4
800027c: f003 ff21 bl 80040c2 <HAL_UART_Transmit>
return wait_until_send_ok();
8000280: 6878 ldr r0, [r7, #4]
8000282: f000 f9af bl 80005e4 <_ZN7ESP826618wait_until_send_okEv>
8000286: 4603 mov r3, r0
}
8000288: 4618 mov r0, r3
800028a: 370c adds r7, #12
800028c: 46bd mov sp, r7
800028e: bd90 pop {r4, r7, pc}
08000290 <_ZN7ESP826611send_uint32EPKcm>:
void ESP8266::send_uint32(const char* name, uint32_t value){
8000290: b580 push {r7, lr}
8000292: f5ad 7d04 sub.w sp, sp, #528 ; 0x210
8000296: af00 add r7, sp, #0
8000298: f507 7304 add.w r3, r7, #528 ; 0x210
800029c: f5a3 7301 sub.w r3, r3, #516 ; 0x204
80002a0: 6018 str r0, [r3, #0]
80002a2: f507 7304 add.w r3, r7, #528 ; 0x210
80002a6: f5a3 7302 sub.w r3, r3, #520 ; 0x208
80002aa: 6019 str r1, [r3, #0]
80002ac: f507 7304 add.w r3, r7, #528 ; 0x210
80002b0: f5a3 7303 sub.w r3, r3, #524 ; 0x20c
80002b4: 601a str r2, [r3, #0]
char commandBuffer[256];
char payloadBuffer[256];
sprintf(payloadBuffer, ">%s:%lu\r\n", name, value);
80002b6: f507 7304 add.w r3, r7, #528 ; 0x210
80002ba: f5a3 7303 sub.w r3, r3, #524 ; 0x20c
80002be: f507 7204 add.w r2, r7, #528 ; 0x210
80002c2: f5a2 7202 sub.w r2, r2, #520 ; 0x208
80002c6: f107 0010 add.w r0, r7, #16
80002ca: 681b ldr r3, [r3, #0]
80002cc: 6812 ldr r2, [r2, #0]
80002ce: 4914 ldr r1, [pc, #80] ; (8000320 <_ZN7ESP826611send_uint32EPKcm+0x90>)
80002d0: f004 ff18 bl 8005104 <siprintf>
sprintf(commandBuffer, "AT+CIPSEND=0,%u\r\n", strlen(payloadBuffer));
80002d4: f107 0310 add.w r3, r7, #16
80002d8: 4618 mov r0, r3
80002da: f7ff ff41 bl 8000160 <strlen>
80002de: 4602 mov r2, r0
80002e0: f507 7388 add.w r3, r7, #272 ; 0x110
80002e4: 490f ldr r1, [pc, #60] ; (8000324 <_ZN7ESP826611send_uint32EPKcm+0x94>)
80002e6: 4618 mov r0, r3
80002e8: f004 ff0c bl 8005104 <siprintf>
command(commandBuffer);
80002ec: f507 7288 add.w r2, r7, #272 ; 0x110
80002f0: f507 7304 add.w r3, r7, #528 ; 0x210
80002f4: f5a3 7301 sub.w r3, r3, #516 ; 0x204
80002f8: 4611 mov r1, r2
80002fa: 6818 ldr r0, [r3, #0]
80002fc: f7ff ff94 bl 8000228 <_ZN7ESP82667commandEPKc>
send(payloadBuffer);
8000300: f107 0210 add.w r2, r7, #16
8000304: f507 7304 add.w r3, r7, #528 ; 0x210
8000308: f5a3 7301 sub.w r3, r3, #516 ; 0x204
800030c: 4611 mov r1, r2
800030e: 6818 ldr r0, [r3, #0]
8000310: f7ff ffa4 bl 800025c <_ZN7ESP82664sendEPKc>
}
8000314: bf00 nop
8000316: f507 7704 add.w r7, r7, #528 ; 0x210
800031a: 46bd mov sp, r7
800031c: bd80 pop {r7, pc}
800031e: bf00 nop
8000320: 080058a8 .word 0x080058a8
8000324: 080058b4 .word 0x080058b4
08000328 <_ZN7ESP826614receive_uint32Ev>:
uint32_t ESP8266::receive_uint32() {
8000328: b580 push {r7, lr}
800032a: b0c2 sub sp, #264 ; 0x108
800032c: af00 add r7, sp, #0
800032e: f507 7384 add.w r3, r7, #264 ; 0x108
8000332: f5a3 7382 sub.w r3, r3, #260 ; 0x104
8000336: 6018 str r0, [r3, #0]
char commandBuffer[256];
sprintf(commandBuffer, "AT+CIPRECVDATA=0,256\r\n");
8000338: f107 0308 add.w r3, r7, #8
800033c: 4909 ldr r1, [pc, #36] ; (8000364 <_ZN7ESP826614receive_uint32Ev+0x3c>)
800033e: 4618 mov r0, r3
8000340: f004 fee0 bl 8005104 <siprintf>
command(commandBuffer);
8000344: f107 0208 add.w r2, r7, #8
8000348: f507 7384 add.w r3, r7, #264 ; 0x108
800034c: f5a3 7382 sub.w r3, r3, #260 ; 0x104
8000350: 4611 mov r1, r2
8000352: 6818 ldr r0, [r3, #0]
8000354: f7ff ff68 bl 8000228 <_ZN7ESP82667commandEPKc>
}
8000358: bf00 nop
800035a: 4618 mov r0, r3
800035c: f507 7784 add.w r7, r7, #264 ; 0x108
8000360: 46bd mov sp, r7
8000362: bd80 pop {r7, pc}
8000364: 080058c8 .word 0x080058c8
08000368 <_ZN7ESP826626wait_on_flag_until_timeoutEm10FlagStatusmm>:
HAL_StatusTypeDef ESP8266::wait_on_flag_until_timeout(uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) {
8000368: b580 push {r7, lr}
800036a: b084 sub sp, #16
800036c: af00 add r7, sp, #0
800036e: 60f8 str r0, [r7, #12]
8000370: 60b9 str r1, [r7, #8]
8000372: 603b str r3, [r7, #0]
8000374: 4613 mov r3, r2
8000376: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) {
8000378: 68fb ldr r3, [r7, #12]
800037a: f8d3 3110 ldr.w r3, [r3, #272] ; 0x110
800037e: 681b ldr r3, [r3, #0]
8000380: 681a ldr r2, [r3, #0]
8000382: 68bb ldr r3, [r7, #8]
8000384: 4013 ands r3, r2
8000386: 68ba ldr r2, [r7, #8]
8000388: 429a cmp r2, r3
800038a: d101 bne.n 8000390 <_ZN7ESP826626wait_on_flag_until_timeoutEm10FlagStatusmm+0x28>
800038c: 2201 movs r2, #1
800038e: e000 b.n 8000392 <_ZN7ESP826626wait_on_flag_until_timeoutEm10FlagStatusmm+0x2a>
8000390: 2200 movs r2, #0
8000392: 79fb ldrb r3, [r7, #7]
8000394: 429a cmp r2, r3
8000396: bf0c ite eq
8000398: 2301 moveq r3, #1
800039a: 2300 movne r3, #0
800039c: b2db uxtb r3, r3
800039e: 2b00 cmp r3, #0
80003a0: d03f beq.n 8000422 <_ZN7ESP826626wait_on_flag_until_timeoutEm10FlagStatusmm+0xba>
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY) {
80003a2: 69bb ldr r3, [r7, #24]
80003a4: f1b3 3fff cmp.w r3, #4294967295
80003a8: d0e6 beq.n 8000378 <_ZN7ESP826626wait_on_flag_until_timeoutEm10FlagStatusmm+0x10>
if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) {
80003aa: 69bb ldr r3, [r7, #24]
80003ac: 2b00 cmp r3, #0
80003ae: d007 beq.n 80003c0 <_ZN7ESP826626wait_on_flag_until_timeoutEm10FlagStatusmm+0x58>
80003b0: f001 fa6a bl 8001888 <HAL_GetTick>
80003b4: 4602 mov r2, r0
80003b6: 683b ldr r3, [r7, #0]
80003b8: 1ad3 subs r3, r2, r3
80003ba: 69ba ldr r2, [r7, #24]
80003bc: 429a cmp r2, r3
80003be: d201 bcs.n 80003c4 <_ZN7ESP826626wait_on_flag_until_timeoutEm10FlagStatusmm+0x5c>
80003c0: 2301 movs r3, #1
80003c2: e000 b.n 80003c6 <_ZN7ESP826626wait_on_flag_until_timeoutEm10FlagStatusmm+0x5e>
80003c4: 2300 movs r3, #0
80003c6: 2b00 cmp r3, #0
80003c8: d0d6 beq.n 8000378 <_ZN7ESP826626wait_on_flag_until_timeoutEm10FlagStatusmm+0x10>
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
80003ca: 68fb ldr r3, [r7, #12]
80003cc: f8d3 3110 ldr.w r3, [r3, #272] ; 0x110
80003d0: 681b ldr r3, [r3, #0]
80003d2: 68da ldr r2, [r3, #12]
80003d4: 68fb ldr r3, [r7, #12]
80003d6: f8d3 3110 ldr.w r3, [r3, #272] ; 0x110
80003da: 681b ldr r3, [r3, #0]
80003dc: f422 72d0 bic.w r2, r2, #416 ; 0x1a0
80003e0: 60da str r2, [r3, #12]
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
80003e2: 68fb ldr r3, [r7, #12]
80003e4: f8d3 3110 ldr.w r3, [r3, #272] ; 0x110
80003e8: 681b ldr r3, [r3, #0]
80003ea: 695a ldr r2, [r3, #20]
80003ec: 68fb ldr r3, [r7, #12]
80003ee: f8d3 3110 ldr.w r3, [r3, #272] ; 0x110
80003f2: 681b ldr r3, [r3, #0]
80003f4: f022 0201 bic.w r2, r2, #1
80003f8: 615a str r2, [r3, #20]
huart->gState = HAL_UART_STATE_READY;
80003fa: 68fb ldr r3, [r7, #12]
80003fc: f8d3 3110 ldr.w r3, [r3, #272] ; 0x110
8000400: 2220 movs r2, #32
8000402: f883 203d strb.w r2, [r3, #61] ; 0x3d
huart->RxState = HAL_UART_STATE_READY;
8000406: 68fb ldr r3, [r7, #12]
8000408: f8d3 3110 ldr.w r3, [r3, #272] ; 0x110
800040c: 2220 movs r2, #32
800040e: f883 203e strb.w r2, [r3, #62] ; 0x3e
/* Process Unlocked */
__HAL_UNLOCK(huart);
8000412: 68fb ldr r3, [r7, #12]
8000414: f8d3 3110 ldr.w r3, [r3, #272] ; 0x110
8000418: 2200 movs r2, #0
800041a: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_TIMEOUT;
800041e: 2303 movs r3, #3
8000420: e000 b.n 8000424 <_ZN7ESP826626wait_on_flag_until_timeoutEm10FlagStatusmm+0xbc>
}
}
}
return HAL_OK;
8000422: 2300 movs r3, #0
}
8000424: 4618 mov r0, r3
8000426: 3710 adds r7, #16
8000428: 46bd mov sp, r7
800042a: bd80 pop {r7, pc}
0800042c <_ZN7ESP826635uart_receive_until_termination_byteEPhthm>:
HAL_StatusTypeDef ESP8266::uart_receive_until_termination_byte(uint8_t *pData, uint16_t Size, uint8_t terminationByte, uint32_t Timeout) {
800042c: b580 push {r7, lr}
800042e: b088 sub sp, #32
8000430: af02 add r7, sp, #8
8000432: 60f8 str r0, [r7, #12]
8000434: 60b9 str r1, [r7, #8]
8000436: 4611 mov r1, r2
8000438: 461a mov r2, r3
800043a: 460b mov r3, r1
800043c: 80fb strh r3, [r7, #6]
800043e: 4613 mov r3, r2
8000440: 717b strb r3, [r7, #5]
uint32_t tickstart = 0U;
8000442: 2300 movs r3, #0
8000444: 617b str r3, [r7, #20]
/* Check that a Rx process is not already ongoing */
if (huart->RxState == HAL_UART_STATE_READY) {
8000446: 68fb ldr r3, [r7, #12]
8000448: f8d3 3110 ldr.w r3, [r3, #272] ; 0x110
800044c: f893 303e ldrb.w r3, [r3, #62] ; 0x3e
8000450: b2db uxtb r3, r3
8000452: 2b20 cmp r3, #32
8000454: bf0c ite eq
8000456: 2301 moveq r3, #1
8000458: 2300 movne r3, #0
800045a: b2db uxtb r3, r3
800045c: 2b00 cmp r3, #0
800045e: d075 beq.n 800054c <_ZN7ESP826635uart_receive_until_termination_byteEPhthm+0x120>
/* Process Locked */
__HAL_LOCK(huart);
8000460: 68fb ldr r3, [r7, #12]
8000462: f8d3 3110 ldr.w r3, [r3, #272] ; 0x110
8000466: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
800046a: 2b01 cmp r3, #1
800046c: d101 bne.n 8000472 <_ZN7ESP826635uart_receive_until_termination_byteEPhthm+0x46>
800046e: 2302 movs r3, #2
8000470: e06d b.n 800054e <_ZN7ESP826635uart_receive_until_termination_byteEPhthm+0x122>
8000472: 68fb ldr r3, [r7, #12]
8000474: f8d3 3110 ldr.w r3, [r3, #272] ; 0x110
8000478: 2201 movs r2, #1
800047a: f883 203c strb.w r2, [r3, #60] ; 0x3c
huart->ErrorCode = HAL_UART_ERROR_NONE;
800047e: 68fb ldr r3, [r7, #12]
8000480: f8d3 3110 ldr.w r3, [r3, #272] ; 0x110
8000484: 2200 movs r2, #0
8000486: 641a str r2, [r3, #64] ; 0x40
huart->RxState = HAL_UART_STATE_BUSY_RX;
8000488: 68fb ldr r3, [r7, #12]
800048a: f8d3 3110 ldr.w r3, [r3, #272] ; 0x110
800048e: 2222 movs r2, #34 ; 0x22
8000490: f883 203e strb.w r2, [r3, #62] ; 0x3e
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8000494: 68fb ldr r3, [r7, #12]
8000496: f8d3 3110 ldr.w r3, [r3, #272] ; 0x110
800049a: 2200 movs r2, #0
800049c: 631a str r2, [r3, #48] ; 0x30
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
800049e: f001 f9f3 bl 8001888 <HAL_GetTick>
80004a2: 6178 str r0, [r7, #20]
huart->RxXferSize = Size;
80004a4: 68fb ldr r3, [r7, #12]
80004a6: f8d3 3110 ldr.w r3, [r3, #272] ; 0x110
80004aa: 88fa ldrh r2, [r7, #6]
80004ac: 859a strh r2, [r3, #44] ; 0x2c
huart->RxXferCount = Size;
80004ae: 68fb ldr r3, [r7, #12]
80004b0: f8d3 3110 ldr.w r3, [r3, #272] ; 0x110
80004b4: 88fa ldrh r2, [r7, #6]
80004b6: 85da strh r2, [r3, #46] ; 0x2e
/* Process Unlocked */
__HAL_UNLOCK(huart);
80004b8: 68fb ldr r3, [r7, #12]
80004ba: f8d3 3110 ldr.w r3, [r3, #272] ; 0x110
80004be: 2200 movs r2, #0
80004c0: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Check the remain data to be received */
while (huart->RxXferCount > 0U) {
80004c4: 68fb ldr r3, [r7, #12]
80004c6: f8d3 3110 ldr.w r3, [r3, #272] ; 0x110
80004ca: 8ddb ldrh r3, [r3, #46] ; 0x2e
80004cc: b29b uxth r3, r3
80004ce: 2b00 cmp r3, #0
80004d0: bf14 ite ne
80004d2: 2301 movne r3, #1
80004d4: 2300 moveq r3, #0
80004d6: b2db uxtb r3, r3
80004d8: 2b00 cmp r3, #0
80004da: d02f beq.n 800053c <_ZN7ESP826635uart_receive_until_termination_byteEPhthm+0x110>
if (wait_on_flag_until_timeout(UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) {
80004dc: 6a3b ldr r3, [r7, #32]
80004de: 9300 str r3, [sp, #0]
80004e0: 697b ldr r3, [r7, #20]
80004e2: 2200 movs r2, #0
80004e4: 2120 movs r1, #32
80004e6: 68f8 ldr r0, [r7, #12]
80004e8: f7ff ff3e bl 8000368 <_ZN7ESP826626wait_on_flag_until_timeoutEm10FlagStatusmm>
80004ec: 4603 mov r3, r0
80004ee: 2b00 cmp r3, #0
80004f0: bf14 ite ne
80004f2: 2301 movne r3, #1
80004f4: 2300 moveq r3, #0
80004f6: b2db uxtb r3, r3
80004f8: 2b00 cmp r3, #0
80004fa: d001 beq.n 8000500 <_ZN7ESP826635uart_receive_until_termination_byteEPhthm+0xd4>
return HAL_TIMEOUT;
80004fc: 2303 movs r3, #3
80004fe: e026 b.n 800054e <_ZN7ESP826635uart_receive_until_termination_byteEPhthm+0x122>
}
*pData = (uint8_t) (huart->Instance->DR & (uint8_t) 0x00FF);
8000500: 68fb ldr r3, [r7, #12]
8000502: f8d3 3110 ldr.w r3, [r3, #272] ; 0x110
8000506: 681b ldr r3, [r3, #0]
8000508: 685b ldr r3, [r3, #4]
800050a: b2da uxtb r2, r3
800050c: 68bb ldr r3, [r7, #8]
800050e: 701a strb r2, [r3, #0]
huart->RxXferCount--;
8000510: 68fb ldr r3, [r7, #12]
8000512: f8d3 3110 ldr.w r3, [r3, #272] ; 0x110
8000516: 8dda ldrh r2, [r3, #46] ; 0x2e
8000518: b292 uxth r2, r2
800051a: 3a01 subs r2, #1
800051c: b292 uxth r2, r2
800051e: 85da strh r2, [r3, #46] ; 0x2e
if (*pData == terminationByte) {
8000520: 68bb ldr r3, [r7, #8]
8000522: 781b ldrb r3, [r3, #0]
8000524: 797a ldrb r2, [r7, #5]
8000526: 429a cmp r2, r3
8000528: d104 bne.n 8000534 <_ZN7ESP826635uart_receive_until_termination_byteEPhthm+0x108>
pData[1] = 0; //Coloca o zero no final da string
800052a: 68bb ldr r3, [r7, #8]
800052c: 3301 adds r3, #1
800052e: 2200 movs r2, #0
8000530: 701a strb r2, [r3, #0]
break;
8000532: e003 b.n 800053c <_ZN7ESP826635uart_receive_until_termination_byteEPhthm+0x110>
}
pData++;
8000534: 68bb ldr r3, [r7, #8]
8000536: 3301 adds r3, #1
8000538: 60bb str r3, [r7, #8]
while (huart->RxXferCount > 0U) {
800053a: e7c3 b.n 80004c4 <_ZN7ESP826635uart_receive_until_termination_byteEPhthm+0x98>
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
800053c: 68fb ldr r3, [r7, #12]
800053e: f8d3 3110 ldr.w r3, [r3, #272] ; 0x110
8000542: 2220 movs r2, #32
8000544: f883 203e strb.w r2, [r3, #62] ; 0x3e
return HAL_OK;
8000548: 2300 movs r3, #0
800054a: e000 b.n 800054e <_ZN7ESP826635uart_receive_until_termination_byteEPhthm+0x122>
} else {
return HAL_BUSY;
800054c: 2302 movs r3, #2
}
}
800054e: 4618 mov r0, r3
8000550: 3718 adds r7, #24
8000552: 46bd mov sp, r7
8000554: bd80 pop {r7, pc}
...
08000558 <_ZN7ESP826613wait_until_okEv>:
ESP8266::statusTypeDef ESP8266::wait_until_ok() {
8000558: b580 push {r7, lr}
800055a: b084 sub sp, #16
800055c: af02 add r7, sp, #8
800055e: 6078 str r0, [r7, #4]
HAL_UART_AbortReceive_IT(huart);
8000560: 687b ldr r3, [r7, #4]
8000562: f8d3 3110 ldr.w r3, [r3, #272] ; 0x110
8000566: 4618 mov r0, r3
8000568: f003 feaa bl 80042c0 <HAL_UART_AbortReceive_IT>
while(uart_receive_until_termination_byte(buffer, MAX_BUFFER_SIZE, '\n', OK_TIMEOUT) != HAL_TIMEOUT){
800056c: 687b ldr r3, [r7, #4]
800056e: f503 718a add.w r1, r3, #276 ; 0x114
8000572: f241 3388 movw r3, #5000 ; 0x1388
8000576: 9300 str r3, [sp, #0]
8000578: 230a movs r3, #10
800057a: f44f 7280 mov.w r2, #256 ; 0x100
800057e: 6878 ldr r0, [r7, #4]
8000580: f7ff ff54 bl 800042c <_ZN7ESP826635uart_receive_until_termination_byteEPhthm>
8000584: 4603 mov r3, r0
8000586: 2b03 cmp r3, #3
8000588: bf14 ite ne
800058a: 2301 movne r3, #1
800058c: 2300 moveq r3, #0
800058e: b2db uxtb r3, r3
8000590: 2b00 cmp r3, #0
8000592: d01e beq.n 80005d2 <_ZN7ESP826613wait_until_okEv+0x7a>
if(!strcmp((char*) buffer, "OK\r\n")){
8000594: 687b ldr r3, [r7, #4]
8000596: f503 738a add.w r3, r3, #276 ; 0x114
800059a: 4910 ldr r1, [pc, #64] ; (80005dc <_ZN7ESP826613wait_until_okEv+0x84>)
800059c: 4618 mov r0, r3
800059e: f7ff fdd5 bl 800014c <strcmp>
80005a2: 4603 mov r3, r0
80005a4: 2b00 cmp r3, #0
80005a6: d101 bne.n 80005ac <_ZN7ESP826613wait_until_okEv+0x54>
return STATUS_OK;
80005a8: 2300 movs r3, #0
80005aa: e013 b.n 80005d4 <_ZN7ESP826613wait_until_okEv+0x7c>
}
if(!strcmp((char*) buffer, "ERROR\r\n")){
80005ac: 687b ldr r3, [r7, #4]
80005ae: f503 738a add.w r3, r3, #276 ; 0x114
80005b2: 490b ldr r1, [pc, #44] ; (80005e0 <_ZN7ESP826613wait_until_okEv+0x88>)
80005b4: 4618 mov r0, r3
80005b6: f7ff fdc9 bl 800014c <strcmp>
80005ba: 4603 mov r3, r0
80005bc: 2b00 cmp r3, #0
80005be: d101 bne.n 80005c4 <_ZN7ESP826613wait_until_okEv+0x6c>
return STATUS_ERROR;
80005c0: 2301 movs r3, #1
80005c2: e007 b.n 80005d4 <_ZN7ESP826613wait_until_okEv+0x7c>
}
if(buffer[0] == '+'){
80005c4: 687b ldr r3, [r7, #4]
80005c6: f893 3114 ldrb.w r3, [r3, #276] ; 0x114
80005ca: 2b2b cmp r3, #43 ; 0x2b
80005cc: d1ce bne.n 800056c <_ZN7ESP826613wait_until_okEv+0x14>
__NOP();
80005ce: bf00 nop
while(uart_receive_until_termination_byte(buffer, MAX_BUFFER_SIZE, '\n', OK_TIMEOUT) != HAL_TIMEOUT){
80005d0: e7cc b.n 800056c <_ZN7ESP826613wait_until_okEv+0x14>
}
}
return STATUS_TIMEOUT;
80005d2: 2302 movs r3, #2
}
80005d4: 4618 mov r0, r3
80005d6: 3708 adds r7, #8
80005d8: 46bd mov sp, r7
80005da: bd80 pop {r7, pc}
80005dc: 080058e0 .word 0x080058e0
80005e0: 080058e8 .word 0x080058e8
080005e4 <_ZN7ESP826618wait_until_send_okEv>:
ESP8266::statusTypeDef ESP8266::wait_until_send_ok() {
80005e4: b580 push {r7, lr}
80005e6: b084 sub sp, #16
80005e8: af02 add r7, sp, #8
80005ea: 6078 str r0, [r7, #4]
HAL_UART_AbortReceive_IT(huart);
80005ec: 687b ldr r3, [r7, #4]
80005ee: f8d3 3110 ldr.w r3, [r3, #272] ; 0x110
80005f2: 4618 mov r0, r3
80005f4: f003 fe64 bl 80042c0 <HAL_UART_AbortReceive_IT>
while(uart_receive_until_termination_byte(buffer, MAX_BUFFER_SIZE, '\n', OK_TIMEOUT) != HAL_TIMEOUT){
80005f8: 687b ldr r3, [r7, #4]
80005fa: f503 718a add.w r1, r3, #276 ; 0x114
80005fe: f241 3388 movw r3, #5000 ; 0x1388
8000602: 9300 str r3, [sp, #0]
8000604: 230a movs r3, #10
8000606: f44f 7280 mov.w r2, #256 ; 0x100
800060a: 6878 ldr r0, [r7, #4]
800060c: f7ff ff0e bl 800042c <_ZN7ESP826635uart_receive_until_termination_byteEPhthm>
8000610: 4603 mov r3, r0
8000612: 2b03 cmp r3, #3
8000614: bf14 ite ne
8000616: 2301 movne r3, #1
8000618: 2300 moveq r3, #0
800061a: b2db uxtb r3, r3
800061c: 2b00 cmp r3, #0
800061e: d01e beq.n 800065e <_ZN7ESP826618wait_until_send_okEv+0x7a>
if(!strcmp((char*) buffer, "SEND OK\r\n")){
8000620: 687b ldr r3, [r7, #4]
8000622: f503 738a add.w r3, r3, #276 ; 0x114
8000626: 4910 ldr r1, [pc, #64] ; (8000668 <_ZN7ESP826618wait_until_send_okEv+0x84>)
8000628: 4618 mov r0, r3
800062a: f7ff fd8f bl 800014c <strcmp>
800062e: 4603 mov r3, r0
8000630: 2b00 cmp r3, #0
8000632: d101 bne.n 8000638 <_ZN7ESP826618wait_until_send_okEv+0x54>
return STATUS_OK;
8000634: 2300 movs r3, #0
8000636: e013 b.n 8000660 <_ZN7ESP826618wait_until_send_okEv+0x7c>
}
if(!strcmp((char*) buffer, "SEND ERROR\r\n")){
8000638: 687b ldr r3, [r7, #4]
800063a: f503 738a add.w r3, r3, #276 ; 0x114
800063e: 490b ldr r1, [pc, #44] ; (800066c <_ZN7ESP826618wait_until_send_okEv+0x88>)
8000640: 4618 mov r0, r3
8000642: f7ff fd83 bl 800014c <strcmp>
8000646: 4603 mov r3, r0
8000648: 2b00 cmp r3, #0
800064a: d101 bne.n 8000650 <_ZN7ESP826618wait_until_send_okEv+0x6c>
return STATUS_ERROR;
800064c: 2301 movs r3, #1
800064e: e007 b.n 8000660 <_ZN7ESP826618wait_until_send_okEv+0x7c>
}
if(buffer[0] == '+'){
8000650: 687b ldr r3, [r7, #4]
8000652: f893 3114 ldrb.w r3, [r3, #276] ; 0x114
8000656: 2b2b cmp r3, #43 ; 0x2b
8000658: d1ce bne.n 80005f8 <_ZN7ESP826618wait_until_send_okEv+0x14>
__NOP();
800065a: bf00 nop
while(uart_receive_until_termination_byte(buffer, MAX_BUFFER_SIZE, '\n', OK_TIMEOUT) != HAL_TIMEOUT){
800065c: e7cc b.n 80005f8 <_ZN7ESP826618wait_until_send_okEv+0x14>
}
}
return STATUS_TIMEOUT;
800065e: 2302 movs r3, #2
}
8000660: 4618 mov r0, r3
8000662: 3708 adds r7, #8
8000664: 46bd mov sp, r7
8000666: bd80 pop {r7, pc}
8000668: 080058f0 .word 0x080058f0
800066c: 080058fc .word 0x080058fc
08000670 <_ZN11SerialDebugC1EP20__UART_HandleTypeDefm>:
*/
#include "SerialDebug.hpp"
#include <string.h>
SerialDebug::SerialDebug(UART_HandleTypeDef* huartptr, uint32_t fifoSize)
8000670: b590 push {r4, r7, lr}
8000672: b085 sub sp, #20
8000674: af00 add r7, sp, #0
8000676: 60f8 str r0, [r7, #12]
8000678: 60b9 str r1, [r7, #8]
800067a: 607a str r2, [r7, #4]
: huartptr(huartptr)
800067c: 68fb ldr r3, [r7, #12]
800067e: 2200 movs r2, #0
8000680: 711a strb r2, [r3, #4]
8000682: 68fb ldr r3, [r7, #12]
8000684: 68ba ldr r2, [r7, #8]
8000686: 609a str r2, [r3, #8]
8000688: 68fb ldr r3, [r7, #12]
800068a: 2203 movs r2, #3
800068c: f883 210c strb.w r2, [r3, #268] ; 0x10c
{
fifo = new StaticFIFO(fifoSize);
8000690: 2014 movs r0, #20
8000692: f004 fb91 bl 8004db8 <_Znwj>
8000696: 4603 mov r3, r0
8000698: 461c mov r4, r3
800069a: 6879 ldr r1, [r7, #4]
800069c: 4620 mov r0, r4
800069e: f000 f99b bl 80009d8 <_ZN10StaticFIFOC1Em>
80006a2: 68fb ldr r3, [r7, #12]
80006a4: 601c str r4, [r3, #0]
}
80006a6: 68fb ldr r3, [r7, #12]
80006a8: 4618 mov r0, r3
80006aa: 3714 adds r7, #20
80006ac: 46bd mov sp, r7
80006ae: bd90 pop {r4, r7, pc}
080006b0 <_ZN11SerialDebug8setLevelENS_10DebugLevelE>:
void SerialDebug::setLevel(DebugLevel level)
{
80006b0: b480 push {r7}
80006b2: b083 sub sp, #12
80006b4: af00 add r7, sp, #0
80006b6: 6078 str r0, [r7, #4]
80006b8: 460b mov r3, r1
80006ba: 70fb strb r3, [r7, #3]
debugLevel = level;
80006bc: 687b ldr r3, [r7, #4]
80006be: 78fa ldrb r2, [r7, #3]
80006c0: f883 210c strb.w r2, [r3, #268] ; 0x10c
}
80006c4: bf00 nop
80006c6: 370c adds r7, #12
80006c8: 46bd mov sp, r7
80006ca: bc80 pop {r7}
80006cc: 4770 bx lr
080006ce <_ZN11SerialDebug20serialTxCpltCallbackEv>:
void SerialDebug::serialTxCpltCallback(){
80006ce: b580 push {r7, lr}
80006d0: b084 sub sp, #16
80006d2: af00 add r7, sp, #0
80006d4: 6078 str r0, [r7, #4]
uint32_t numChars;
uint8_t* pointer;
if (fifo->pop(&pointer, &numChars, bufSize) >= 0){
80006d6: 687b ldr r3, [r7, #4]
80006d8: 6818 ldr r0, [r3, #0]
80006da: f107 020c add.w r2, r7, #12
80006de: f107 0108 add.w r1, r7, #8
80006e2: 2380 movs r3, #128 ; 0x80
80006e4: f000 fa35 bl 8000b52 <_ZN10StaticFIFO3popEPPhPmm>
80006e8: 4603 mov r3, r0
80006ea: 43db mvns r3, r3
80006ec: 0fdb lsrs r3, r3, #31
80006ee: b2db uxtb r3, r3
80006f0: 2b00 cmp r3, #0
80006f2: d00f beq.n 8000714 <_ZN11SerialDebug20serialTxCpltCallbackEv+0x46>
memcpy(uartBuf, pointer, numChars);
80006f4: 687b ldr r3, [r7, #4]
80006f6: 338c adds r3, #140 ; 0x8c
80006f8: 68b9 ldr r1, [r7, #8]
80006fa: 68fa ldr r2, [r7, #12]
80006fc: 4618 mov r0, r3
80006fe: f004 fbbb bl 8004e78 <memcpy>
HAL_UART_Transmit_DMA(huartptr, pointer, (uint16_t)numChars);
8000702: 687b ldr r3, [r7, #4]
8000704: 689b ldr r3, [r3, #8]
8000706: 68b9 ldr r1, [r7, #8]
8000708: 68fa ldr r2, [r7, #12]
800070a: b292 uxth r2, r2
800070c: 4618 mov r0, r3
800070e: f003 fd6b bl 80041e8 <HAL_UART_Transmit_DMA>
}else{
transmitting = false;
}
}
8000712: e002 b.n 800071a <_ZN11SerialDebug20serialTxCpltCallbackEv+0x4c>
transmitting = false;
8000714: 687b ldr r3, [r7, #4]
8000716: 2200 movs r2, #0
8000718: 711a strb r2, [r3, #4]
}
800071a: bf00 nop
800071c: 3710 adds r7, #16
800071e: 46bd mov sp, r7
8000720: bd80 pop {r7, pc}
...
08000724 <_ZN11SerialDebug5debugEPKc>:
void SerialDebug::debug(const char* data){
8000724: b590 push {r4, r7, lr}
8000726: b085 sub sp, #20
8000728: af00 add r7, sp, #0
800072a: 6078 str r0, [r7, #4]
800072c: 6039 str r1, [r7, #0]
if (debugLevel <= DEBUG_LEVEL_DEBUG){
800072e: 687b ldr r3, [r7, #4]
8000730: f893 310c ldrb.w r3, [r3, #268] ; 0x10c
8000734: 2b00 cmp r3, #0
8000736: d130 bne.n 800079a <_ZN11SerialDebug5debugEPKc+0x76>
int numChars = sprintf(charBuf, "[%13lu] DBG: %.105s\r\n", HAL_GetTick(), data);
8000738: 687b ldr r3, [r7, #4]
800073a: f103 040c add.w r4, r3, #12
800073e: f001 f8a3 bl 8001888 <HAL_GetTick>
8000742: 4602 mov r2, r0
8000744: 683b ldr r3, [r7, #0]
8000746: 4917 ldr r1, [pc, #92] ; (80007a4 <_ZN11SerialDebug5debugEPKc+0x80>)
8000748: 4620 mov r0, r4
800074a: f004 fcdb bl 8005104 <siprintf>
800074e: 60f8 str r0, [r7, #12]
if(numChars > 0){
8000750: 68fb ldr r3, [r7, #12]
8000752: 2b00 cmp r3, #0
8000754: dd21 ble.n 800079a <_ZN11SerialDebug5debugEPKc+0x76>
if(transmitting){
8000756: 687b ldr r3, [r7, #4]
8000758: 791b ldrb r3, [r3, #4]
800075a: 2b00 cmp r3, #0
800075c: d008 beq.n 8000770 <_ZN11SerialDebug5debugEPKc+0x4c>
fifo->push(charBuf, numChars);
800075e: 687b ldr r3, [r7, #4]
8000760: 6818 ldr r0, [r3, #0]
8000762: 687b ldr r3, [r7, #4]
8000764: 330c adds r3, #12
8000766: 68fa ldr r2, [r7, #12]
8000768: 4619 mov r1, r3
800076a: f000 f987 bl 8000a7c <_ZN10StaticFIFO4pushEPcm>
memcpy(uartBuf, (uint8_t*)charBuf, numChars);
HAL_UART_Transmit_DMA(huartptr, uartBuf, (uint16_t)numChars);
}
}
}
}
800076e: e014 b.n 800079a <_ZN11SerialDebug5debugEPKc+0x76>
transmitting = true;
8000770: 687b ldr r3, [r7, #4]
8000772: 2201 movs r2, #1
8000774: 711a strb r2, [r3, #4]
memcpy(uartBuf, (uint8_t*)charBuf, numChars);
8000776: 687b ldr r3, [r7, #4]
8000778: f103 008c add.w r0, r3, #140 ; 0x8c
800077c: 687b ldr r3, [r7, #4]
800077e: 330c adds r3, #12
8000780: 68fa ldr r2, [r7, #12]
8000782: 4619 mov r1, r3
8000784: f004 fb78 bl 8004e78 <memcpy>
HAL_UART_Transmit_DMA(huartptr, uartBuf, (uint16_t)numChars);
8000788: 687b ldr r3, [r7, #4]
800078a: 6898 ldr r0, [r3, #8]
800078c: 687b ldr r3, [r7, #4]
800078e: 338c adds r3, #140 ; 0x8c
8000790: 68fa ldr r2, [r7, #12]
8000792: b292 uxth r2, r2
8000794: 4619 mov r1, r3
8000796: f003 fd27 bl 80041e8 <HAL_UART_Transmit_DMA>
}
800079a: bf00 nop
800079c: 3714 adds r7, #20
800079e: 46bd mov sp, r7
80007a0: bd90 pop {r4, r7, pc}
80007a2: bf00 nop
80007a4: 0800590c .word 0x0800590c
080007a8 <_ZN11SerialDebug4infoEPKc>:
void SerialDebug::info(const char* data){
80007a8: b590 push {r4, r7, lr}
80007aa: b085 sub sp, #20
80007ac: af00 add r7, sp, #0
80007ae: 6078 str r0, [r7, #4]
80007b0: 6039 str r1, [r7, #0]
if (debugLevel <= DEBUG_LEVEL_INFO){
80007b2: 687b ldr r3, [r7, #4]
80007b4: f893 310c ldrb.w r3, [r3, #268] ; 0x10c
80007b8: 2b01 cmp r3, #1
80007ba: d830 bhi.n 800081e <_ZN11SerialDebug4infoEPKc+0x76>
int numChars = sprintf(charBuf, "[%13lu] INF: %.105s\r\n", HAL_GetTick(), data);
80007bc: 687b ldr r3, [r7, #4]
80007be: f103 040c add.w r4, r3, #12
80007c2: f001 f861 bl 8001888 <HAL_GetTick>
80007c6: 4602 mov r2, r0
80007c8: 683b ldr r3, [r7, #0]
80007ca: 4917 ldr r1, [pc, #92] ; (8000828 <_ZN11SerialDebug4infoEPKc+0x80>)
80007cc: 4620 mov r0, r4
80007ce: f004 fc99 bl 8005104 <siprintf>
80007d2: 60f8 str r0, [r7, #12]
if(numChars > 0){
80007d4: 68fb ldr r3, [r7, #12]
80007d6: 2b00 cmp r3, #0
80007d8: dd21 ble.n 800081e <_ZN11SerialDebug4infoEPKc+0x76>
if(transmitting){
80007da: 687b ldr r3, [r7, #4]
80007dc: 791b ldrb r3, [r3, #4]
80007de: 2b00 cmp r3, #0
80007e0: d008 beq.n 80007f4 <_ZN11SerialDebug4infoEPKc+0x4c>
fifo->push(charBuf, numChars);
80007e2: 687b ldr r3, [r7, #4]
80007e4: 6818 ldr r0, [r3, #0]
80007e6: 687b ldr r3, [r7, #4]
80007e8: 330c adds r3, #12
80007ea: 68fa ldr r2, [r7, #12]
80007ec: 4619 mov r1, r3
80007ee: f000 f945 bl 8000a7c <_ZN10StaticFIFO4pushEPcm>
memcpy(uartBuf, (uint8_t*)charBuf, numChars);
HAL_UART_Transmit_DMA(huartptr, uartBuf, (uint16_t)numChars);
}
}
}
}
80007f2: e014 b.n 800081e <_ZN11SerialDebug4infoEPKc+0x76>
transmitting = true;
80007f4: 687b ldr r3, [r7, #4]
80007f6: 2201 movs r2, #1
80007f8: 711a strb r2, [r3, #4]
memcpy(uartBuf, (uint8_t*)charBuf, numChars);
80007fa: 687b ldr r3, [r7, #4]
80007fc: f103 008c add.w r0, r3, #140 ; 0x8c
8000800: 687b ldr r3, [r7, #4]
8000802: 330c adds r3, #12
8000804: 68fa ldr r2, [r7, #12]
8000806: 4619 mov r1, r3
8000808: f004 fb36 bl 8004e78 <memcpy>
HAL_UART_Transmit_DMA(huartptr, uartBuf, (uint16_t)numChars);
800080c: 687b ldr r3, [r7, #4]
800080e: 6898 ldr r0, [r3, #8]
8000810: 687b ldr r3, [r7, #4]
8000812: 338c adds r3, #140 ; 0x8c
8000814: 68fa ldr r2, [r7, #12]
8000816: b292 uxth r2, r2
8000818: 4619 mov r1, r3
800081a: f003 fce5 bl 80041e8 <HAL_UART_Transmit_DMA>
}
800081e: bf00 nop
8000820: 3714 adds r7, #20
8000822: 46bd mov sp, r7
8000824: bd90 pop {r4, r7, pc}
8000826: bf00 nop
8000828: 08005924 .word 0x08005924
0800082c <HAL_TIM_PeriodElapsedCallback>:
//Temporary variables begin
char buf[64];
//Temporary Variables end
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim){
800082c: b480 push {r7}
800082e: b083 sub sp, #12
8000830: af00 add r7, sp, #0
8000832: 6078 str r0, [r7, #4]
if(htim==&htim4){
}
}
8000834: bf00 nop
8000836: 370c adds r7, #12
8000838: 46bd mov sp, r7
800083a: bc80 pop {r7}
800083c: 4770 bx lr
...
08000840 <HAL_UART_TxCpltCallback>:
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
8000840: b580 push {r7, lr}
8000842: b082 sub sp, #8
8000844: af00 add r7, sp, #0
8000846: 6078 str r0, [r7, #4]
if(huart == &huart2){
8000848: 687b ldr r3, [r7, #4]
800084a: 4a05 ldr r2, [pc, #20] ; (8000860 <HAL_UART_TxCpltCallback+0x20>)
800084c: 4293 cmp r3, r2
800084e: d102 bne.n 8000856 <HAL_UART_TxCpltCallback+0x16>
debug.serialTxCpltCallback();
8000850: 4804 ldr r0, [pc, #16] ; (8000864 <HAL_UART_TxCpltCallback+0x24>)
8000852: f7ff ff3c bl 80006ce <_ZN11SerialDebug20serialTxCpltCallbackEv>
}
}
8000856: bf00 nop
8000858: 3708 adds r7, #8
800085a: 46bd mov sp, r7
800085c: bd80 pop {r7, pc}
800085e: bf00 nop
8000860: 20000514 .word 0x20000514
8000864: 2000008c .word 0x2000008c
08000868 <start>:
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) {
}
void start(){
8000868: b580 push {r7, lr}
800086a: af00 add r7, sp, #0
debug.setLevel(SerialDebug::DEBUG_LEVEL_DEBUG);
800086c: 2100 movs r1, #0
800086e: 482a ldr r0, [pc, #168] ; (8000918 <start+0xb0>)
8000870: f7ff ff1e bl 80006b0 <_ZN11SerialDebug8setLevelENS_10DebugLevelE>
debug.info("-----Init-----");
8000874: 4929 ldr r1, [pc, #164] ; (800091c <start+0xb4>)
8000876: 4828 ldr r0, [pc, #160] ; (8000918 <start+0xb0>)
8000878: f7ff ff96 bl 80007a8 <_ZN11SerialDebug4infoEPKc>
debug.info("Init timers begin");
800087c: 4928 ldr r1, [pc, #160] ; (8000920 <start+0xb8>)
800087e: 4826 ldr r0, [pc, #152] ; (8000918 <start+0xb0>)
8000880: f7ff ff92 bl 80007a8 <_ZN11SerialDebug4infoEPKc>
//HAL_TIM_Encoder_Start(&htim1, TIM_CHANNEL_1);
HAL_TIM_Encoder_Start(&htim1, TIM_CHANNEL_ALL);
8000884: 213c movs r1, #60 ; 0x3c
8000886: 4827 ldr r0, [pc, #156] ; (8000924 <start+0xbc>)
8000888: f002 fd7e bl 8003388 <HAL_TIM_Encoder_Start>
//HAL_TIM_Encoder_Start(&htim3, TIM_CHANNEL_1);
HAL_TIM_Encoder_Start(&htim3, TIM_CHANNEL_ALL);
800088c: 213c movs r1, #60 ; 0x3c
800088e: 4826 ldr r0, [pc, #152] ; (8000928 <start+0xc0>)
8000890: f002 fd7a bl 8003388 <HAL_TIM_Encoder_Start>
HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_ALL);
8000894: 213c movs r1, #60 ; 0x3c
8000896: 4825 ldr r0, [pc, #148] ; (800092c <start+0xc4>)
8000898: f002 fc32 bl 8003100 <HAL_TIM_PWM_Start>
HAL_TIM_Base_Start(&htim4);
800089c: 4824 ldr r0, [pc, #144] ; (8000930 <start+0xc8>)
800089e: f002 fb95 bl 8002fcc <HAL_TIM_Base_Start>
debug.info("Init timers end");
80008a2: 4924 ldr r1, [pc, #144] ; (8000934 <start+0xcc>)
80008a4: 481c ldr r0, [pc, #112] ; (8000918 <start+0xb0>)
80008a6: f7ff ff7f bl 80007a8 <_ZN11SerialDebug4infoEPKc>
debug.info("Init ESP8266 begin");
80008aa: 4923 ldr r1, [pc, #140] ; (8000938 <start+0xd0>)
80008ac: 481a ldr r0, [pc, #104] ; (8000918 <start+0xb0>)
80008ae: f7ff ff7b bl 80007a8 <_ZN11SerialDebug4infoEPKc>
HAL_Delay(1000);
80008b2: f44f 707a mov.w r0, #1000 ; 0x3e8
80008b6: f000 fff1 bl 800189c <HAL_Delay>
switch(esp0.command("ATE1\r\n")){
80008ba: 4920 ldr r1, [pc, #128] ; (800093c <start+0xd4>)
80008bc: 4820 ldr r0, [pc, #128] ; (8000940 <start+0xd8>)
80008be: f7ff fcb3 bl 8000228 <_ZN7ESP82667commandEPKc>
80008c2: 4603 mov r3, r0
80008c4: 2b02 cmp r3, #2
80008c6: d010 beq.n 80008ea <start+0x82>
80008c8: 2b02 cmp r3, #2
80008ca: dc13 bgt.n 80008f4 <start+0x8c>
80008cc: 2b00 cmp r3, #0
80008ce: d002 beq.n 80008d6 <start+0x6e>
80008d0: 2b01 cmp r3, #1
80008d2: d005 beq.n 80008e0 <start+0x78>
80008d4: e00e b.n 80008f4 <start+0x8c>
case ESP8266::STATUS_OK:
debug.debug("ATE0 OK");
80008d6: 491b ldr r1, [pc, #108] ; (8000944 <start+0xdc>)
80008d8: 480f ldr r0, [pc, #60] ; (8000918 <start+0xb0>)
80008da: f7ff ff23 bl 8000724 <_ZN11SerialDebug5debugEPKc>
break;
80008de: e009 b.n 80008f4 <start+0x8c>
case ESP8266::STATUS_ERROR:
debug.debug("ATE0 ERROR");
80008e0: 4919 ldr r1, [pc, #100] ; (8000948 <start+0xe0>)
80008e2: 480d ldr r0, [pc, #52] ; (8000918 <start+0xb0>)
80008e4: f7ff ff1e bl 8000724 <_ZN11SerialDebug5debugEPKc>
break;
80008e8: e004 b.n 80008f4 <start+0x8c>
case ESP8266::STATUS_TIMEOUT:
debug.debug("ATE0 TIMEOUT");
80008ea: 4918 ldr r1, [pc, #96] ; (800094c <start+0xe4>)
80008ec: 480a ldr r0, [pc, #40] ; (8000918 <start+0xb0>)
80008ee: f7ff ff19 bl 8000724 <_ZN11SerialDebug5debugEPKc>
break;
80008f2: bf00 nop
}
esp0.init();
80008f4: 4812 ldr r0, [pc, #72] ; (8000940 <start+0xd8>)
80008f6: f7ff fc71 bl 80001dc <_ZN7ESP82664initEv>
//+IPD,0,14:Hello World 01\r\n
debug.info("Init ESP8266 end");
80008fa: 4915 ldr r1, [pc, #84] ; (8000950 <start+0xe8>)
80008fc: 4806 ldr r0, [pc, #24] ; (8000918 <start+0xb0>)
80008fe: f7ff ff53 bl 80007a8 <_ZN11SerialDebug4infoEPKc>
while(true){
esp0.send_uint32("TIM1->CNT", TIM1->CNT);
8000902: 4b14 ldr r3, [pc, #80] ; (8000954 <start+0xec>)
8000904: 6a5b ldr r3, [r3, #36] ; 0x24
8000906: 461a mov r2, r3
8000908: 4913 ldr r1, [pc, #76] ; (8000958 <start+0xf0>)
800090a: 480d ldr r0, [pc, #52] ; (8000940 <start+0xd8>)
800090c: f7ff fcc0 bl 8000290 <_ZN7ESP826611send_uint32EPKcm>
esp0.receive_uint32();
8000910: 480b ldr r0, [pc, #44] ; (8000940 <start+0xd8>)
8000912: f7ff fd09 bl 8000328 <_ZN7ESP826614receive_uint32Ev>
esp0.send_uint32("TIM1->CNT", TIM1->CNT);
8000916: e7f4 b.n 8000902 <start+0x9a>
8000918: 2000008c .word 0x2000008c
800091c: 0800596c .word 0x0800596c
8000920: 0800597c .word 0x0800597c
8000924: 200003b0 .word 0x200003b0
8000928: 20000440 .word 0x20000440
800092c: 200003f8 .word 0x200003f8
8000930: 20000488 .word 0x20000488
8000934: 08005990 .word 0x08005990
8000938: 080059a0 .word 0x080059a0
800093c: 080059b4 .word 0x080059b4
8000940: 2000019c .word 0x2000019c
8000944: 080059bc .word 0x080059bc
8000948: 080059c4 .word 0x080059c4
800094c: 080059d0 .word 0x080059d0
8000950: 080059e0 .word 0x080059e0
8000954: 40012c00 .word 0x40012c00
8000958: 080059f4 .word 0x080059f4
0800095c <_Z41__static_initialization_and_destruction_0ii>:
/*sprintf(buf, "TIM1->CNT: %lu", TIM1->CNT);
debug.debug(buf);*/
//HAL_Delay(10);
}
}
800095c: b580 push {r7, lr}
800095e: b082 sub sp, #8
8000960: af00 add r7, sp, #0
8000962: 6078 str r0, [r7, #4]
8000964: 6039 str r1, [r7, #0]
8000966: 687b ldr r3, [r7, #4]
8000968: 2b01 cmp r3, #1
800096a: d10d bne.n 8000988 <_Z41__static_initialization_and_destruction_0ii+0x2c>
800096c: 683b ldr r3, [r7, #0]
800096e: f64f 72ff movw r2, #65535 ; 0xffff
8000972: 4293 cmp r3, r2
8000974: d108 bne.n 8000988 <_Z41__static_initialization_and_destruction_0ii+0x2c>
SerialDebug debug(&huart2, 32);
8000976: 2220 movs r2, #32
8000978: 490b ldr r1, [pc, #44] ; (80009a8 <_Z41__static_initialization_and_destruction_0ii+0x4c>)
800097a: 480c ldr r0, [pc, #48] ; (80009ac <_Z41__static_initialization_and_destruction_0ii+0x50>)
800097c: f7ff fe78 bl 8000670 <_ZN11SerialDebugC1EP20__UART_HandleTypeDefm>
ESP8266 esp0(&huart1);
8000980: 490b ldr r1, [pc, #44] ; (80009b0 <_Z41__static_initialization_and_destruction_0ii+0x54>)
8000982: 480c ldr r0, [pc, #48] ; (80009b4 <_Z41__static_initialization_and_destruction_0ii+0x58>)
8000984: f7ff fbf4 bl 8000170 <_ZN7ESP8266C1EP20__UART_HandleTypeDef>
8000988: 687b ldr r3, [r7, #4]
800098a: 2b00 cmp r3, #0
800098c: d107 bne.n 800099e <_Z41__static_initialization_and_destruction_0ii+0x42>
800098e: 683b ldr r3, [r7, #0]
8000990: f64f 72ff movw r2, #65535 ; 0xffff
8000994: 4293 cmp r3, r2
8000996: d102 bne.n 800099e <_Z41__static_initialization_and_destruction_0ii+0x42>
8000998: 4806 ldr r0, [pc, #24] ; (80009b4 <_Z41__static_initialization_and_destruction_0ii+0x58>)
800099a: f7ff fbfd bl 8000198 <_ZN7ESP8266D1Ev>
}
800099e: bf00 nop
80009a0: 3708 adds r7, #8
80009a2: 46bd mov sp, r7
80009a4: bd80 pop {r7, pc}
80009a6: bf00 nop
80009a8: 20000514 .word 0x20000514
80009ac: 2000008c .word 0x2000008c
80009b0: 200004d0 .word 0x200004d0
80009b4: 2000019c .word 0x2000019c
080009b8 <_GLOBAL__sub_I_debug>:
80009b8: b580 push {r7, lr}
80009ba: af00 add r7, sp, #0
80009bc: f64f 71ff movw r1, #65535 ; 0xffff
80009c0: 2001 movs r0, #1
80009c2: f7ff ffcb bl 800095c <_Z41__static_initialization_and_destruction_0ii>
80009c6: bd80 pop {r7, pc}
080009c8 <_GLOBAL__sub_D_debug>:
80009c8: b580 push {r7, lr}
80009ca: af00 add r7, sp, #0
80009cc: f64f 71ff movw r1, #65535 ; 0xffff
80009d0: 2000 movs r0, #0
80009d2: f7ff ffc3 bl 800095c <_Z41__static_initialization_and_destruction_0ii>
80009d6: bd80 pop {r7, pc}
080009d8 <_ZN10StaticFIFOC1Em>:
#include "StaticFIFO.hpp"
#include <cstring>
StaticFIFO::StaticFIFO(uint32_t fifoSize) : fifoSize(fifoSize){
80009d8: b580 push {r7, lr}
80009da: b082 sub sp, #8
80009dc: af00 add r7, sp, #0
80009de: 6078 str r0, [r7, #4]
80009e0: 6039 str r1, [r7, #0]
80009e2: 4a11 ldr r2, [pc, #68] ; (8000a28 <_ZN10StaticFIFOC1Em+0x50>)
80009e4: 687b ldr r3, [r7, #4]
80009e6: 601a str r2, [r3, #0]
80009e8: 687b ldr r3, [r7, #4]
80009ea: 683a ldr r2, [r7, #0]
80009ec: 605a str r2, [r3, #4]
80009ee: 687b ldr r3, [r7, #4]
80009f0: 2200 movs r2, #0
80009f2: 60da str r2, [r3, #12]
80009f4: 687b ldr r3, [r7, #4]
80009f6: 2200 movs r2, #0
80009f8: 611a str r2, [r3, #16]
fifo = new StringContainer[fifoSize];
80009fa: 683a ldr r2, [r7, #0]
80009fc: 4b0b ldr r3, [pc, #44] ; (8000a2c <_ZN10StaticFIFOC1Em+0x54>)
80009fe: 429a cmp r2, r3
8000a00: d804 bhi.n 8000a0c <_ZN10StaticFIFOC1Em+0x34>
8000a02: 4613 mov r3, r2
8000a04: 015b lsls r3, r3, #5
8000a06: 4413 add r3, r2
8000a08: 009b lsls r3, r3, #2
8000a0a: e001 b.n 8000a10 <_ZN10StaticFIFOC1Em+0x38>
8000a0c: f04f 33ff mov.w r3, #4294967295
8000a10: 4618 mov r0, r3
8000a12: f004 f9e2 bl 8004dda <_Znaj>
8000a16: 4603 mov r3, r0
8000a18: 461a mov r2, r3
8000a1a: 687b ldr r3, [r7, #4]
8000a1c: 609a str r2, [r3, #8]
}
8000a1e: 687b ldr r3, [r7, #4]
8000a20: 4618 mov r0, r3
8000a22: 3708 adds r7, #8
8000a24: 46bd mov sp, r7
8000a26: bd80 pop {r7, pc}
8000a28: 08005a28 .word 0x08005a28
8000a2c: 00f83e0f .word 0x00f83e0f
08000a30 <_ZN10StaticFIFOD1Ev>:
StaticFIFO::~StaticFIFO() {
8000a30: b580 push {r7, lr}
8000a32: b082 sub sp, #8
8000a34: af00 add r7, sp, #0
8000a36: 6078 str r0, [r7, #4]
8000a38: 4a07 ldr r2, [pc, #28] ; (8000a58 <_ZN10StaticFIFOD1Ev+0x28>)
8000a3a: 687b ldr r3, [r7, #4]
8000a3c: 601a str r2, [r3, #0]
delete fifo;
8000a3e: 687b ldr r3, [r7, #4]
8000a40: 689b ldr r3, [r3, #8]
8000a42: 2b00 cmp r3, #0
8000a44: d003 beq.n 8000a4e <_ZN10StaticFIFOD1Ev+0x1e>
8000a46: 2184 movs r1, #132 ; 0x84
8000a48: 4618 mov r0, r3
8000a4a: f004 f9b3 bl 8004db4 <_ZdlPvj>
}
8000a4e: 687b ldr r3, [r7, #4]
8000a50: 4618 mov r0, r3
8000a52: 3708 adds r7, #8
8000a54: 46bd mov sp, r7
8000a56: bd80 pop {r7, pc}
8000a58: 08005a28 .word 0x08005a28
08000a5c <_ZN10StaticFIFOD0Ev>:
StaticFIFO::~StaticFIFO() {
8000a5c: b580 push {r7, lr}
8000a5e: b082 sub sp, #8
8000a60: af00 add r7, sp, #0
8000a62: 6078 str r0, [r7, #4]
}
8000a64: 6878 ldr r0, [r7, #4]
8000a66: f7ff ffe3 bl 8000a30 <_ZN10StaticFIFOD1Ev>
8000a6a: 2114 movs r1, #20
8000a6c: 6878 ldr r0, [r7, #4]
8000a6e: f004 f9a1 bl 8004db4 <_ZdlPvj>
8000a72: 687b ldr r3, [r7, #4]
8000a74: 4618 mov r0, r3
8000a76: 3708 adds r7, #8
8000a78: 46bd mov sp, r7
8000a7a: bd80 pop {r7, pc}
08000a7c <_ZN10StaticFIFO4pushEPcm>:
fifo[lastIdx] = stringContainer;
lastIdx = (lastIdx + 1) % fifoSize;
return (((fifoSize + lastIdx) - firstIdx) % fifoSize);
}
int32_t StaticFIFO::push(char* stringPointer, uint32_t stringLength){
8000a7c: b580 push {r7, lr}
8000a7e: b0a6 sub sp, #152 ; 0x98
8000a80: af00 add r7, sp, #0
8000a82: 60f8 str r0, [r7, #12]
8000a84: 60b9 str r1, [r7, #8]
8000a86: 607a str r2, [r7, #4]
if (((fifoSize + firstIdx) - lastIdx) % fifoSize == 1) {
8000a88: 68fb ldr r3, [r7, #12]
8000a8a: 685a ldr r2, [r3, #4]
8000a8c: 68fb ldr r3, [r7, #12]
8000a8e: 68db ldr r3, [r3, #12]
8000a90: 441a add r2, r3
8000a92: 68fb ldr r3, [r7, #12]
8000a94: 691b ldr r3, [r3, #16]
8000a96: 1ad3 subs r3, r2, r3
8000a98: 68fa ldr r2, [r7, #12]
8000a9a: 6852 ldr r2, [r2, #4]
8000a9c: fbb3 f1f2 udiv r1, r3, r2
8000aa0: fb01 f202 mul.w r2, r1, r2
8000aa4: 1a9b subs r3, r3, r2
8000aa6: 2b01 cmp r3, #1
8000aa8: d101 bne.n 8000aae <_ZN10StaticFIFO4pushEPcm+0x32>
return 0; //overflow
8000aaa: 2300 movs r3, #0
8000aac: e04d b.n 8000b4a <_ZN10StaticFIFO4pushEPcm+0xce>
}else if(stringLength > bufSize){
8000aae: 687b ldr r3, [r7, #4]
8000ab0: 2b80 cmp r3, #128 ; 0x80
8000ab2: d902 bls.n 8000aba <_ZN10StaticFIFO4pushEPcm+0x3e>
return -2; //length limit
8000ab4: f06f 0301 mvn.w r3, #1
8000ab8: e047 b.n 8000b4a <_ZN10StaticFIFO4pushEPcm+0xce>
}
StringContainer stringContainer;
for(uint32_t i=0; i < (stringLength); i++){
8000aba: 2300 movs r3, #0
8000abc: f8c7 3094 str.w r3, [r7, #148] ; 0x94
8000ac0: f8d7 2094 ldr.w r2, [r7, #148] ; 0x94
8000ac4: 687b ldr r3, [r7, #4]
8000ac6: 429a cmp r2, r3
8000ac8: d211 bcs.n 8000aee <_ZN10StaticFIFO4pushEPcm+0x72>
stringContainer.buffer[i] = stringPointer[i];
8000aca: 68ba ldr r2, [r7, #8]
8000acc: f8d7 3094 ldr.w r3, [r7, #148] ; 0x94
8000ad0: 4413 add r3, r2
8000ad2: 7819 ldrb r1, [r3, #0]
8000ad4: f107 0210 add.w r2, r7, #16
8000ad8: f8d7 3094 ldr.w r3, [r7, #148] ; 0x94
8000adc: 4413 add r3, r2
8000ade: 460a mov r2, r1
8000ae0: 701a strb r2, [r3, #0]
for(uint32_t i=0; i < (stringLength); i++){
8000ae2: f8d7 3094 ldr.w r3, [r7, #148] ; 0x94
8000ae6: 3301 adds r3, #1
8000ae8: f8c7 3094 str.w r3, [r7, #148] ; 0x94
8000aec: e7e8 b.n 8000ac0 <_ZN10StaticFIFO4pushEPcm+0x44>
}
stringContainer.length = stringLength;
8000aee: 687b ldr r3, [r7, #4]
8000af0: f8c7 3090 str.w r3, [r7, #144] ; 0x90
fifo[lastIdx] = stringContainer;
8000af4: 68fb ldr r3, [r7, #12]
8000af6: 6899 ldr r1, [r3, #8]
8000af8: 68fb ldr r3, [r7, #12]
8000afa: 691a ldr r2, [r3, #16]
8000afc: 4613 mov r3, r2
8000afe: 015b lsls r3, r3, #5
8000b00: 4413 add r3, r2
8000b02: 009b lsls r3, r3, #2
8000b04: 440b add r3, r1
8000b06: 4618 mov r0, r3
8000b08: f107 0310 add.w r3, r7, #16
8000b0c: 2284 movs r2, #132 ; 0x84
8000b0e: 4619 mov r1, r3
8000b10: f004 f9b2 bl 8004e78 <memcpy>
lastIdx = (lastIdx + 1) % fifoSize;
8000b14: 68fb ldr r3, [r7, #12]
8000b16: 691b ldr r3, [r3, #16]
8000b18: 3301 adds r3, #1
8000b1a: 68fa ldr r2, [r7, #12]
8000b1c: 6852 ldr r2, [r2, #4]
8000b1e: fbb3 f1f2 udiv r1, r3, r2
8000b22: fb01 f202 mul.w r2, r1, r2
8000b26: 1a9a subs r2, r3, r2
8000b28: 68fb ldr r3, [r7, #12]
8000b2a: 611a str r2, [r3, #16]
return (((fifoSize + lastIdx) - firstIdx) % fifoSize);
8000b2c: 68fb ldr r3, [r7, #12]
8000b2e: 685a ldr r2, [r3, #4]
8000b30: 68fb ldr r3, [r7, #12]
8000b32: 691b ldr r3, [r3, #16]
8000b34: 441a add r2, r3
8000b36: 68fb ldr r3, [r7, #12]
8000b38: 68db ldr r3, [r3, #12]
8000b3a: 1ad3 subs r3, r2, r3
8000b3c: 68fa ldr r2, [r7, #12]
8000b3e: 6852 ldr r2, [r2, #4]
8000b40: fbb3 f1f2 udiv r1, r3, r2
8000b44: fb01 f202 mul.w r2, r1, r2
8000b48: 1a9b subs r3, r3, r2
}
8000b4a: 4618 mov r0, r3
8000b4c: 3798 adds r7, #152 ; 0x98
8000b4e: 46bd mov sp, r7
8000b50: bd80 pop {r7, pc}
08000b52 <_ZN10StaticFIFO3popEPPhPmm>:
int32_t StaticFIFO::pop(uint8_t** pointer, uint32_t* length, uint32_t max_length){
8000b52: b480 push {r7}
8000b54: b085 sub sp, #20
8000b56: af00 add r7, sp, #0
8000b58: 60f8 str r0, [r7, #12]
8000b5a: 60b9 str r1, [r7, #8]
8000b5c: 607a str r2, [r7, #4]
8000b5e: 603b str r3, [r7, #0]
if (lastIdx == firstIdx){
8000b60: 68fb ldr r3, [r7, #12]
8000b62: 691a ldr r2, [r3, #16]
8000b64: 68fb ldr r3, [r7, #12]
8000b66: 68db ldr r3, [r3, #12]
8000b68: 429a cmp r2, r3
8000b6a: d102 bne.n 8000b72 <_ZN10StaticFIFO3popEPPhPmm+0x20>
return -1; //underrun
8000b6c: f04f 33ff mov.w r3, #4294967295
8000b70: e044 b.n 8000bfc <_ZN10StaticFIFO3popEPPhPmm+0xaa>
}else if(fifo[firstIdx].length > max_length){
8000b72: 68fb ldr r3, [r7, #12]
8000b74: 6899 ldr r1, [r3, #8]
8000b76: 68fb ldr r3, [r7, #12]
8000b78: 68da ldr r2, [r3, #12]
8000b7a: 4613 mov r3, r2
8000b7c: 015b lsls r3, r3, #5
8000b7e: 4413 add r3, r2
8000b80: 009b lsls r3, r3, #2
8000b82: 440b add r3, r1
8000b84: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
8000b88: 683a ldr r2, [r7, #0]
8000b8a: 429a cmp r2, r3
8000b8c: d202 bcs.n 8000b94 <_ZN10StaticFIFO3popEPPhPmm+0x42>
return -2; //length limit
8000b8e: f06f 0301 mvn.w r3, #1
8000b92: e033 b.n 8000bfc <_ZN10StaticFIFO3popEPPhPmm+0xaa>
}
*pointer = fifo[firstIdx].buffer;
8000b94: 68fb ldr r3, [r7, #12]
8000b96: 6899 ldr r1, [r3, #8]
8000b98: 68fb ldr r3, [r7, #12]
8000b9a: 68da ldr r2, [r3, #12]
8000b9c: 4613 mov r3, r2
8000b9e: 015b lsls r3, r3, #5
8000ba0: 4413 add r3, r2
8000ba2: 009b lsls r3, r3, #2
8000ba4: 440b add r3, r1
8000ba6: 461a mov r2, r3
8000ba8: 68bb ldr r3, [r7, #8]
8000baa: 601a str r2, [r3, #0]
*length = fifo[firstIdx].length;
8000bac: 68fb ldr r3, [r7, #12]
8000bae: 6899 ldr r1, [r3, #8]
8000bb0: 68fb ldr r3, [r7, #12]
8000bb2: 68da ldr r2, [r3, #12]
8000bb4: 4613 mov r3, r2
8000bb6: 015b lsls r3, r3, #5
8000bb8: 4413 add r3, r2
8000bba: 009b lsls r3, r3, #2
8000bbc: 440b add r3, r1
8000bbe: f8d3 2080 ldr.w r2, [r3, #128] ; 0x80
8000bc2: 687b ldr r3, [r7, #4]
8000bc4: 601a str r2, [r3, #0]
firstIdx = (firstIdx + 1) % fifoSize;
8000bc6: 68fb ldr r3, [r7, #12]
8000bc8: 68db ldr r3, [r3, #12]
8000bca: 3301 adds r3, #1
8000bcc: 68fa ldr r2, [r7, #12]
8000bce: 6852 ldr r2, [r2, #4]
8000bd0: fbb3 f1f2 udiv r1, r3, r2
8000bd4: fb01 f202 mul.w r2, r1, r2
8000bd8: 1a9a subs r2, r3, r2
8000bda: 68fb ldr r3, [r7, #12]
8000bdc: 60da str r2, [r3, #12]
return (((fifoSize + lastIdx) - firstIdx) % fifoSize);
8000bde: 68fb ldr r3, [r7, #12]
8000be0: 685a ldr r2, [r3, #4]
8000be2: 68fb ldr r3, [r7, #12]
8000be4: 691b ldr r3, [r3, #16]
8000be6: 441a add r2, r3
8000be8: 68fb ldr r3, [r7, #12]
8000bea: 68db ldr r3, [r3, #12]
8000bec: 1ad3 subs r3, r2, r3
8000bee: 68fa ldr r2, [r7, #12]
8000bf0: 6852 ldr r2, [r2, #4]
8000bf2: fbb3 f1f2 udiv r1, r3, r2
8000bf6: fb01 f202 mul.w r2, r1, r2
8000bfa: 1a9b subs r3, r3, r2
}
8000bfc: 4618 mov r0, r3
8000bfe: 3714 adds r7, #20
8000c00: 46bd mov sp, r7
8000c02: bc80 pop {r7}
8000c04: 4770 bx lr
08000c06 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000c06: b580 push {r7, lr}
8000c08: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000c0a: f000 fde5 bl 80017d8 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000c0e: f000 f815 bl 8000c3c <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000c12: f000 fa75 bl 8001100 <MX_GPIO_Init>
MX_DMA_Init();
8000c16: f000 fa55 bl 80010c4 <MX_DMA_Init>
MX_USART1_UART_Init();
8000c1a: f000 f9dd bl 8000fd8 <MX_USART1_UART_Init>
MX_TIM4_Init();
8000c1e: f000 f98d bl 8000f3c <MX_TIM4_Init>
MX_TIM2_Init();
8000c22: f000 f8bd bl 8000da0 <MX_TIM2_Init>
MX_USB_PCD_Init();
8000c26: f000 fa2b bl 8001080 <MX_USB_PCD_Init>
MX_TIM1_Init();
8000c2a: f000 f861 bl 8000cf0 <MX_TIM1_Init>
MX_TIM3_Init();
8000c2e: f000 f931 bl 8000e94 <MX_TIM3_Init>
MX_USART2_UART_Init();
8000c32: f000 f9fb bl 800102c <MX_USART2_UART_Init>
/* USER CODE BEGIN 2 */
start();
8000c36: f7ff fe17 bl 8000868 <start>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
8000c3a: e7fe b.n 8000c3a <main+0x34>
08000c3c <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000c3c: b580 push {r7, lr}
8000c3e: b094 sub sp, #80 ; 0x50
8000c40: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000c42: f107 0328 add.w r3, r7, #40 ; 0x28
8000c46: 2228 movs r2, #40 ; 0x28
8000c48: 2100 movs r1, #0
8000c4a: 4618 mov r0, r3
8000c4c: f004 f922 bl 8004e94 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000c50: f107 0314 add.w r3, r7, #20
8000c54: 2200 movs r2, #0
8000c56: 601a str r2, [r3, #0]
8000c58: 605a str r2, [r3, #4]
8000c5a: 609a str r2, [r3, #8]
8000c5c: 60da str r2, [r3, #12]
8000c5e: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
8000c60: 1d3b adds r3, r7, #4
8000c62: 2200 movs r2, #0
8000c64: 601a str r2, [r3, #0]
8000c66: 605a str r2, [r3, #4]
8000c68: 609a str r2, [r3, #8]
8000c6a: 60da str r2, [r3, #12]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
8000c6c: 2301 movs r3, #1
8000c6e: 62bb str r3, [r7, #40] ; 0x28
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
8000c70: f44f 3380 mov.w r3, #65536 ; 0x10000
8000c74: 62fb str r3, [r7, #44] ; 0x2c
RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
8000c76: 2300 movs r3, #0
8000c78: 633b str r3, [r7, #48] ; 0x30
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
8000c7a: 2301 movs r3, #1
8000c7c: 63bb str r3, [r7, #56] ; 0x38
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
8000c7e: 2302 movs r3, #2
8000c80: 647b str r3, [r7, #68] ; 0x44
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
8000c82: f44f 3380 mov.w r3, #65536 ; 0x10000
8000c86: 64bb str r3, [r7, #72] ; 0x48
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
8000c88: f44f 13e0 mov.w r3, #1835008 ; 0x1c0000
8000c8c: 64fb str r3, [r7, #76] ; 0x4c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000c8e: f107 0328 add.w r3, r7, #40 ; 0x28
8000c92: 4618 mov r0, r3
8000c94: f001 fc7a bl 800258c <HAL_RCC_OscConfig>
8000c98: 4603 mov r3, r0
8000c9a: 2b00 cmp r3, #0
8000c9c: d001 beq.n 8000ca2 <SystemClock_Config+0x66>
{
Error_Handler();
8000c9e: f000 fa95 bl 80011cc <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000ca2: 230f movs r3, #15
8000ca4: 617b str r3, [r7, #20]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
8000ca6: 2302 movs r3, #2
8000ca8: 61bb str r3, [r7, #24]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000caa: 2300 movs r3, #0
8000cac: 61fb str r3, [r7, #28]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
8000cae: f44f 6380 mov.w r3, #1024 ; 0x400
8000cb2: 623b str r3, [r7, #32]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
8000cb4: 2300 movs r3, #0
8000cb6: 627b str r3, [r7, #36] ; 0x24
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
8000cb8: f107 0314 add.w r3, r7, #20
8000cbc: 2102 movs r1, #2
8000cbe: 4618 mov r0, r3
8000cc0: f001 fee6 bl 8002a90 <HAL_RCC_ClockConfig>
8000cc4: 4603 mov r3, r0
8000cc6: 2b00 cmp r3, #0
8000cc8: d001 beq.n 8000cce <SystemClock_Config+0x92>
{
Error_Handler();
8000cca: f000 fa7f bl 80011cc <Error_Handler>
}
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
8000cce: 2310 movs r3, #16
8000cd0: 607b str r3, [r7, #4]
PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
8000cd2: 2300 movs r3, #0
8000cd4: 613b str r3, [r7, #16]
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8000cd6: 1d3b adds r3, r7, #4
8000cd8: 4618 mov r0, r3
8000cda: f002 f871 bl 8002dc0 <HAL_RCCEx_PeriphCLKConfig>
8000cde: 4603 mov r3, r0
8000ce0: 2b00 cmp r3, #0
8000ce2: d001 beq.n 8000ce8 <SystemClock_Config+0xac>
{
Error_Handler();
8000ce4: f000 fa72 bl 80011cc <Error_Handler>
}
}
8000ce8: bf00 nop
8000cea: 3750 adds r7, #80 ; 0x50
8000cec: 46bd mov sp, r7
8000cee: bd80 pop {r7, pc}
08000cf0 <MX_TIM1_Init>:
* @brief TIM1 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM1_Init(void)
{
8000cf0: b580 push {r7, lr}
8000cf2: b08c sub sp, #48 ; 0x30
8000cf4: af00 add r7, sp, #0
/* USER CODE BEGIN TIM1_Init 0 */
/* USER CODE END TIM1_Init 0 */
TIM_Encoder_InitTypeDef sConfig = {0};
8000cf6: f107 030c add.w r3, r7, #12
8000cfa: 2224 movs r2, #36 ; 0x24
8000cfc: 2100 movs r1, #0
8000cfe: 4618 mov r0, r3
8000d00: f004 f8c8 bl 8004e94 <memset>
TIM_MasterConfigTypeDef sMasterConfig = {0};
8000d04: 1d3b adds r3, r7, #4
8000d06: 2200 movs r2, #0
8000d08: 601a str r2, [r3, #0]
8000d0a: 605a str r2, [r3, #4]
/* USER CODE BEGIN TIM1_Init 1 */
/* USER CODE END TIM1_Init 1 */
htim1.Instance = TIM1;
8000d0c: 4b22 ldr r3, [pc, #136] ; (8000d98 <MX_TIM1_Init+0xa8>)
8000d0e: 4a23 ldr r2, [pc, #140] ; (8000d9c <MX_TIM1_Init+0xac>)
8000d10: 601a str r2, [r3, #0]
htim1.Init.Prescaler = 0;
8000d12: 4b21 ldr r3, [pc, #132] ; (8000d98 <MX_TIM1_Init+0xa8>)
8000d14: 2200 movs r2, #0
8000d16: 605a str r2, [r3, #4]
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
8000d18: 4b1f ldr r3, [pc, #124] ; (8000d98 <MX_TIM1_Init+0xa8>)
8000d1a: 2200 movs r2, #0
8000d1c: 609a str r2, [r3, #8]
htim1.Init.Period = 65535;
8000d1e: 4b1e ldr r3, [pc, #120] ; (8000d98 <MX_TIM1_Init+0xa8>)
8000d20: f64f 72ff movw r2, #65535 ; 0xffff
8000d24: 60da str r2, [r3, #12]
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8000d26: 4b1c ldr r3, [pc, #112] ; (8000d98 <MX_TIM1_Init+0xa8>)
8000d28: 2200 movs r2, #0
8000d2a: 611a str r2, [r3, #16]
htim1.Init.RepetitionCounter = 0;
8000d2c: 4b1a ldr r3, [pc, #104] ; (8000d98 <MX_TIM1_Init+0xa8>)
8000d2e: 2200 movs r2, #0
8000d30: 615a str r2, [r3, #20]
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8000d32: 4b19 ldr r3, [pc, #100] ; (8000d98 <MX_TIM1_Init+0xa8>)
8000d34: 2200 movs r2, #0
8000d36: 619a str r2, [r3, #24]
sConfig.EncoderMode = TIM_ENCODERMODE_TI1;
8000d38: 2301 movs r3, #1
8000d3a: 60fb str r3, [r7, #12]
sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;
8000d3c: 2300 movs r3, #0
8000d3e: 613b str r3, [r7, #16]
sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
8000d40: 2301 movs r3, #1
8000d42: 617b str r3, [r7, #20]
sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
8000d44: 2300 movs r3, #0
8000d46: 61bb str r3, [r7, #24]
sConfig.IC1Filter = 0;
8000d48: 2300 movs r3, #0
8000d4a: 61fb str r3, [r7, #28]
sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;
8000d4c: 2300 movs r3, #0
8000d4e: 623b str r3, [r7, #32]
sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
8000d50: 2301 movs r3, #1
8000d52: 627b str r3, [r7, #36] ; 0x24
sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
8000d54: 2300 movs r3, #0
8000d56: 62bb str r3, [r7, #40] ; 0x28
sConfig.IC2Filter = 0;
8000d58: 2300 movs r3, #0
8000d5a: 62fb str r3, [r7, #44] ; 0x2c
if (HAL_TIM_Encoder_Init(&htim1, &sConfig) != HAL_OK)
8000d5c: f107 030c add.w r3, r7, #12
8000d60: 4619 mov r1, r3
8000d62: 480d ldr r0, [pc, #52] ; (8000d98 <MX_TIM1_Init+0xa8>)
8000d64: f002 fa6e bl 8003244 <HAL_TIM_Encoder_Init>
8000d68: 4603 mov r3, r0
8000d6a: 2b00 cmp r3, #0
8000d6c: d001 beq.n 8000d72 <MX_TIM1_Init+0x82>
{
Error_Handler();
8000d6e: f000 fa2d bl 80011cc <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8000d72: 2300 movs r3, #0
8000d74: 607b str r3, [r7, #4]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8000d76: 2300 movs r3, #0
8000d78: 60bb str r3, [r7, #8]
if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
8000d7a: 1d3b adds r3, r7, #4
8000d7c: 4619 mov r1, r3
8000d7e: 4806 ldr r0, [pc, #24] ; (8000d98 <MX_TIM1_Init+0xa8>)
8000d80: f003 f8e2 bl 8003f48 <HAL_TIMEx_MasterConfigSynchronization>
8000d84: 4603 mov r3, r0
8000d86: 2b00 cmp r3, #0
8000d88: d001 beq.n 8000d8e <MX_TIM1_Init+0x9e>
{
Error_Handler();
8000d8a: f000 fa1f bl 80011cc <Error_Handler>
}
/* USER CODE BEGIN TIM1_Init 2 */
/* USER CODE END TIM1_Init 2 */
}
8000d8e: bf00 nop
8000d90: 3730 adds r7, #48 ; 0x30
8000d92: 46bd mov sp, r7
8000d94: bd80 pop {r7, pc}
8000d96: bf00 nop
8000d98: 200003b0 .word 0x200003b0
8000d9c: 40012c00 .word 0x40012c00
08000da0 <MX_TIM2_Init>:
* @brief TIM2 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM2_Init(void)
{
8000da0: b580 push {r7, lr}
8000da2: b08a sub sp, #40 ; 0x28
8000da4: af00 add r7, sp, #0
/* USER CODE BEGIN TIM2_Init 0 */
/* USER CODE END TIM2_Init 0 */
TIM_MasterConfigTypeDef sMasterConfig = {0};
8000da6: f107 0320 add.w r3, r7, #32
8000daa: 2200 movs r2, #0
8000dac: 601a str r2, [r3, #0]
8000dae: 605a str r2, [r3, #4]
TIM_OC_InitTypeDef sConfigOC = {0};
8000db0: 1d3b adds r3, r7, #4
8000db2: 2200 movs r2, #0
8000db4: 601a str r2, [r3, #0]
8000db6: 605a str r2, [r3, #4]
8000db8: 609a str r2, [r3, #8]
8000dba: 60da str r2, [r3, #12]
8000dbc: 611a str r2, [r3, #16]
8000dbe: 615a str r2, [r3, #20]
8000dc0: 619a str r2, [r3, #24]
/* USER CODE BEGIN TIM2_Init 1 */
/* USER CODE END TIM2_Init 1 */
htim2.Instance = TIM2;
8000dc2: 4b33 ldr r3, [pc, #204] ; (8000e90 <MX_TIM2_Init+0xf0>)
8000dc4: f04f 4280 mov.w r2, #1073741824 ; 0x40000000
8000dc8: 601a str r2, [r3, #0]
htim2.Init.Prescaler = 0;
8000dca: 4b31 ldr r3, [pc, #196] ; (8000e90 <MX_TIM2_Init+0xf0>)
8000dcc: 2200 movs r2, #0
8000dce: 605a str r2, [r3, #4]
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
8000dd0: 4b2f ldr r3, [pc, #188] ; (8000e90 <MX_TIM2_Init+0xf0>)
8000dd2: 2200 movs r2, #0
8000dd4: 609a str r2, [r3, #8]
htim2.Init.Period = 65535;
8000dd6: 4b2e ldr r3, [pc, #184] ; (8000e90 <MX_TIM2_Init+0xf0>)
8000dd8: f64f 72ff movw r2, #65535 ; 0xffff
8000ddc: 60da str r2, [r3, #12]
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8000dde: 4b2c ldr r3, [pc, #176] ; (8000e90 <MX_TIM2_Init+0xf0>)
8000de0: 2200 movs r2, #0
8000de2: 611a str r2, [r3, #16]
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8000de4: 4b2a ldr r3, [pc, #168] ; (8000e90 <MX_TIM2_Init+0xf0>)
8000de6: 2200 movs r2, #0
8000de8: 619a str r2, [r3, #24]
if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)
8000dea: 4829 ldr r0, [pc, #164] ; (8000e90 <MX_TIM2_Init+0xf0>)
8000dec: f002 f938 bl 8003060 <HAL_TIM_PWM_Init>
8000df0: 4603 mov r3, r0
8000df2: 2b00 cmp r3, #0
8000df4: d001 beq.n 8000dfa <MX_TIM2_Init+0x5a>
{
Error_Handler();
8000df6: f000 f9e9 bl 80011cc <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8000dfa: 2300 movs r3, #0
8000dfc: 623b str r3, [r7, #32]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8000dfe: 2300 movs r3, #0
8000e00: 627b str r3, [r7, #36] ; 0x24
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
8000e02: f107 0320 add.w r3, r7, #32
8000e06: 4619 mov r1, r3
8000e08: 4821 ldr r0, [pc, #132] ; (8000e90 <MX_TIM2_Init+0xf0>)
8000e0a: f003 f89d bl 8003f48 <HAL_TIMEx_MasterConfigSynchronization>
8000e0e: 4603 mov r3, r0
8000e10: 2b00 cmp r3, #0
8000e12: d001 beq.n 8000e18 <MX_TIM2_Init+0x78>
{
Error_Handler();
8000e14: f000 f9da bl 80011cc <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
8000e18: 2360 movs r3, #96 ; 0x60
8000e1a: 607b str r3, [r7, #4]
sConfigOC.Pulse = 0;
8000e1c: 2300 movs r3, #0
8000e1e: 60bb str r3, [r7, #8]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
8000e20: 2300 movs r3, #0
8000e22: 60fb str r3, [r7, #12]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
8000e24: 2300 movs r3, #0
8000e26: 617b str r3, [r7, #20]
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
8000e28: 1d3b adds r3, r7, #4
8000e2a: 2200 movs r2, #0
8000e2c: 4619 mov r1, r3
8000e2e: 4818 ldr r0, [pc, #96] ; (8000e90 <MX_TIM2_Init+0xf0>)
8000e30: f002 fc40 bl 80036b4 <HAL_TIM_PWM_ConfigChannel>
8000e34: 4603 mov r3, r0
8000e36: 2b00 cmp r3, #0
8000e38: d001 beq.n 8000e3e <MX_TIM2_Init+0x9e>
{
Error_Handler();
8000e3a: f000 f9c7 bl 80011cc <Error_Handler>
}
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
8000e3e: 1d3b adds r3, r7, #4
8000e40: 2204 movs r2, #4
8000e42: 4619 mov r1, r3
8000e44: 4812 ldr r0, [pc, #72] ; (8000e90 <MX_TIM2_Init+0xf0>)
8000e46: f002 fc35 bl 80036b4 <HAL_TIM_PWM_ConfigChannel>
8000e4a: 4603 mov r3, r0
8000e4c: 2b00 cmp r3, #0
8000e4e: d001 beq.n 8000e54 <MX_TIM2_Init+0xb4>
{
Error_Handler();
8000e50: f000 f9bc bl 80011cc <Error_Handler>
}
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
8000e54: 1d3b adds r3, r7, #4
8000e56: 2208 movs r2, #8
8000e58: 4619 mov r1, r3
8000e5a: 480d ldr r0, [pc, #52] ; (8000e90 <MX_TIM2_Init+0xf0>)
8000e5c: f002 fc2a bl 80036b4 <HAL_TIM_PWM_ConfigChannel>
8000e60: 4603 mov r3, r0
8000e62: 2b00 cmp r3, #0
8000e64: d001 beq.n 8000e6a <MX_TIM2_Init+0xca>
{
Error_Handler();
8000e66: f000 f9b1 bl 80011cc <Error_Handler>
}
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
8000e6a: 1d3b adds r3, r7, #4
8000e6c: 220c movs r2, #12
8000e6e: 4619 mov r1, r3
8000e70: 4807 ldr r0, [pc, #28] ; (8000e90 <MX_TIM2_Init+0xf0>)
8000e72: f002 fc1f bl 80036b4 <HAL_TIM_PWM_ConfigChannel>
8000e76: 4603 mov r3, r0
8000e78: 2b00 cmp r3, #0
8000e7a: d001 beq.n 8000e80 <MX_TIM2_Init+0xe0>
{
Error_Handler();
8000e7c: f000 f9a6 bl 80011cc <Error_Handler>
}
/* USER CODE BEGIN TIM2_Init 2 */
/* USER CODE END TIM2_Init 2 */
HAL_TIM_MspPostInit(&htim2);
8000e80: 4803 ldr r0, [pc, #12] ; (8000e90 <MX_TIM2_Init+0xf0>)
8000e82: f000 fa89 bl 8001398 <HAL_TIM_MspPostInit>
}
8000e86: bf00 nop
8000e88: 3728 adds r7, #40 ; 0x28
8000e8a: 46bd mov sp, r7
8000e8c: bd80 pop {r7, pc}
8000e8e: bf00 nop
8000e90: 200003f8 .word 0x200003f8
08000e94 <MX_TIM3_Init>:
* @brief TIM3 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM3_Init(void)
{
8000e94: b580 push {r7, lr}
8000e96: b08c sub sp, #48 ; 0x30
8000e98: af00 add r7, sp, #0
/* USER CODE BEGIN TIM3_Init 0 */
/* USER CODE END TIM3_Init 0 */
TIM_Encoder_InitTypeDef sConfig = {0};
8000e9a: f107 030c add.w r3, r7, #12
8000e9e: 2224 movs r2, #36 ; 0x24
8000ea0: 2100 movs r1, #0
8000ea2: 4618 mov r0, r3
8000ea4: f003 fff6 bl 8004e94 <memset>
TIM_MasterConfigTypeDef sMasterConfig = {0};
8000ea8: 1d3b adds r3, r7, #4
8000eaa: 2200 movs r2, #0
8000eac: 601a str r2, [r3, #0]
8000eae: 605a str r2, [r3, #4]
/* USER CODE BEGIN TIM3_Init 1 */
/* USER CODE END TIM3_Init 1 */
htim3.Instance = TIM3;
8000eb0: 4b20 ldr r3, [pc, #128] ; (8000f34 <MX_TIM3_Init+0xa0>)
8000eb2: 4a21 ldr r2, [pc, #132] ; (8000f38 <MX_TIM3_Init+0xa4>)
8000eb4: 601a str r2, [r3, #0]
htim3.Init.Prescaler = 0;
8000eb6: 4b1f ldr r3, [pc, #124] ; (8000f34 <MX_TIM3_Init+0xa0>)
8000eb8: 2200 movs r2, #0
8000eba: 605a str r2, [r3, #4]
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
8000ebc: 4b1d ldr r3, [pc, #116] ; (8000f34 <MX_TIM3_Init+0xa0>)
8000ebe: 2200 movs r2, #0
8000ec0: 609a str r2, [r3, #8]
htim3.Init.Period = 65535;
8000ec2: 4b1c ldr r3, [pc, #112] ; (8000f34 <MX_TIM3_Init+0xa0>)
8000ec4: f64f 72ff movw r2, #65535 ; 0xffff
8000ec8: 60da str r2, [r3, #12]
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8000eca: 4b1a ldr r3, [pc, #104] ; (8000f34 <MX_TIM3_Init+0xa0>)
8000ecc: 2200 movs r2, #0
8000ece: 611a str r2, [r3, #16]
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8000ed0: 4b18 ldr r3, [pc, #96] ; (8000f34 <MX_TIM3_Init+0xa0>)
8000ed2: 2200 movs r2, #0
8000ed4: 619a str r2, [r3, #24]
sConfig.EncoderMode = TIM_ENCODERMODE_TI1;
8000ed6: 2301 movs r3, #1
8000ed8: 60fb str r3, [r7, #12]
sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;
8000eda: 2300 movs r3, #0
8000edc: 613b str r3, [r7, #16]
sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
8000ede: 2301 movs r3, #1
8000ee0: 617b str r3, [r7, #20]
sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
8000ee2: 2300 movs r3, #0
8000ee4: 61bb str r3, [r7, #24]
sConfig.IC1Filter = 0;
8000ee6: 2300 movs r3, #0
8000ee8: 61fb str r3, [r7, #28]
sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;
8000eea: 2300 movs r3, #0
8000eec: 623b str r3, [r7, #32]
sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
8000eee: 2301 movs r3, #1
8000ef0: 627b str r3, [r7, #36] ; 0x24
sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
8000ef2: 2300 movs r3, #0
8000ef4: 62bb str r3, [r7, #40] ; 0x28
sConfig.IC2Filter = 0;
8000ef6: 2300 movs r3, #0
8000ef8: 62fb str r3, [r7, #44] ; 0x2c
if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK)
8000efa: f107 030c add.w r3, r7, #12
8000efe: 4619 mov r1, r3
8000f00: 480c ldr r0, [pc, #48] ; (8000f34 <MX_TIM3_Init+0xa0>)
8000f02: f002 f99f bl 8003244 <HAL_TIM_Encoder_Init>
8000f06: 4603 mov r3, r0
8000f08: 2b00 cmp r3, #0
8000f0a: d001 beq.n 8000f10 <MX_TIM3_Init+0x7c>
{
Error_Handler();
8000f0c: f000 f95e bl 80011cc <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8000f10: 2300 movs r3, #0
8000f12: 607b str r3, [r7, #4]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8000f14: 2300 movs r3, #0
8000f16: 60bb str r3, [r7, #8]
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
8000f18: 1d3b adds r3, r7, #4
8000f1a: 4619 mov r1, r3
8000f1c: 4805 ldr r0, [pc, #20] ; (8000f34 <MX_TIM3_Init+0xa0>)
8000f1e: f003 f813 bl 8003f48 <HAL_TIMEx_MasterConfigSynchronization>
8000f22: 4603 mov r3, r0
8000f24: 2b00 cmp r3, #0
8000f26: d001 beq.n 8000f2c <MX_TIM3_Init+0x98>
{
Error_Handler();
8000f28: f000 f950 bl 80011cc <Error_Handler>
}
/* USER CODE BEGIN TIM3_Init 2 */
/* USER CODE END TIM3_Init 2 */
}
8000f2c: bf00 nop
8000f2e: 3730 adds r7, #48 ; 0x30
8000f30: 46bd mov sp, r7
8000f32: bd80 pop {r7, pc}
8000f34: 20000440 .word 0x20000440
8000f38: 40000400 .word 0x40000400
08000f3c <MX_TIM4_Init>:
* @brief TIM4 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM4_Init(void)
{
8000f3c: b580 push {r7, lr}
8000f3e: b086 sub sp, #24
8000f40: af00 add r7, sp, #0
/* USER CODE BEGIN TIM4_Init 0 */
/* USER CODE END TIM4_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
8000f42: f107 0308 add.w r3, r7, #8
8000f46: 2200 movs r2, #0
8000f48: 601a str r2, [r3, #0]
8000f4a: 605a str r2, [r3, #4]
8000f4c: 609a str r2, [r3, #8]
8000f4e: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
8000f50: 463b mov r3, r7
8000f52: 2200 movs r2, #0
8000f54: 601a str r2, [r3, #0]
8000f56: 605a str r2, [r3, #4]
/* USER CODE BEGIN TIM4_Init 1 */
/* USER CODE END TIM4_Init 1 */
htim4.Instance = TIM4;
8000f58: 4b1d ldr r3, [pc, #116] ; (8000fd0 <MX_TIM4_Init+0x94>)
8000f5a: 4a1e ldr r2, [pc, #120] ; (8000fd4 <MX_TIM4_Init+0x98>)
8000f5c: 601a str r2, [r3, #0]
htim4.Init.Prescaler = 71;
8000f5e: 4b1c ldr r3, [pc, #112] ; (8000fd0 <MX_TIM4_Init+0x94>)
8000f60: 2247 movs r2, #71 ; 0x47
8000f62: 605a str r2, [r3, #4]
htim4.Init.CounterMode = TIM_COUNTERMODE_UP;
8000f64: 4b1a ldr r3, [pc, #104] ; (8000fd0 <MX_TIM4_Init+0x94>)
8000f66: 2200 movs r2, #0
8000f68: 609a str r2, [r3, #8]
htim4.Init.Period = 9999;
8000f6a: 4b19 ldr r3, [pc, #100] ; (8000fd0 <MX_TIM4_Init+0x94>)
8000f6c: f242 720f movw r2, #9999 ; 0x270f
8000f70: 60da str r2, [r3, #12]
htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8000f72: 4b17 ldr r3, [pc, #92] ; (8000fd0 <MX_TIM4_Init+0x94>)
8000f74: 2200 movs r2, #0
8000f76: 611a str r2, [r3, #16]
htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8000f78: 4b15 ldr r3, [pc, #84] ; (8000fd0 <MX_TIM4_Init+0x94>)
8000f7a: 2200 movs r2, #0
8000f7c: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim4) != HAL_OK)
8000f7e: 4814 ldr r0, [pc, #80] ; (8000fd0 <MX_TIM4_Init+0x94>)
8000f80: f001 ffd4 bl 8002f2c <HAL_TIM_Base_Init>
8000f84: 4603 mov r3, r0
8000f86: 2b00 cmp r3, #0
8000f88: d001 beq.n 8000f8e <MX_TIM4_Init+0x52>
{
Error_Handler();
8000f8a: f000 f91f bl 80011cc <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8000f8e: f44f 5380 mov.w r3, #4096 ; 0x1000
8000f92: 60bb str r3, [r7, #8]
if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK)
8000f94: f107 0308 add.w r3, r7, #8
8000f98: 4619 mov r1, r3
8000f9a: 480d ldr r0, [pc, #52] ; (8000fd0 <MX_TIM4_Init+0x94>)
8000f9c: f002 fc48 bl 8003830 <HAL_TIM_ConfigClockSource>
8000fa0: 4603 mov r3, r0
8000fa2: 2b00 cmp r3, #0
8000fa4: d001 beq.n 8000faa <MX_TIM4_Init+0x6e>
{
Error_Handler();
8000fa6: f000 f911 bl 80011cc <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8000faa: 2300 movs r3, #0
8000fac: 603b str r3, [r7, #0]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8000fae: 2300 movs r3, #0
8000fb0: 607b str r3, [r7, #4]
if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK)
8000fb2: 463b mov r3, r7
8000fb4: 4619 mov r1, r3
8000fb6: 4806 ldr r0, [pc, #24] ; (8000fd0 <MX_TIM4_Init+0x94>)
8000fb8: f002 ffc6 bl 8003f48 <HAL_TIMEx_MasterConfigSynchronization>
8000fbc: 4603 mov r3, r0
8000fbe: 2b00 cmp r3, #0
8000fc0: d001 beq.n 8000fc6 <MX_TIM4_Init+0x8a>
{
Error_Handler();
8000fc2: f000 f903 bl 80011cc <Error_Handler>
}
/* USER CODE BEGIN TIM4_Init 2 */
/* USER CODE END TIM4_Init 2 */
}
8000fc6: bf00 nop
8000fc8: 3718 adds r7, #24
8000fca: 46bd mov sp, r7
8000fcc: bd80 pop {r7, pc}
8000fce: bf00 nop
8000fd0: 20000488 .word 0x20000488
8000fd4: 40000800 .word 0x40000800
08000fd8 <MX_USART1_UART_Init>:
* @brief USART1 Initialization Function
* @param None
* @retval None
*/
static void MX_USART1_UART_Init(void)
{
8000fd8: b580 push {r7, lr}
8000fda: af00 add r7, sp, #0
/* USER CODE END USART1_Init 0 */
/* USER CODE BEGIN USART1_Init 1 */
/* USER CODE END USART1_Init 1 */
huart1.Instance = USART1;
8000fdc: 4b10 ldr r3, [pc, #64] ; (8001020 <MX_USART1_UART_Init+0x48>)
8000fde: 4a11 ldr r2, [pc, #68] ; (8001024 <MX_USART1_UART_Init+0x4c>)
8000fe0: 601a str r2, [r3, #0]
huart1.Init.BaudRate = 2250000;
8000fe2: 4b0f ldr r3, [pc, #60] ; (8001020 <MX_USART1_UART_Init+0x48>)
8000fe4: 4a10 ldr r2, [pc, #64] ; (8001028 <MX_USART1_UART_Init+0x50>)
8000fe6: 605a str r2, [r3, #4]
huart1.Init.WordLength = UART_WORDLENGTH_8B;
8000fe8: 4b0d ldr r3, [pc, #52] ; (8001020 <MX_USART1_UART_Init+0x48>)
8000fea: 2200 movs r2, #0
8000fec: 609a str r2, [r3, #8]
huart1.Init.StopBits = UART_STOPBITS_1;
8000fee: 4b0c ldr r3, [pc, #48] ; (8001020 <MX_USART1_UART_Init+0x48>)
8000ff0: 2200 movs r2, #0
8000ff2: 60da str r2, [r3, #12]
huart1.Init.Parity = UART_PARITY_NONE;
8000ff4: 4b0a ldr r3, [pc, #40] ; (8001020 <MX_USART1_UART_Init+0x48>)
8000ff6: 2200 movs r2, #0
8000ff8: 611a str r2, [r3, #16]
huart1.Init.Mode = UART_MODE_TX_RX;
8000ffa: 4b09 ldr r3, [pc, #36] ; (8001020 <MX_USART1_UART_Init+0x48>)
8000ffc: 220c movs r2, #12
8000ffe: 615a str r2, [r3, #20]
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
8001000: 4b07 ldr r3, [pc, #28] ; (8001020 <MX_USART1_UART_Init+0x48>)
8001002: 2200 movs r2, #0
8001004: 619a str r2, [r3, #24]
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
8001006: 4b06 ldr r3, [pc, #24] ; (8001020 <MX_USART1_UART_Init+0x48>)
8001008: 2200 movs r2, #0
800100a: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart1) != HAL_OK)
800100c: 4804 ldr r0, [pc, #16] ; (8001020 <MX_USART1_UART_Init+0x48>)
800100e: f003 f80b bl 8004028 <HAL_UART_Init>
8001012: 4603 mov r3, r0
8001014: 2b00 cmp r3, #0
8001016: d001 beq.n 800101c <MX_USART1_UART_Init+0x44>
{
Error_Handler();
8001018: f000 f8d8 bl 80011cc <Error_Handler>
}
/* USER CODE BEGIN USART1_Init 2 */
/* USER CODE END USART1_Init 2 */
}
800101c: bf00 nop
800101e: bd80 pop {r7, pc}
8001020: 200004d0 .word 0x200004d0
8001024: 40013800 .word 0x40013800
8001028: 00225510 .word 0x00225510
0800102c <MX_USART2_UART_Init>:
* @brief USART2 Initialization Function
* @param None
* @retval None
*/
static void MX_USART2_UART_Init(void)
{
800102c: b580 push {r7, lr}
800102e: af00 add r7, sp, #0
/* USER CODE END USART2_Init 0 */
/* USER CODE BEGIN USART2_Init 1 */
/* USER CODE END USART2_Init 1 */
huart2.Instance = USART2;
8001030: 4b10 ldr r3, [pc, #64] ; (8001074 <MX_USART2_UART_Init+0x48>)
8001032: 4a11 ldr r2, [pc, #68] ; (8001078 <MX_USART2_UART_Init+0x4c>)
8001034: 601a str r2, [r3, #0]
huart2.Init.BaudRate = 2250000;
8001036: 4b0f ldr r3, [pc, #60] ; (8001074 <MX_USART2_UART_Init+0x48>)
8001038: 4a10 ldr r2, [pc, #64] ; (800107c <MX_USART2_UART_Init+0x50>)
800103a: 605a str r2, [r3, #4]
huart2.Init.WordLength = UART_WORDLENGTH_8B;
800103c: 4b0d ldr r3, [pc, #52] ; (8001074 <MX_USART2_UART_Init+0x48>)
800103e: 2200 movs r2, #0
8001040: 609a str r2, [r3, #8]
huart2.Init.StopBits = UART_STOPBITS_1;
8001042: 4b0c ldr r3, [pc, #48] ; (8001074 <MX_USART2_UART_Init+0x48>)
8001044: 2200 movs r2, #0
8001046: 60da str r2, [r3, #12]
huart2.Init.Parity = UART_PARITY_NONE;
8001048: 4b0a ldr r3, [pc, #40] ; (8001074 <MX_USART2_UART_Init+0x48>)
800104a: 2200 movs r2, #0
800104c: 611a str r2, [r3, #16]
huart2.Init.Mode = UART_MODE_TX_RX;
800104e: 4b09 ldr r3, [pc, #36] ; (8001074 <MX_USART2_UART_Init+0x48>)
8001050: 220c movs r2, #12
8001052: 615a str r2, [r3, #20]
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
8001054: 4b07 ldr r3, [pc, #28] ; (8001074 <MX_USART2_UART_Init+0x48>)
8001056: 2200 movs r2, #0
8001058: 619a str r2, [r3, #24]
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
800105a: 4b06 ldr r3, [pc, #24] ; (8001074 <MX_USART2_UART_Init+0x48>)
800105c: 2200 movs r2, #0
800105e: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart2) != HAL_OK)
8001060: 4804 ldr r0, [pc, #16] ; (8001074 <MX_USART2_UART_Init+0x48>)
8001062: f002 ffe1 bl 8004028 <HAL_UART_Init>
8001066: 4603 mov r3, r0
8001068: 2b00 cmp r3, #0
800106a: d001 beq.n 8001070 <MX_USART2_UART_Init+0x44>
{
Error_Handler();
800106c: f000 f8ae bl 80011cc <Error_Handler>
}
/* USER CODE BEGIN USART2_Init 2 */
/* USER CODE END USART2_Init 2 */
}
8001070: bf00 nop
8001072: bd80 pop {r7, pc}
8001074: 20000514 .word 0x20000514
8001078: 40004400 .word 0x40004400
800107c: 00225510 .word 0x00225510
08001080 <MX_USB_PCD_Init>:
* @brief USB Initialization Function
* @param None
* @retval None
*/
static void MX_USB_PCD_Init(void)
{
8001080: b580 push {r7, lr}
8001082: af00 add r7, sp, #0
/* USER CODE END USB_Init 0 */
/* USER CODE BEGIN USB_Init 1 */
/* USER CODE END USB_Init 1 */
hpcd_USB_FS.Instance = USB;
8001084: 4b0d ldr r3, [pc, #52] ; (80010bc <MX_USB_PCD_Init+0x3c>)
8001086: 4a0e ldr r2, [pc, #56] ; (80010c0 <MX_USB_PCD_Init+0x40>)
8001088: 601a str r2, [r3, #0]
hpcd_USB_FS.Init.dev_endpoints = 8;
800108a: 4b0c ldr r3, [pc, #48] ; (80010bc <MX_USB_PCD_Init+0x3c>)
800108c: 2208 movs r2, #8
800108e: 605a str r2, [r3, #4]
hpcd_USB_FS.Init.speed = PCD_SPEED_FULL;
8001090: 4b0a ldr r3, [pc, #40] ; (80010bc <MX_USB_PCD_Init+0x3c>)
8001092: 2202 movs r2, #2
8001094: 609a str r2, [r3, #8]
hpcd_USB_FS.Init.low_power_enable = DISABLE;
8001096: 4b09 ldr r3, [pc, #36] ; (80010bc <MX_USB_PCD_Init+0x3c>)
8001098: 2200 movs r2, #0
800109a: 619a str r2, [r3, #24]
hpcd_USB_FS.Init.lpm_enable = DISABLE;
800109c: 4b07 ldr r3, [pc, #28] ; (80010bc <MX_USB_PCD_Init+0x3c>)
800109e: 2200 movs r2, #0
80010a0: 61da str r2, [r3, #28]
hpcd_USB_FS.Init.battery_charging_enable = DISABLE;
80010a2: 4b06 ldr r3, [pc, #24] ; (80010bc <MX_USB_PCD_Init+0x3c>)
80010a4: 2200 movs r2, #0
80010a6: 621a str r2, [r3, #32]
if (HAL_PCD_Init(&hpcd_USB_FS) != HAL_OK)
80010a8: 4804 ldr r0, [pc, #16] ; (80010bc <MX_USB_PCD_Init+0x3c>)
80010aa: f001 f963 bl 8002374 <HAL_PCD_Init>
80010ae: 4603 mov r3, r0
80010b0: 2b00 cmp r3, #0
80010b2: d001 beq.n 80010b8 <MX_USB_PCD_Init+0x38>
{
Error_Handler();
80010b4: f000 f88a bl 80011cc <Error_Handler>
}
/* USER CODE BEGIN USB_Init 2 */
/* USER CODE END USB_Init 2 */
}
80010b8: bf00 nop
80010ba: bd80 pop {r7, pc}
80010bc: 2000059c .word 0x2000059c
80010c0: 40005c00 .word 0x40005c00
080010c4 <MX_DMA_Init>:
/**
* Enable DMA controller clock
*/
static void MX_DMA_Init(void)
{
80010c4: b580 push {r7, lr}
80010c6: b082 sub sp, #8
80010c8: af00 add r7, sp, #0
/* DMA controller clock enable */
__HAL_RCC_DMA1_CLK_ENABLE();
80010ca: 4b0c ldr r3, [pc, #48] ; (80010fc <MX_DMA_Init+0x38>)
80010cc: 695b ldr r3, [r3, #20]
80010ce: 4a0b ldr r2, [pc, #44] ; (80010fc <MX_DMA_Init+0x38>)
80010d0: f043 0301 orr.w r3, r3, #1
80010d4: 6153 str r3, [r2, #20]
80010d6: 4b09 ldr r3, [pc, #36] ; (80010fc <MX_DMA_Init+0x38>)
80010d8: 695b ldr r3, [r3, #20]
80010da: f003 0301 and.w r3, r3, #1
80010de: 607b str r3, [r7, #4]
80010e0: 687b ldr r3, [r7, #4]
/* DMA interrupt init */
/* DMA1_Channel7_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Channel7_IRQn, 0, 0);
80010e2: 2200 movs r2, #0
80010e4: 2100 movs r1, #0
80010e6: 2011 movs r0, #17
80010e8: f000 fcd3 bl 8001a92 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DMA1_Channel7_IRQn);
80010ec: 2011 movs r0, #17
80010ee: f000 fcec bl 8001aca <HAL_NVIC_EnableIRQ>
}
80010f2: bf00 nop
80010f4: 3708 adds r7, #8
80010f6: 46bd mov sp, r7
80010f8: bd80 pop {r7, pc}
80010fa: bf00 nop
80010fc: 40021000 .word 0x40021000
08001100 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8001100: b580 push {r7, lr}
8001102: b088 sub sp, #32
8001104: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001106: f107 0310 add.w r3, r7, #16
800110a: 2200 movs r2, #0
800110c: 601a str r2, [r3, #0]
800110e: 605a str r2, [r3, #4]
8001110: 609a str r2, [r3, #8]
8001112: 60da str r2, [r3, #12]
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
8001114: 4b2a ldr r3, [pc, #168] ; (80011c0 <MX_GPIO_Init+0xc0>)
8001116: 699b ldr r3, [r3, #24]
8001118: 4a29 ldr r2, [pc, #164] ; (80011c0 <MX_GPIO_Init+0xc0>)
800111a: f043 0310 orr.w r3, r3, #16
800111e: 6193 str r3, [r2, #24]
8001120: 4b27 ldr r3, [pc, #156] ; (80011c0 <MX_GPIO_Init+0xc0>)
8001122: 699b ldr r3, [r3, #24]
8001124: f003 0310 and.w r3, r3, #16
8001128: 60fb str r3, [r7, #12]
800112a: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOD_CLK_ENABLE();
800112c: 4b24 ldr r3, [pc, #144] ; (80011c0 <MX_GPIO_Init+0xc0>)
800112e: 699b ldr r3, [r3, #24]
8001130: 4a23 ldr r2, [pc, #140] ; (80011c0 <MX_GPIO_Init+0xc0>)
8001132: f043 0320 orr.w r3, r3, #32
8001136: 6193 str r3, [r2, #24]
8001138: 4b21 ldr r3, [pc, #132] ; (80011c0 <MX_GPIO_Init+0xc0>)
800113a: 699b ldr r3, [r3, #24]
800113c: f003 0320 and.w r3, r3, #32
8001140: 60bb str r3, [r7, #8]
8001142: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001144: 4b1e ldr r3, [pc, #120] ; (80011c0 <MX_GPIO_Init+0xc0>)
8001146: 699b ldr r3, [r3, #24]
8001148: 4a1d ldr r2, [pc, #116] ; (80011c0 <MX_GPIO_Init+0xc0>)
800114a: f043 0304 orr.w r3, r3, #4
800114e: 6193 str r3, [r2, #24]
8001150: 4b1b ldr r3, [pc, #108] ; (80011c0 <MX_GPIO_Init+0xc0>)
8001152: 699b ldr r3, [r3, #24]
8001154: f003 0304 and.w r3, r3, #4
8001158: 607b str r3, [r7, #4]
800115a: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOB_CLK_ENABLE();
800115c: 4b18 ldr r3, [pc, #96] ; (80011c0 <MX_GPIO_Init+0xc0>)
800115e: 699b ldr r3, [r3, #24]
8001160: 4a17 ldr r2, [pc, #92] ; (80011c0 <MX_GPIO_Init+0xc0>)
8001162: f043 0308 orr.w r3, r3, #8
8001166: 6193 str r3, [r2, #24]
8001168: 4b15 ldr r3, [pc, #84] ; (80011c0 <MX_GPIO_Init+0xc0>)
800116a: 699b ldr r3, [r3, #24]
800116c: f003 0308 and.w r3, r3, #8
8001170: 603b str r3, [r7, #0]
8001172: 683b ldr r3, [r7, #0]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LED_BUILTIN_GPIO_Port, LED_BUILTIN_Pin, GPIO_PIN_SET);
8001174: 2201 movs r2, #1
8001176: f44f 5100 mov.w r1, #8192 ; 0x2000
800117a: 4812 ldr r0, [pc, #72] ; (80011c4 <MX_GPIO_Init+0xc4>)
800117c: f001 f8e2 bl 8002344 <HAL_GPIO_WritePin>
/*Configure GPIO pin : LED_BUILTIN_Pin */
GPIO_InitStruct.Pin = LED_BUILTIN_Pin;
8001180: f44f 5300 mov.w r3, #8192 ; 0x2000
8001184: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001186: 2301 movs r3, #1
8001188: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800118a: 2300 movs r3, #0
800118c: 61bb str r3, [r7, #24]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800118e: 2302 movs r3, #2
8001190: 61fb str r3, [r7, #28]
HAL_GPIO_Init(LED_BUILTIN_GPIO_Port, &GPIO_InitStruct);
8001192: f107 0310 add.w r3, r7, #16
8001196: 4619 mov r1, r3
8001198: 480a ldr r0, [pc, #40] ; (80011c4 <MX_GPIO_Init+0xc4>)
800119a: f000 ff4f bl 800203c <HAL_GPIO_Init>
/*Configure GPIO pin : BOOT1_Pin */
GPIO_InitStruct.Pin = BOOT1_Pin;
800119e: 2304 movs r3, #4
80011a0: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
80011a2: 2300 movs r3, #0
80011a4: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80011a6: 2300 movs r3, #0
80011a8: 61bb str r3, [r7, #24]
HAL_GPIO_Init(BOOT1_GPIO_Port, &GPIO_InitStruct);
80011aa: f107 0310 add.w r3, r7, #16
80011ae: 4619 mov r1, r3
80011b0: 4805 ldr r0, [pc, #20] ; (80011c8 <MX_GPIO_Init+0xc8>)
80011b2: f000 ff43 bl 800203c <HAL_GPIO_Init>
}
80011b6: bf00 nop
80011b8: 3720 adds r7, #32
80011ba: 46bd mov sp, r7
80011bc: bd80 pop {r7, pc}
80011be: bf00 nop
80011c0: 40021000 .word 0x40021000
80011c4: 40011000 .word 0x40011000
80011c8: 40010c00 .word 0x40010c00
080011cc <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
80011cc: b480 push {r7}
80011ce: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
80011d0: b672 cpsid i
}
80011d2: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
80011d4: e7fe b.n 80011d4 <Error_Handler+0x8>
...
080011d8 <HAL_MspInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
80011d8: b480 push {r7}
80011da: b085 sub sp, #20
80011dc: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_AFIO_CLK_ENABLE();
80011de: 4b15 ldr r3, [pc, #84] ; (8001234 <HAL_MspInit+0x5c>)
80011e0: 699b ldr r3, [r3, #24]
80011e2: 4a14 ldr r2, [pc, #80] ; (8001234 <HAL_MspInit+0x5c>)
80011e4: f043 0301 orr.w r3, r3, #1
80011e8: 6193 str r3, [r2, #24]
80011ea: 4b12 ldr r3, [pc, #72] ; (8001234 <HAL_MspInit+0x5c>)
80011ec: 699b ldr r3, [r3, #24]
80011ee: f003 0301 and.w r3, r3, #1
80011f2: 60bb str r3, [r7, #8]
80011f4: 68bb ldr r3, [r7, #8]
__HAL_RCC_PWR_CLK_ENABLE();
80011f6: 4b0f ldr r3, [pc, #60] ; (8001234 <HAL_MspInit+0x5c>)
80011f8: 69db ldr r3, [r3, #28]
80011fa: 4a0e ldr r2, [pc, #56] ; (8001234 <HAL_MspInit+0x5c>)
80011fc: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8001200: 61d3 str r3, [r2, #28]
8001202: 4b0c ldr r3, [pc, #48] ; (8001234 <HAL_MspInit+0x5c>)
8001204: 69db ldr r3, [r3, #28]
8001206: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
800120a: 607b str r3, [r7, #4]
800120c: 687b ldr r3, [r7, #4]
/* System interrupt init*/
/** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
*/
__HAL_AFIO_REMAP_SWJ_NOJTAG();
800120e: 4b0a ldr r3, [pc, #40] ; (8001238 <HAL_MspInit+0x60>)
8001210: 685b ldr r3, [r3, #4]
8001212: 60fb str r3, [r7, #12]
8001214: 68fb ldr r3, [r7, #12]
8001216: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000
800121a: 60fb str r3, [r7, #12]
800121c: 68fb ldr r3, [r7, #12]
800121e: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000
8001222: 60fb str r3, [r7, #12]
8001224: 4a04 ldr r2, [pc, #16] ; (8001238 <HAL_MspInit+0x60>)
8001226: 68fb ldr r3, [r7, #12]
8001228: 6053 str r3, [r2, #4]
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
800122a: bf00 nop
800122c: 3714 adds r7, #20
800122e: 46bd mov sp, r7
8001230: bc80 pop {r7}
8001232: 4770 bx lr
8001234: 40021000 .word 0x40021000
8001238: 40010000 .word 0x40010000
0800123c <HAL_TIM_Encoder_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_encoder: TIM_Encoder handle pointer
* @retval None
*/
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder)
{
800123c: b580 push {r7, lr}
800123e: b08a sub sp, #40 ; 0x28
8001240: af00 add r7, sp, #0
8001242: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001244: f107 0318 add.w r3, r7, #24
8001248: 2200 movs r2, #0
800124a: 601a str r2, [r3, #0]
800124c: 605a str r2, [r3, #4]
800124e: 609a str r2, [r3, #8]
8001250: 60da str r2, [r3, #12]
if(htim_encoder->Instance==TIM1)
8001252: 687b ldr r3, [r7, #4]
8001254: 681b ldr r3, [r3, #0]
8001256: 4a2b ldr r2, [pc, #172] ; (8001304 <HAL_TIM_Encoder_MspInit+0xc8>)
8001258: 4293 cmp r3, r2
800125a: d125 bne.n 80012a8 <HAL_TIM_Encoder_MspInit+0x6c>
{
/* USER CODE BEGIN TIM1_MspInit 0 */
/* USER CODE END TIM1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM1_CLK_ENABLE();
800125c: 4b2a ldr r3, [pc, #168] ; (8001308 <HAL_TIM_Encoder_MspInit+0xcc>)
800125e: 699b ldr r3, [r3, #24]
8001260: 4a29 ldr r2, [pc, #164] ; (8001308 <HAL_TIM_Encoder_MspInit+0xcc>)
8001262: f443 6300 orr.w r3, r3, #2048 ; 0x800
8001266: 6193 str r3, [r2, #24]
8001268: 4b27 ldr r3, [pc, #156] ; (8001308 <HAL_TIM_Encoder_MspInit+0xcc>)
800126a: 699b ldr r3, [r3, #24]
800126c: f403 6300 and.w r3, r3, #2048 ; 0x800
8001270: 617b str r3, [r7, #20]
8001272: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001274: 4b24 ldr r3, [pc, #144] ; (8001308 <HAL_TIM_Encoder_MspInit+0xcc>)
8001276: 699b ldr r3, [r3, #24]
8001278: 4a23 ldr r2, [pc, #140] ; (8001308 <HAL_TIM_Encoder_MspInit+0xcc>)
800127a: f043 0304 orr.w r3, r3, #4
800127e: 6193 str r3, [r2, #24]
8001280: 4b21 ldr r3, [pc, #132] ; (8001308 <HAL_TIM_Encoder_MspInit+0xcc>)
8001282: 699b ldr r3, [r3, #24]
8001284: f003 0304 and.w r3, r3, #4
8001288: 613b str r3, [r7, #16]
800128a: 693b ldr r3, [r7, #16]
/**TIM1 GPIO Configuration
PA8 ------> TIM1_CH1
PA9 ------> TIM1_CH2
*/
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9;
800128c: f44f 7340 mov.w r3, #768 ; 0x300
8001290: 61bb str r3, [r7, #24]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001292: 2300 movs r3, #0
8001294: 61fb str r3, [r7, #28]
GPIO_InitStruct.Pull = GPIO_PULLUP;
8001296: 2301 movs r3, #1
8001298: 623b str r3, [r7, #32]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800129a: f107 0318 add.w r3, r7, #24
800129e: 4619 mov r1, r3
80012a0: 481a ldr r0, [pc, #104] ; (800130c <HAL_TIM_Encoder_MspInit+0xd0>)
80012a2: f000 fecb bl 800203c <HAL_GPIO_Init>
/* USER CODE BEGIN TIM3_MspInit 1 */
/* USER CODE END TIM3_MspInit 1 */
}
}
80012a6: e028 b.n 80012fa <HAL_TIM_Encoder_MspInit+0xbe>
else if(htim_encoder->Instance==TIM3)
80012a8: 687b ldr r3, [r7, #4]
80012aa: 681b ldr r3, [r3, #0]
80012ac: 4a18 ldr r2, [pc, #96] ; (8001310 <HAL_TIM_Encoder_MspInit+0xd4>)
80012ae: 4293 cmp r3, r2
80012b0: d123 bne.n 80012fa <HAL_TIM_Encoder_MspInit+0xbe>
__HAL_RCC_TIM3_CLK_ENABLE();
80012b2: 4b15 ldr r3, [pc, #84] ; (8001308 <HAL_TIM_Encoder_MspInit+0xcc>)
80012b4: 69db ldr r3, [r3, #28]
80012b6: 4a14 ldr r2, [pc, #80] ; (8001308 <HAL_TIM_Encoder_MspInit+0xcc>)
80012b8: f043 0302 orr.w r3, r3, #2
80012bc: 61d3 str r3, [r2, #28]
80012be: 4b12 ldr r3, [pc, #72] ; (8001308 <HAL_TIM_Encoder_MspInit+0xcc>)
80012c0: 69db ldr r3, [r3, #28]
80012c2: f003 0302 and.w r3, r3, #2
80012c6: 60fb str r3, [r7, #12]
80012c8: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
80012ca: 4b0f ldr r3, [pc, #60] ; (8001308 <HAL_TIM_Encoder_MspInit+0xcc>)
80012cc: 699b ldr r3, [r3, #24]
80012ce: 4a0e ldr r2, [pc, #56] ; (8001308 <HAL_TIM_Encoder_MspInit+0xcc>)
80012d0: f043 0304 orr.w r3, r3, #4
80012d4: 6193 str r3, [r2, #24]
80012d6: 4b0c ldr r3, [pc, #48] ; (8001308 <HAL_TIM_Encoder_MspInit+0xcc>)
80012d8: 699b ldr r3, [r3, #24]
80012da: f003 0304 and.w r3, r3, #4
80012de: 60bb str r3, [r7, #8]
80012e0: 68bb ldr r3, [r7, #8]
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
80012e2: 23c0 movs r3, #192 ; 0xc0
80012e4: 61bb str r3, [r7, #24]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
80012e6: 2300 movs r3, #0
80012e8: 61fb str r3, [r7, #28]
GPIO_InitStruct.Pull = GPIO_PULLUP;
80012ea: 2301 movs r3, #1
80012ec: 623b str r3, [r7, #32]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80012ee: f107 0318 add.w r3, r7, #24
80012f2: 4619 mov r1, r3
80012f4: 4805 ldr r0, [pc, #20] ; (800130c <HAL_TIM_Encoder_MspInit+0xd0>)
80012f6: f000 fea1 bl 800203c <HAL_GPIO_Init>
}
80012fa: bf00 nop
80012fc: 3728 adds r7, #40 ; 0x28
80012fe: 46bd mov sp, r7
8001300: bd80 pop {r7, pc}
8001302: bf00 nop
8001304: 40012c00 .word 0x40012c00
8001308: 40021000 .word 0x40021000
800130c: 40010800 .word 0x40010800
8001310: 40000400 .word 0x40000400
08001314 <HAL_TIM_PWM_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_pwm: TIM_PWM handle pointer
* @retval None
*/
void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm)
{
8001314: b480 push {r7}
8001316: b085 sub sp, #20
8001318: af00 add r7, sp, #0
800131a: 6078 str r0, [r7, #4]
if(htim_pwm->Instance==TIM2)
800131c: 687b ldr r3, [r7, #4]
800131e: 681b ldr r3, [r3, #0]
8001320: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8001324: d10b bne.n 800133e <HAL_TIM_PWM_MspInit+0x2a>
{
/* USER CODE BEGIN TIM2_MspInit 0 */
/* USER CODE END TIM2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM2_CLK_ENABLE();
8001326: 4b08 ldr r3, [pc, #32] ; (8001348 <HAL_TIM_PWM_MspInit+0x34>)
8001328: 69db ldr r3, [r3, #28]
800132a: 4a07 ldr r2, [pc, #28] ; (8001348 <HAL_TIM_PWM_MspInit+0x34>)
800132c: f043 0301 orr.w r3, r3, #1
8001330: 61d3 str r3, [r2, #28]
8001332: 4b05 ldr r3, [pc, #20] ; (8001348 <HAL_TIM_PWM_MspInit+0x34>)
8001334: 69db ldr r3, [r3, #28]
8001336: f003 0301 and.w r3, r3, #1
800133a: 60fb str r3, [r7, #12]
800133c: 68fb ldr r3, [r7, #12]
/* USER CODE BEGIN TIM2_MspInit 1 */
/* USER CODE END TIM2_MspInit 1 */
}
}
800133e: bf00 nop
8001340: 3714 adds r7, #20
8001342: 46bd mov sp, r7
8001344: bc80 pop {r7}
8001346: 4770 bx lr
8001348: 40021000 .word 0x40021000
0800134c <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
800134c: b580 push {r7, lr}
800134e: b084 sub sp, #16
8001350: af00 add r7, sp, #0
8001352: 6078 str r0, [r7, #4]
if(htim_base->Instance==TIM4)
8001354: 687b ldr r3, [r7, #4]
8001356: 681b ldr r3, [r3, #0]
8001358: 4a0d ldr r2, [pc, #52] ; (8001390 <HAL_TIM_Base_MspInit+0x44>)
800135a: 4293 cmp r3, r2
800135c: d113 bne.n 8001386 <HAL_TIM_Base_MspInit+0x3a>
{
/* USER CODE BEGIN TIM4_MspInit 0 */
/* USER CODE END TIM4_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM4_CLK_ENABLE();
800135e: 4b0d ldr r3, [pc, #52] ; (8001394 <HAL_TIM_Base_MspInit+0x48>)
8001360: 69db ldr r3, [r3, #28]
8001362: 4a0c ldr r2, [pc, #48] ; (8001394 <HAL_TIM_Base_MspInit+0x48>)
8001364: f043 0304 orr.w r3, r3, #4
8001368: 61d3 str r3, [r2, #28]
800136a: 4b0a ldr r3, [pc, #40] ; (8001394 <HAL_TIM_Base_MspInit+0x48>)
800136c: 69db ldr r3, [r3, #28]
800136e: f003 0304 and.w r3, r3, #4
8001372: 60fb str r3, [r7, #12]
8001374: 68fb ldr r3, [r7, #12]
/* TIM4 interrupt Init */
HAL_NVIC_SetPriority(TIM4_IRQn, 15, 0);
8001376: 2200 movs r2, #0
8001378: 210f movs r1, #15
800137a: 201e movs r0, #30
800137c: f000 fb89 bl 8001a92 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM4_IRQn);
8001380: 201e movs r0, #30
8001382: f000 fba2 bl 8001aca <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN TIM4_MspInit 1 */
/* USER CODE END TIM4_MspInit 1 */
}
}
8001386: bf00 nop
8001388: 3710 adds r7, #16
800138a: 46bd mov sp, r7
800138c: bd80 pop {r7, pc}
800138e: bf00 nop
8001390: 40000800 .word 0x40000800
8001394: 40021000 .word 0x40021000
08001398 <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
8001398: b580 push {r7, lr}
800139a: b08a sub sp, #40 ; 0x28
800139c: af00 add r7, sp, #0
800139e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80013a0: f107 0314 add.w r3, r7, #20
80013a4: 2200 movs r2, #0
80013a6: 601a str r2, [r3, #0]
80013a8: 605a str r2, [r3, #4]
80013aa: 609a str r2, [r3, #8]
80013ac: 60da str r2, [r3, #12]
if(htim->Instance==TIM2)
80013ae: 687b ldr r3, [r7, #4]
80013b0: 681b ldr r3, [r3, #0]
80013b2: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
80013b6: d143 bne.n 8001440 <HAL_TIM_MspPostInit+0xa8>
{
/* USER CODE BEGIN TIM2_MspPostInit 0 */
/* USER CODE END TIM2_MspPostInit 0 */
__HAL_RCC_GPIOB_CLK_ENABLE();
80013b8: 4b23 ldr r3, [pc, #140] ; (8001448 <HAL_TIM_MspPostInit+0xb0>)
80013ba: 699b ldr r3, [r3, #24]
80013bc: 4a22 ldr r2, [pc, #136] ; (8001448 <HAL_TIM_MspPostInit+0xb0>)
80013be: f043 0308 orr.w r3, r3, #8
80013c2: 6193 str r3, [r2, #24]
80013c4: 4b20 ldr r3, [pc, #128] ; (8001448 <HAL_TIM_MspPostInit+0xb0>)
80013c6: 699b ldr r3, [r3, #24]
80013c8: f003 0308 and.w r3, r3, #8
80013cc: 613b str r3, [r7, #16]
80013ce: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
80013d0: 4b1d ldr r3, [pc, #116] ; (8001448 <HAL_TIM_MspPostInit+0xb0>)
80013d2: 699b ldr r3, [r3, #24]
80013d4: 4a1c ldr r2, [pc, #112] ; (8001448 <HAL_TIM_MspPostInit+0xb0>)
80013d6: f043 0304 orr.w r3, r3, #4
80013da: 6193 str r3, [r2, #24]
80013dc: 4b1a ldr r3, [pc, #104] ; (8001448 <HAL_TIM_MspPostInit+0xb0>)
80013de: 699b ldr r3, [r3, #24]
80013e0: f003 0304 and.w r3, r3, #4
80013e4: 60fb str r3, [r7, #12]
80013e6: 68fb ldr r3, [r7, #12]
PB10 ------> TIM2_CH3
PB11 ------> TIM2_CH4
PA15 ------> TIM2_CH1
PB3 ------> TIM2_CH2
*/
GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_3;
80013e8: f640 4308 movw r3, #3080 ; 0xc08
80013ec: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80013ee: 2302 movs r3, #2
80013f0: 61bb str r3, [r7, #24]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80013f2: 2302 movs r3, #2
80013f4: 623b str r3, [r7, #32]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80013f6: f107 0314 add.w r3, r7, #20
80013fa: 4619 mov r1, r3
80013fc: 4813 ldr r0, [pc, #76] ; (800144c <HAL_TIM_MspPostInit+0xb4>)
80013fe: f000 fe1d bl 800203c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_15;
8001402: f44f 4300 mov.w r3, #32768 ; 0x8000
8001406: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001408: 2302 movs r3, #2
800140a: 61bb str r3, [r7, #24]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800140c: 2302 movs r3, #2
800140e: 623b str r3, [r7, #32]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001410: f107 0314 add.w r3, r7, #20
8001414: 4619 mov r1, r3
8001416: 480e ldr r0, [pc, #56] ; (8001450 <HAL_TIM_MspPostInit+0xb8>)
8001418: f000 fe10 bl 800203c <HAL_GPIO_Init>
__HAL_AFIO_REMAP_TIM2_ENABLE();
800141c: 4b0d ldr r3, [pc, #52] ; (8001454 <HAL_TIM_MspPostInit+0xbc>)
800141e: 685b ldr r3, [r3, #4]
8001420: 627b str r3, [r7, #36] ; 0x24
8001422: 6a7b ldr r3, [r7, #36] ; 0x24
8001424: f423 7340 bic.w r3, r3, #768 ; 0x300
8001428: 627b str r3, [r7, #36] ; 0x24
800142a: 6a7b ldr r3, [r7, #36] ; 0x24
800142c: f043 63e0 orr.w r3, r3, #117440512 ; 0x7000000
8001430: 627b str r3, [r7, #36] ; 0x24
8001432: 6a7b ldr r3, [r7, #36] ; 0x24
8001434: f443 7340 orr.w r3, r3, #768 ; 0x300
8001438: 627b str r3, [r7, #36] ; 0x24
800143a: 4a06 ldr r2, [pc, #24] ; (8001454 <HAL_TIM_MspPostInit+0xbc>)
800143c: 6a7b ldr r3, [r7, #36] ; 0x24
800143e: 6053 str r3, [r2, #4]
/* USER CODE BEGIN TIM2_MspPostInit 1 */
/* USER CODE END TIM2_MspPostInit 1 */
}
}
8001440: bf00 nop
8001442: 3728 adds r7, #40 ; 0x28
8001444: 46bd mov sp, r7
8001446: bd80 pop {r7, pc}
8001448: 40021000 .word 0x40021000
800144c: 40010c00 .word 0x40010c00
8001450: 40010800 .word 0x40010800
8001454: 40010000 .word 0x40010000
08001458 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
8001458: b580 push {r7, lr}
800145a: b08c sub sp, #48 ; 0x30
800145c: af00 add r7, sp, #0
800145e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001460: f107 031c add.w r3, r7, #28
8001464: 2200 movs r2, #0
8001466: 601a str r2, [r3, #0]
8001468: 605a str r2, [r3, #4]
800146a: 609a str r2, [r3, #8]
800146c: 60da str r2, [r3, #12]
if(huart->Instance==USART1)
800146e: 687b ldr r3, [r7, #4]
8001470: 681b ldr r3, [r3, #0]
8001472: 4a58 ldr r2, [pc, #352] ; (80015d4 <HAL_UART_MspInit+0x17c>)
8001474: 4293 cmp r3, r2
8001476: d146 bne.n 8001506 <HAL_UART_MspInit+0xae>
{
/* USER CODE BEGIN USART1_MspInit 0 */
/* USER CODE END USART1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USART1_CLK_ENABLE();
8001478: 4b57 ldr r3, [pc, #348] ; (80015d8 <HAL_UART_MspInit+0x180>)
800147a: 699b ldr r3, [r3, #24]
800147c: 4a56 ldr r2, [pc, #344] ; (80015d8 <HAL_UART_MspInit+0x180>)
800147e: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8001482: 6193 str r3, [r2, #24]
8001484: 4b54 ldr r3, [pc, #336] ; (80015d8 <HAL_UART_MspInit+0x180>)
8001486: 699b ldr r3, [r3, #24]
8001488: f403 4380 and.w r3, r3, #16384 ; 0x4000
800148c: 61bb str r3, [r7, #24]
800148e: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOB_CLK_ENABLE();
8001490: 4b51 ldr r3, [pc, #324] ; (80015d8 <HAL_UART_MspInit+0x180>)
8001492: 699b ldr r3, [r3, #24]
8001494: 4a50 ldr r2, [pc, #320] ; (80015d8 <HAL_UART_MspInit+0x180>)
8001496: f043 0308 orr.w r3, r3, #8
800149a: 6193 str r3, [r2, #24]
800149c: 4b4e ldr r3, [pc, #312] ; (80015d8 <HAL_UART_MspInit+0x180>)
800149e: 699b ldr r3, [r3, #24]
80014a0: f003 0308 and.w r3, r3, #8
80014a4: 617b str r3, [r7, #20]
80014a6: 697b ldr r3, [r7, #20]
/**USART1 GPIO Configuration
PB6 ------> USART1_TX
PB7 ------> USART1_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_6;
80014a8: 2340 movs r3, #64 ; 0x40
80014aa: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80014ac: 2302 movs r3, #2
80014ae: 623b str r3, [r7, #32]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
80014b0: 2303 movs r3, #3
80014b2: 62bb str r3, [r7, #40] ; 0x28
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80014b4: f107 031c add.w r3, r7, #28
80014b8: 4619 mov r1, r3
80014ba: 4848 ldr r0, [pc, #288] ; (80015dc <HAL_UART_MspInit+0x184>)
80014bc: f000 fdbe bl 800203c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_7;
80014c0: 2380 movs r3, #128 ; 0x80
80014c2: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
80014c4: 2300 movs r3, #0
80014c6: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80014c8: 2300 movs r3, #0
80014ca: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80014cc: f107 031c add.w r3, r7, #28
80014d0: 4619 mov r1, r3
80014d2: 4842 ldr r0, [pc, #264] ; (80015dc <HAL_UART_MspInit+0x184>)
80014d4: f000 fdb2 bl 800203c <HAL_GPIO_Init>
__HAL_AFIO_REMAP_USART1_ENABLE();
80014d8: 4b41 ldr r3, [pc, #260] ; (80015e0 <HAL_UART_MspInit+0x188>)
80014da: 685b ldr r3, [r3, #4]
80014dc: 62fb str r3, [r7, #44] ; 0x2c
80014de: 6afb ldr r3, [r7, #44] ; 0x2c
80014e0: f043 63e0 orr.w r3, r3, #117440512 ; 0x7000000
80014e4: 62fb str r3, [r7, #44] ; 0x2c
80014e6: 6afb ldr r3, [r7, #44] ; 0x2c
80014e8: f043 0304 orr.w r3, r3, #4
80014ec: 62fb str r3, [r7, #44] ; 0x2c
80014ee: 4a3c ldr r2, [pc, #240] ; (80015e0 <HAL_UART_MspInit+0x188>)
80014f0: 6afb ldr r3, [r7, #44] ; 0x2c
80014f2: 6053 str r3, [r2, #4]
/* USART1 interrupt Init */
HAL_NVIC_SetPriority(USART1_IRQn, 7, 0);
80014f4: 2200 movs r2, #0
80014f6: 2107 movs r1, #7
80014f8: 2025 movs r0, #37 ; 0x25
80014fa: f000 faca bl 8001a92 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(USART1_IRQn);
80014fe: 2025 movs r0, #37 ; 0x25
8001500: f000 fae3 bl 8001aca <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN USART2_MspInit 1 */
/* USER CODE END USART2_MspInit 1 */
}
}
8001504: e062 b.n 80015cc <HAL_UART_MspInit+0x174>
else if(huart->Instance==USART2)
8001506: 687b ldr r3, [r7, #4]
8001508: 681b ldr r3, [r3, #0]
800150a: 4a36 ldr r2, [pc, #216] ; (80015e4 <HAL_UART_MspInit+0x18c>)
800150c: 4293 cmp r3, r2
800150e: d15d bne.n 80015cc <HAL_UART_MspInit+0x174>
__HAL_RCC_USART2_CLK_ENABLE();
8001510: 4b31 ldr r3, [pc, #196] ; (80015d8 <HAL_UART_MspInit+0x180>)
8001512: 69db ldr r3, [r3, #28]
8001514: 4a30 ldr r2, [pc, #192] ; (80015d8 <HAL_UART_MspInit+0x180>)
8001516: f443 3300 orr.w r3, r3, #131072 ; 0x20000
800151a: 61d3 str r3, [r2, #28]
800151c: 4b2e ldr r3, [pc, #184] ; (80015d8 <HAL_UART_MspInit+0x180>)
800151e: 69db ldr r3, [r3, #28]
8001520: f403 3300 and.w r3, r3, #131072 ; 0x20000
8001524: 613b str r3, [r7, #16]
8001526: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001528: 4b2b ldr r3, [pc, #172] ; (80015d8 <HAL_UART_MspInit+0x180>)
800152a: 699b ldr r3, [r3, #24]
800152c: 4a2a ldr r2, [pc, #168] ; (80015d8 <HAL_UART_MspInit+0x180>)
800152e: f043 0304 orr.w r3, r3, #4
8001532: 6193 str r3, [r2, #24]
8001534: 4b28 ldr r3, [pc, #160] ; (80015d8 <HAL_UART_MspInit+0x180>)
8001536: 699b ldr r3, [r3, #24]
8001538: f003 0304 and.w r3, r3, #4
800153c: 60fb str r3, [r7, #12]
800153e: 68fb ldr r3, [r7, #12]
GPIO_InitStruct.Pin = GPIO_PIN_2;
8001540: 2304 movs r3, #4
8001542: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001544: 2302 movs r3, #2
8001546: 623b str r3, [r7, #32]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
8001548: 2303 movs r3, #3
800154a: 62bb str r3, [r7, #40] ; 0x28
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800154c: f107 031c add.w r3, r7, #28
8001550: 4619 mov r1, r3
8001552: 4825 ldr r0, [pc, #148] ; (80015e8 <HAL_UART_MspInit+0x190>)
8001554: f000 fd72 bl 800203c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_3;
8001558: 2308 movs r3, #8
800155a: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
800155c: 2300 movs r3, #0
800155e: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001560: 2300 movs r3, #0
8001562: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001564: f107 031c add.w r3, r7, #28
8001568: 4619 mov r1, r3
800156a: 481f ldr r0, [pc, #124] ; (80015e8 <HAL_UART_MspInit+0x190>)
800156c: f000 fd66 bl 800203c <HAL_GPIO_Init>
hdma_usart2_tx.Instance = DMA1_Channel7;
8001570: 4b1e ldr r3, [pc, #120] ; (80015ec <HAL_UART_MspInit+0x194>)
8001572: 4a1f ldr r2, [pc, #124] ; (80015f0 <HAL_UART_MspInit+0x198>)
8001574: 601a str r2, [r3, #0]
hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
8001576: 4b1d ldr r3, [pc, #116] ; (80015ec <HAL_UART_MspInit+0x194>)
8001578: 2210 movs r2, #16
800157a: 605a str r2, [r3, #4]
hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE;
800157c: 4b1b ldr r3, [pc, #108] ; (80015ec <HAL_UART_MspInit+0x194>)
800157e: 2200 movs r2, #0
8001580: 609a str r2, [r3, #8]
hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE;
8001582: 4b1a ldr r3, [pc, #104] ; (80015ec <HAL_UART_MspInit+0x194>)
8001584: 2280 movs r2, #128 ; 0x80
8001586: 60da str r2, [r3, #12]
hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
8001588: 4b18 ldr r3, [pc, #96] ; (80015ec <HAL_UART_MspInit+0x194>)
800158a: 2200 movs r2, #0
800158c: 611a str r2, [r3, #16]
hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
800158e: 4b17 ldr r3, [pc, #92] ; (80015ec <HAL_UART_MspInit+0x194>)
8001590: 2200 movs r2, #0
8001592: 615a str r2, [r3, #20]
hdma_usart2_tx.Init.Mode = DMA_NORMAL;
8001594: 4b15 ldr r3, [pc, #84] ; (80015ec <HAL_UART_MspInit+0x194>)
8001596: 2200 movs r2, #0
8001598: 619a str r2, [r3, #24]
hdma_usart2_tx.Init.Priority = DMA_PRIORITY_LOW;
800159a: 4b14 ldr r3, [pc, #80] ; (80015ec <HAL_UART_MspInit+0x194>)
800159c: 2200 movs r2, #0
800159e: 61da str r2, [r3, #28]
if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK)
80015a0: 4812 ldr r0, [pc, #72] ; (80015ec <HAL_UART_MspInit+0x194>)
80015a2: f000 faad bl 8001b00 <HAL_DMA_Init>
80015a6: 4603 mov r3, r0
80015a8: 2b00 cmp r3, #0
80015aa: d001 beq.n 80015b0 <HAL_UART_MspInit+0x158>
Error_Handler();
80015ac: f7ff fe0e bl 80011cc <Error_Handler>
__HAL_LINKDMA(huart,hdmatx,hdma_usart2_tx);
80015b0: 687b ldr r3, [r7, #4]
80015b2: 4a0e ldr r2, [pc, #56] ; (80015ec <HAL_UART_MspInit+0x194>)
80015b4: 635a str r2, [r3, #52] ; 0x34
80015b6: 4a0d ldr r2, [pc, #52] ; (80015ec <HAL_UART_MspInit+0x194>)
80015b8: 687b ldr r3, [r7, #4]
80015ba: 6253 str r3, [r2, #36] ; 0x24
HAL_NVIC_SetPriority(USART2_IRQn, 0, 0);
80015bc: 2200 movs r2, #0
80015be: 2100 movs r1, #0
80015c0: 2026 movs r0, #38 ; 0x26
80015c2: f000 fa66 bl 8001a92 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(USART2_IRQn);
80015c6: 2026 movs r0, #38 ; 0x26
80015c8: f000 fa7f bl 8001aca <HAL_NVIC_EnableIRQ>
}
80015cc: bf00 nop
80015ce: 3730 adds r7, #48 ; 0x30
80015d0: 46bd mov sp, r7
80015d2: bd80 pop {r7, pc}
80015d4: 40013800 .word 0x40013800
80015d8: 40021000 .word 0x40021000
80015dc: 40010c00 .word 0x40010c00
80015e0: 40010000 .word 0x40010000
80015e4: 40004400 .word 0x40004400
80015e8: 40010800 .word 0x40010800
80015ec: 20000558 .word 0x20000558
80015f0: 40020080 .word 0x40020080
080015f4 <HAL_PCD_MspInit>:
* This function configures the hardware resources used in this example
* @param hpcd: PCD handle pointer
* @retval None
*/
void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd)
{
80015f4: b480 push {r7}
80015f6: b085 sub sp, #20
80015f8: af00 add r7, sp, #0
80015fa: 6078 str r0, [r7, #4]
if(hpcd->Instance==USB)
80015fc: 687b ldr r3, [r7, #4]
80015fe: 681b ldr r3, [r3, #0]
8001600: 4a09 ldr r2, [pc, #36] ; (8001628 <HAL_PCD_MspInit+0x34>)
8001602: 4293 cmp r3, r2
8001604: d10b bne.n 800161e <HAL_PCD_MspInit+0x2a>
{
/* USER CODE BEGIN USB_MspInit 0 */
/* USER CODE END USB_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USB_CLK_ENABLE();
8001606: 4b09 ldr r3, [pc, #36] ; (800162c <HAL_PCD_MspInit+0x38>)
8001608: 69db ldr r3, [r3, #28]
800160a: 4a08 ldr r2, [pc, #32] ; (800162c <HAL_PCD_MspInit+0x38>)
800160c: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
8001610: 61d3 str r3, [r2, #28]
8001612: 4b06 ldr r3, [pc, #24] ; (800162c <HAL_PCD_MspInit+0x38>)
8001614: 69db ldr r3, [r3, #28]
8001616: f403 0300 and.w r3, r3, #8388608 ; 0x800000
800161a: 60fb str r3, [r7, #12]
800161c: 68fb ldr r3, [r7, #12]
/* USER CODE BEGIN USB_MspInit 1 */
/* USER CODE END USB_MspInit 1 */
}
}
800161e: bf00 nop
8001620: 3714 adds r7, #20
8001622: 46bd mov sp, r7
8001624: bc80 pop {r7}
8001626: 4770 bx lr
8001628: 40005c00 .word 0x40005c00
800162c: 40021000 .word 0x40021000
08001630 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8001630: b480 push {r7}
8001632: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8001634: e7fe b.n 8001634 <NMI_Handler+0x4>
08001636 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8001636: b480 push {r7}
8001638: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
800163a: e7fe b.n 800163a <HardFault_Handler+0x4>
0800163c <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
800163c: b480 push {r7}
800163e: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8001640: e7fe b.n 8001640 <MemManage_Handler+0x4>
08001642 <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8001642: b480 push {r7}
8001644: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8001646: e7fe b.n 8001646 <BusFault_Handler+0x4>
08001648 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8001648: b480 push {r7}
800164a: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
800164c: e7fe b.n 800164c <UsageFault_Handler+0x4>
0800164e <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
800164e: b480 push {r7}
8001650: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
8001652: bf00 nop
8001654: 46bd mov sp, r7
8001656: bc80 pop {r7}
8001658: 4770 bx lr
0800165a <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
800165a: b480 push {r7}
800165c: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
800165e: bf00 nop
8001660: 46bd mov sp, r7
8001662: bc80 pop {r7}
8001664: 4770 bx lr
08001666 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8001666: b480 push {r7}
8001668: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
800166a: bf00 nop
800166c: 46bd mov sp, r7
800166e: bc80 pop {r7}
8001670: 4770 bx lr
08001672 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8001672: b580 push {r7, lr}
8001674: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8001676: f000 f8f5 bl 8001864 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
800167a: bf00 nop
800167c: bd80 pop {r7, pc}
...
08001680 <DMA1_Channel7_IRQHandler>:
/**
* @brief This function handles DMA1 channel7 global interrupt.
*/
void DMA1_Channel7_IRQHandler(void)
{
8001680: b580 push {r7, lr}
8001682: af00 add r7, sp, #0
/* USER CODE BEGIN DMA1_Channel7_IRQn 0 */
/* USER CODE END DMA1_Channel7_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_usart2_tx);
8001684: 4802 ldr r0, [pc, #8] ; (8001690 <DMA1_Channel7_IRQHandler+0x10>)
8001686: f000 fba5 bl 8001dd4 <HAL_DMA_IRQHandler>
/* USER CODE BEGIN DMA1_Channel7_IRQn 1 */
/* USER CODE END DMA1_Channel7_IRQn 1 */
}
800168a: bf00 nop
800168c: bd80 pop {r7, pc}
800168e: bf00 nop
8001690: 20000558 .word 0x20000558
08001694 <TIM4_IRQHandler>:
/**
* @brief This function handles TIM4 global interrupt.
*/
void TIM4_IRQHandler(void)
{
8001694: b580 push {r7, lr}
8001696: af00 add r7, sp, #0
/* USER CODE BEGIN TIM4_IRQn 0 */
/* USER CODE END TIM4_IRQn 0 */
HAL_TIM_IRQHandler(&htim4);
8001698: 4802 ldr r0, [pc, #8] ; (80016a4 <TIM4_IRQHandler+0x10>)
800169a: f001 ff03 bl 80034a4 <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM4_IRQn 1 */
/* USER CODE END TIM4_IRQn 1 */
}
800169e: bf00 nop
80016a0: bd80 pop {r7, pc}
80016a2: bf00 nop
80016a4: 20000488 .word 0x20000488
080016a8 <USART1_IRQHandler>:
/**
* @brief This function handles USART1 global interrupt.
*/
void USART1_IRQHandler(void)
{
80016a8: b580 push {r7, lr}
80016aa: af00 add r7, sp, #0
/* USER CODE BEGIN USART1_IRQn 0 */
/* USER CODE END USART1_IRQn 0 */
HAL_UART_IRQHandler(&huart1);
80016ac: 4802 ldr r0, [pc, #8] ; (80016b8 <USART1_IRQHandler+0x10>)
80016ae: f002 fe71 bl 8004394 <HAL_UART_IRQHandler>
/* USER CODE BEGIN USART1_IRQn 1 */
/* USER CODE END USART1_IRQn 1 */
}
80016b2: bf00 nop
80016b4: bd80 pop {r7, pc}
80016b6: bf00 nop
80016b8: 200004d0 .word 0x200004d0
080016bc <USART2_IRQHandler>:
/**
* @brief This function handles USART2 global interrupt.
*/
void USART2_IRQHandler(void)
{
80016bc: b580 push {r7, lr}
80016be: af00 add r7, sp, #0
/* USER CODE BEGIN USART2_IRQn 0 */
/* USER CODE END USART2_IRQn 0 */
HAL_UART_IRQHandler(&huart2);
80016c0: 4802 ldr r0, [pc, #8] ; (80016cc <USART2_IRQHandler+0x10>)
80016c2: f002 fe67 bl 8004394 <HAL_UART_IRQHandler>
/* USER CODE BEGIN USART2_IRQn 1 */
/* USER CODE END USART2_IRQn 1 */
}
80016c6: bf00 nop
80016c8: bd80 pop {r7, pc}
80016ca: bf00 nop
80016cc: 20000514 .word 0x20000514
080016d0 <_getpid>:
void initialise_monitor_handles()
{
}
int _getpid(void)
{
80016d0: b480 push {r7}
80016d2: af00 add r7, sp, #0
return 1;
80016d4: 2301 movs r3, #1
}
80016d6: 4618 mov r0, r3
80016d8: 46bd mov sp, r7
80016da: bc80 pop {r7}
80016dc: 4770 bx lr
080016de <_kill>:
int _kill(int pid, int sig)
{
80016de: b580 push {r7, lr}
80016e0: b082 sub sp, #8
80016e2: af00 add r7, sp, #0
80016e4: 6078 str r0, [r7, #4]
80016e6: 6039 str r1, [r7, #0]
(void)pid;
(void)sig;
errno = EINVAL;
80016e8: f003 fb8c bl 8004e04 <__errno>
80016ec: 4603 mov r3, r0
80016ee: 2216 movs r2, #22
80016f0: 601a str r2, [r3, #0]
return -1;
80016f2: f04f 33ff mov.w r3, #4294967295
}
80016f6: 4618 mov r0, r3
80016f8: 3708 adds r7, #8
80016fa: 46bd mov sp, r7
80016fc: bd80 pop {r7, pc}
080016fe <_exit>:
void _exit (int status)
{
80016fe: b580 push {r7, lr}
8001700: b082 sub sp, #8
8001702: af00 add r7, sp, #0
8001704: 6078 str r0, [r7, #4]
_kill(status, -1);
8001706: f04f 31ff mov.w r1, #4294967295
800170a: 6878 ldr r0, [r7, #4]
800170c: f7ff ffe7 bl 80016de <_kill>
while (1) {} /* Make sure we hang here */
8001710: e7fe b.n 8001710 <_exit+0x12>
...
08001714 <_sbrk>:
*
* @param incr Memory size
* @return Pointer to allocated memory
*/
void *_sbrk(ptrdiff_t incr)
{
8001714: b580 push {r7, lr}
8001716: b086 sub sp, #24
8001718: af00 add r7, sp, #0
800171a: 6078 str r0, [r7, #4]
extern uint8_t _end; /* Symbol defined in the linker script */
extern uint8_t _estack; /* Symbol defined in the linker script */
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
800171c: 4a14 ldr r2, [pc, #80] ; (8001770 <_sbrk+0x5c>)
800171e: 4b15 ldr r3, [pc, #84] ; (8001774 <_sbrk+0x60>)
8001720: 1ad3 subs r3, r2, r3
8001722: 617b str r3, [r7, #20]
const uint8_t *max_heap = (uint8_t *)stack_limit;
8001724: 697b ldr r3, [r7, #20]
8001726: 613b str r3, [r7, #16]
uint8_t *prev_heap_end;
/* Initialize heap end at first call */
if (NULL == __sbrk_heap_end)
8001728: 4b13 ldr r3, [pc, #76] ; (8001778 <_sbrk+0x64>)
800172a: 681b ldr r3, [r3, #0]
800172c: 2b00 cmp r3, #0
800172e: d102 bne.n 8001736 <_sbrk+0x22>
{
__sbrk_heap_end = &_end;
8001730: 4b11 ldr r3, [pc, #68] ; (8001778 <_sbrk+0x64>)
8001732: 4a12 ldr r2, [pc, #72] ; (800177c <_sbrk+0x68>)
8001734: 601a str r2, [r3, #0]
}
/* Protect heap from growing into the reserved MSP stack */
if (__sbrk_heap_end + incr > max_heap)
8001736: 4b10 ldr r3, [pc, #64] ; (8001778 <_sbrk+0x64>)
8001738: 681a ldr r2, [r3, #0]
800173a: 687b ldr r3, [r7, #4]
800173c: 4413 add r3, r2
800173e: 693a ldr r2, [r7, #16]
8001740: 429a cmp r2, r3
8001742: d207 bcs.n 8001754 <_sbrk+0x40>
{
errno = ENOMEM;
8001744: f003 fb5e bl 8004e04 <__errno>
8001748: 4603 mov r3, r0
800174a: 220c movs r2, #12
800174c: 601a str r2, [r3, #0]
return (void *)-1;
800174e: f04f 33ff mov.w r3, #4294967295
8001752: e009 b.n 8001768 <_sbrk+0x54>
}
prev_heap_end = __sbrk_heap_end;
8001754: 4b08 ldr r3, [pc, #32] ; (8001778 <_sbrk+0x64>)
8001756: 681b ldr r3, [r3, #0]
8001758: 60fb str r3, [r7, #12]
__sbrk_heap_end += incr;
800175a: 4b07 ldr r3, [pc, #28] ; (8001778 <_sbrk+0x64>)
800175c: 681a ldr r2, [r3, #0]
800175e: 687b ldr r3, [r7, #4]
8001760: 4413 add r3, r2
8001762: 4a05 ldr r2, [pc, #20] ; (8001778 <_sbrk+0x64>)
8001764: 6013 str r3, [r2, #0]
return (void *)prev_heap_end;
8001766: 68fb ldr r3, [r7, #12]
}
8001768: 4618 mov r0, r3
800176a: 3718 adds r7, #24
800176c: 46bd mov sp, r7
800176e: bd80 pop {r7, pc}
8001770: 20005000 .word 0x20005000
8001774: 00000400 .word 0x00000400
8001778: 20000888 .word 0x20000888
800177c: 200008a8 .word 0x200008a8
08001780 <SystemInit>:
* @note This function should be used only after reset.
* @param None
* @retval None
*/
void SystemInit (void)
{
8001780: b480 push {r7}
8001782: af00 add r7, sp, #0
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#endif /* USER_VECT_TAB_ADDRESS */
}
8001784: bf00 nop
8001786: 46bd mov sp, r7
8001788: bc80 pop {r7}
800178a: 4770 bx lr
0800178c <Reset_Handler>:
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
800178c: 480c ldr r0, [pc, #48] ; (80017c0 <LoopFillZerobss+0x12>)
ldr r1, =_edata
800178e: 490d ldr r1, [pc, #52] ; (80017c4 <LoopFillZerobss+0x16>)
ldr r2, =_sidata
8001790: 4a0d ldr r2, [pc, #52] ; (80017c8 <LoopFillZerobss+0x1a>)
movs r3, #0
8001792: 2300 movs r3, #0
b LoopCopyDataInit
8001794: e002 b.n 800179c <LoopCopyDataInit>
08001796 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8001796: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8001798: 50c4 str r4, [r0, r3]
adds r3, r3, #4
800179a: 3304 adds r3, #4
0800179c <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
800179c: 18c4 adds r4, r0, r3
cmp r4, r1
800179e: 428c cmp r4, r1
bcc CopyDataInit
80017a0: d3f9 bcc.n 8001796 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
80017a2: 4a0a ldr r2, [pc, #40] ; (80017cc <LoopFillZerobss+0x1e>)
ldr r4, =_ebss
80017a4: 4c0a ldr r4, [pc, #40] ; (80017d0 <LoopFillZerobss+0x22>)
movs r3, #0
80017a6: 2300 movs r3, #0
b LoopFillZerobss
80017a8: e001 b.n 80017ae <LoopFillZerobss>
080017aa <FillZerobss>:
FillZerobss:
str r3, [r2]
80017aa: 6013 str r3, [r2, #0]
adds r2, r2, #4
80017ac: 3204 adds r2, #4
080017ae <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
80017ae: 42a2 cmp r2, r4
bcc FillZerobss
80017b0: d3fb bcc.n 80017aa <FillZerobss>
/* Call the clock system intitialization function.*/
bl SystemInit
80017b2: f7ff ffe5 bl 8001780 <SystemInit>
/* Call static constructors */
bl __libc_init_array
80017b6: f003 fb2b bl 8004e10 <__libc_init_array>
/* Call the application's entry point.*/
bl main
80017ba: f7ff fa24 bl 8000c06 <main>
bx lr
80017be: 4770 bx lr
ldr r0, =_sdata
80017c0: 20000000 .word 0x20000000
ldr r1, =_edata
80017c4: 20000070 .word 0x20000070
ldr r2, =_sidata
80017c8: 08005a8c .word 0x08005a8c
ldr r2, =_sbss
80017cc: 20000070 .word 0x20000070
ldr r4, =_ebss
80017d0: 200008a4 .word 0x200008a4
080017d4 <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
80017d4: e7fe b.n 80017d4 <ADC1_2_IRQHandler>
...
080017d8 <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
80017d8: b580 push {r7, lr}
80017da: af00 add r7, sp, #0
defined(STM32F102x6) || defined(STM32F102xB) || \
defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
defined(STM32F105xC) || defined(STM32F107xC)
/* Prefetch buffer is not available on value line devices */
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
80017dc: 4b08 ldr r3, [pc, #32] ; (8001800 <HAL_Init+0x28>)
80017de: 681b ldr r3, [r3, #0]
80017e0: 4a07 ldr r2, [pc, #28] ; (8001800 <HAL_Init+0x28>)
80017e2: f043 0310 orr.w r3, r3, #16
80017e6: 6013 str r3, [r2, #0]
#endif
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
80017e8: 2003 movs r0, #3
80017ea: f000 f947 bl 8001a7c <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
80017ee: 2000 movs r0, #0
80017f0: f000 f808 bl 8001804 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
80017f4: f7ff fcf0 bl 80011d8 <HAL_MspInit>
/* Return function status */
return HAL_OK;
80017f8: 2300 movs r3, #0
}
80017fa: 4618 mov r0, r3
80017fc: bd80 pop {r7, pc}
80017fe: bf00 nop
8001800: 40022000 .word 0x40022000
08001804 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8001804: b580 push {r7, lr}
8001806: b082 sub sp, #8
8001808: af00 add r7, sp, #0
800180a: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
800180c: 4b12 ldr r3, [pc, #72] ; (8001858 <HAL_InitTick+0x54>)
800180e: 681a ldr r2, [r3, #0]
8001810: 4b12 ldr r3, [pc, #72] ; (800185c <HAL_InitTick+0x58>)
8001812: 781b ldrb r3, [r3, #0]
8001814: 4619 mov r1, r3
8001816: f44f 737a mov.w r3, #1000 ; 0x3e8
800181a: fbb3 f3f1 udiv r3, r3, r1
800181e: fbb2 f3f3 udiv r3, r2, r3
8001822: 4618 mov r0, r3
8001824: f000 f95f bl 8001ae6 <HAL_SYSTICK_Config>
8001828: 4603 mov r3, r0
800182a: 2b00 cmp r3, #0
800182c: d001 beq.n 8001832 <HAL_InitTick+0x2e>
{
return HAL_ERROR;
800182e: 2301 movs r3, #1
8001830: e00e b.n 8001850 <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8001832: 687b ldr r3, [r7, #4]
8001834: 2b0f cmp r3, #15
8001836: d80a bhi.n 800184e <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8001838: 2200 movs r2, #0
800183a: 6879 ldr r1, [r7, #4]
800183c: f04f 30ff mov.w r0, #4294967295
8001840: f000 f927 bl 8001a92 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8001844: 4a06 ldr r2, [pc, #24] ; (8001860 <HAL_InitTick+0x5c>)
8001846: 687b ldr r3, [r7, #4]
8001848: 6013 str r3, [r2, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
800184a: 2300 movs r3, #0
800184c: e000 b.n 8001850 <HAL_InitTick+0x4c>
return HAL_ERROR;
800184e: 2301 movs r3, #1
}
8001850: 4618 mov r0, r3
8001852: 3708 adds r7, #8
8001854: 46bd mov sp, r7
8001856: bd80 pop {r7, pc}
8001858: 20000000 .word 0x20000000
800185c: 20000008 .word 0x20000008
8001860: 20000004 .word 0x20000004
08001864 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8001864: b480 push {r7}
8001866: af00 add r7, sp, #0
uwTick += uwTickFreq;
8001868: 4b05 ldr r3, [pc, #20] ; (8001880 <HAL_IncTick+0x1c>)
800186a: 781b ldrb r3, [r3, #0]
800186c: 461a mov r2, r3
800186e: 4b05 ldr r3, [pc, #20] ; (8001884 <HAL_IncTick+0x20>)
8001870: 681b ldr r3, [r3, #0]
8001872: 4413 add r3, r2
8001874: 4a03 ldr r2, [pc, #12] ; (8001884 <HAL_IncTick+0x20>)
8001876: 6013 str r3, [r2, #0]
}
8001878: bf00 nop
800187a: 46bd mov sp, r7
800187c: bc80 pop {r7}
800187e: 4770 bx lr
8001880: 20000008 .word 0x20000008
8001884: 2000088c .word 0x2000088c
08001888 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8001888: b480 push {r7}
800188a: af00 add r7, sp, #0
return uwTick;
800188c: 4b02 ldr r3, [pc, #8] ; (8001898 <HAL_GetTick+0x10>)
800188e: 681b ldr r3, [r3, #0]
}
8001890: 4618 mov r0, r3
8001892: 46bd mov sp, r7
8001894: bc80 pop {r7}
8001896: 4770 bx lr
8001898: 2000088c .word 0x2000088c
0800189c <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
800189c: b580 push {r7, lr}
800189e: b084 sub sp, #16
80018a0: af00 add r7, sp, #0
80018a2: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
80018a4: f7ff fff0 bl 8001888 <HAL_GetTick>
80018a8: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
80018aa: 687b ldr r3, [r7, #4]
80018ac: 60fb str r3, [r7, #12]
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
80018ae: 68fb ldr r3, [r7, #12]
80018b0: f1b3 3fff cmp.w r3, #4294967295
80018b4: d005 beq.n 80018c2 <HAL_Delay+0x26>
{
wait += (uint32_t)(uwTickFreq);
80018b6: 4b0a ldr r3, [pc, #40] ; (80018e0 <HAL_Delay+0x44>)
80018b8: 781b ldrb r3, [r3, #0]
80018ba: 461a mov r2, r3
80018bc: 68fb ldr r3, [r7, #12]
80018be: 4413 add r3, r2
80018c0: 60fb str r3, [r7, #12]
}
while ((HAL_GetTick() - tickstart) < wait)
80018c2: bf00 nop
80018c4: f7ff ffe0 bl 8001888 <HAL_GetTick>
80018c8: 4602 mov r2, r0
80018ca: 68bb ldr r3, [r7, #8]
80018cc: 1ad3 subs r3, r2, r3
80018ce: 68fa ldr r2, [r7, #12]
80018d0: 429a cmp r2, r3
80018d2: d8f7 bhi.n 80018c4 <HAL_Delay+0x28>
{
}
}
80018d4: bf00 nop
80018d6: bf00 nop
80018d8: 3710 adds r7, #16
80018da: 46bd mov sp, r7
80018dc: bd80 pop {r7, pc}
80018de: bf00 nop
80018e0: 20000008 .word 0x20000008
080018e4 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
80018e4: b480 push {r7}
80018e6: b085 sub sp, #20
80018e8: af00 add r7, sp, #0
80018ea: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80018ec: 687b ldr r3, [r7, #4]
80018ee: f003 0307 and.w r3, r3, #7
80018f2: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
80018f4: 4b0c ldr r3, [pc, #48] ; (8001928 <__NVIC_SetPriorityGrouping+0x44>)
80018f6: 68db ldr r3, [r3, #12]
80018f8: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
80018fa: 68ba ldr r2, [r7, #8]
80018fc: f64f 03ff movw r3, #63743 ; 0xf8ff
8001900: 4013 ands r3, r2
8001902: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8001904: 68fb ldr r3, [r7, #12]
8001906: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8001908: 68bb ldr r3, [r7, #8]
800190a: 4313 orrs r3, r2
reg_value = (reg_value |
800190c: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
8001910: f443 3300 orr.w r3, r3, #131072 ; 0x20000
8001914: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8001916: 4a04 ldr r2, [pc, #16] ; (8001928 <__NVIC_SetPriorityGrouping+0x44>)
8001918: 68bb ldr r3, [r7, #8]
800191a: 60d3 str r3, [r2, #12]
}
800191c: bf00 nop
800191e: 3714 adds r7, #20
8001920: 46bd mov sp, r7
8001922: bc80 pop {r7}
8001924: 4770 bx lr
8001926: bf00 nop
8001928: e000ed00 .word 0xe000ed00
0800192c <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
800192c: b480 push {r7}
800192e: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8001930: 4b04 ldr r3, [pc, #16] ; (8001944 <__NVIC_GetPriorityGrouping+0x18>)
8001932: 68db ldr r3, [r3, #12]
8001934: 0a1b lsrs r3, r3, #8
8001936: f003 0307 and.w r3, r3, #7
}
800193a: 4618 mov r0, r3
800193c: 46bd mov sp, r7
800193e: bc80 pop {r7}
8001940: 4770 bx lr
8001942: bf00 nop
8001944: e000ed00 .word 0xe000ed00
08001948 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
8001948: b480 push {r7}
800194a: b083 sub sp, #12
800194c: af00 add r7, sp, #0
800194e: 4603 mov r3, r0
8001950: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8001952: f997 3007 ldrsb.w r3, [r7, #7]
8001956: 2b00 cmp r3, #0
8001958: db0b blt.n 8001972 <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
800195a: 79fb ldrb r3, [r7, #7]
800195c: f003 021f and.w r2, r3, #31
8001960: 4906 ldr r1, [pc, #24] ; (800197c <__NVIC_EnableIRQ+0x34>)
8001962: f997 3007 ldrsb.w r3, [r7, #7]
8001966: 095b lsrs r3, r3, #5
8001968: 2001 movs r0, #1
800196a: fa00 f202 lsl.w r2, r0, r2
800196e: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
8001972: bf00 nop
8001974: 370c adds r7, #12
8001976: 46bd mov sp, r7
8001978: bc80 pop {r7}
800197a: 4770 bx lr
800197c: e000e100 .word 0xe000e100
08001980 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8001980: b480 push {r7}
8001982: b083 sub sp, #12
8001984: af00 add r7, sp, #0
8001986: 4603 mov r3, r0
8001988: 6039 str r1, [r7, #0]
800198a: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
800198c: f997 3007 ldrsb.w r3, [r7, #7]
8001990: 2b00 cmp r3, #0
8001992: db0a blt.n 80019aa <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8001994: 683b ldr r3, [r7, #0]
8001996: b2da uxtb r2, r3
8001998: 490c ldr r1, [pc, #48] ; (80019cc <__NVIC_SetPriority+0x4c>)
800199a: f997 3007 ldrsb.w r3, [r7, #7]
800199e: 0112 lsls r2, r2, #4
80019a0: b2d2 uxtb r2, r2
80019a2: 440b add r3, r1
80019a4: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
80019a8: e00a b.n 80019c0 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
80019aa: 683b ldr r3, [r7, #0]
80019ac: b2da uxtb r2, r3
80019ae: 4908 ldr r1, [pc, #32] ; (80019d0 <__NVIC_SetPriority+0x50>)
80019b0: 79fb ldrb r3, [r7, #7]
80019b2: f003 030f and.w r3, r3, #15
80019b6: 3b04 subs r3, #4
80019b8: 0112 lsls r2, r2, #4
80019ba: b2d2 uxtb r2, r2
80019bc: 440b add r3, r1
80019be: 761a strb r2, [r3, #24]
}
80019c0: bf00 nop
80019c2: 370c adds r7, #12
80019c4: 46bd mov sp, r7
80019c6: bc80 pop {r7}
80019c8: 4770 bx lr
80019ca: bf00 nop
80019cc: e000e100 .word 0xe000e100
80019d0: e000ed00 .word 0xe000ed00
080019d4 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
80019d4: b480 push {r7}
80019d6: b089 sub sp, #36 ; 0x24
80019d8: af00 add r7, sp, #0
80019da: 60f8 str r0, [r7, #12]
80019dc: 60b9 str r1, [r7, #8]
80019de: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80019e0: 68fb ldr r3, [r7, #12]
80019e2: f003 0307 and.w r3, r3, #7
80019e6: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
80019e8: 69fb ldr r3, [r7, #28]
80019ea: f1c3 0307 rsb r3, r3, #7
80019ee: 2b04 cmp r3, #4
80019f0: bf28 it cs
80019f2: 2304 movcs r3, #4
80019f4: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
80019f6: 69fb ldr r3, [r7, #28]
80019f8: 3304 adds r3, #4
80019fa: 2b06 cmp r3, #6
80019fc: d902 bls.n 8001a04 <NVIC_EncodePriority+0x30>
80019fe: 69fb ldr r3, [r7, #28]
8001a00: 3b03 subs r3, #3
8001a02: e000 b.n 8001a06 <NVIC_EncodePriority+0x32>
8001a04: 2300 movs r3, #0
8001a06: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8001a08: f04f 32ff mov.w r2, #4294967295
8001a0c: 69bb ldr r3, [r7, #24]
8001a0e: fa02 f303 lsl.w r3, r2, r3
8001a12: 43da mvns r2, r3
8001a14: 68bb ldr r3, [r7, #8]
8001a16: 401a ands r2, r3
8001a18: 697b ldr r3, [r7, #20]
8001a1a: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8001a1c: f04f 31ff mov.w r1, #4294967295
8001a20: 697b ldr r3, [r7, #20]
8001a22: fa01 f303 lsl.w r3, r1, r3
8001a26: 43d9 mvns r1, r3
8001a28: 687b ldr r3, [r7, #4]
8001a2a: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8001a2c: 4313 orrs r3, r2
);
}
8001a2e: 4618 mov r0, r3
8001a30: 3724 adds r7, #36 ; 0x24
8001a32: 46bd mov sp, r7
8001a34: bc80 pop {r7}
8001a36: 4770 bx lr
08001a38 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8001a38: b580 push {r7, lr}
8001a3a: b082 sub sp, #8
8001a3c: af00 add r7, sp, #0
8001a3e: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8001a40: 687b ldr r3, [r7, #4]
8001a42: 3b01 subs r3, #1
8001a44: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
8001a48: d301 bcc.n 8001a4e <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
8001a4a: 2301 movs r3, #1
8001a4c: e00f b.n 8001a6e <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8001a4e: 4a0a ldr r2, [pc, #40] ; (8001a78 <SysTick_Config+0x40>)
8001a50: 687b ldr r3, [r7, #4]
8001a52: 3b01 subs r3, #1
8001a54: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8001a56: 210f movs r1, #15
8001a58: f04f 30ff mov.w r0, #4294967295
8001a5c: f7ff ff90 bl 8001980 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8001a60: 4b05 ldr r3, [pc, #20] ; (8001a78 <SysTick_Config+0x40>)
8001a62: 2200 movs r2, #0
8001a64: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8001a66: 4b04 ldr r3, [pc, #16] ; (8001a78 <SysTick_Config+0x40>)
8001a68: 2207 movs r2, #7
8001a6a: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8001a6c: 2300 movs r3, #0
}
8001a6e: 4618 mov r0, r3
8001a70: 3708 adds r7, #8
8001a72: 46bd mov sp, r7
8001a74: bd80 pop {r7, pc}
8001a76: bf00 nop
8001a78: e000e010 .word 0xe000e010
08001a7c <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8001a7c: b580 push {r7, lr}
8001a7e: b082 sub sp, #8
8001a80: af00 add r7, sp, #0
8001a82: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8001a84: 6878 ldr r0, [r7, #4]
8001a86: f7ff ff2d bl 80018e4 <__NVIC_SetPriorityGrouping>
}
8001a8a: bf00 nop
8001a8c: 3708 adds r7, #8
8001a8e: 46bd mov sp, r7
8001a90: bd80 pop {r7, pc}
08001a92 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8001a92: b580 push {r7, lr}
8001a94: b086 sub sp, #24
8001a96: af00 add r7, sp, #0
8001a98: 4603 mov r3, r0
8001a9a: 60b9 str r1, [r7, #8]
8001a9c: 607a str r2, [r7, #4]
8001a9e: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
8001aa0: 2300 movs r3, #0
8001aa2: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8001aa4: f7ff ff42 bl 800192c <__NVIC_GetPriorityGrouping>
8001aa8: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8001aaa: 687a ldr r2, [r7, #4]
8001aac: 68b9 ldr r1, [r7, #8]
8001aae: 6978 ldr r0, [r7, #20]
8001ab0: f7ff ff90 bl 80019d4 <NVIC_EncodePriority>
8001ab4: 4602 mov r2, r0
8001ab6: f997 300f ldrsb.w r3, [r7, #15]
8001aba: 4611 mov r1, r2
8001abc: 4618 mov r0, r3
8001abe: f7ff ff5f bl 8001980 <__NVIC_SetPriority>
}
8001ac2: bf00 nop
8001ac4: 3718 adds r7, #24
8001ac6: 46bd mov sp, r7
8001ac8: bd80 pop {r7, pc}
08001aca <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
8001aca: b580 push {r7, lr}
8001acc: b082 sub sp, #8
8001ace: af00 add r7, sp, #0
8001ad0: 4603 mov r3, r0
8001ad2: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8001ad4: f997 3007 ldrsb.w r3, [r7, #7]
8001ad8: 4618 mov r0, r3
8001ada: f7ff ff35 bl 8001948 <__NVIC_EnableIRQ>
}
8001ade: bf00 nop
8001ae0: 3708 adds r7, #8
8001ae2: 46bd mov sp, r7
8001ae4: bd80 pop {r7, pc}
08001ae6 <HAL_SYSTICK_Config>:
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
8001ae6: b580 push {r7, lr}
8001ae8: b082 sub sp, #8
8001aea: af00 add r7, sp, #0
8001aec: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8001aee: 6878 ldr r0, [r7, #4]
8001af0: f7ff ffa2 bl 8001a38 <SysTick_Config>
8001af4: 4603 mov r3, r0
}
8001af6: 4618 mov r0, r3
8001af8: 3708 adds r7, #8
8001afa: 46bd mov sp, r7
8001afc: bd80 pop {r7, pc}
...
08001b00 <HAL_DMA_Init>:
* @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
8001b00: b480 push {r7}
8001b02: b085 sub sp, #20
8001b04: af00 add r7, sp, #0
8001b06: 6078 str r0, [r7, #4]
uint32_t tmp = 0U;
8001b08: 2300 movs r3, #0
8001b0a: 60fb str r3, [r7, #12]
/* Check the DMA handle allocation */
if(hdma == NULL)
8001b0c: 687b ldr r3, [r7, #4]
8001b0e: 2b00 cmp r3, #0
8001b10: d101 bne.n 8001b16 <HAL_DMA_Init+0x16>
{
return HAL_ERROR;
8001b12: 2301 movs r3, #1
8001b14: e043 b.n 8001b9e <HAL_DMA_Init+0x9e>
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
hdma->DmaBaseAddress = DMA2;
}
#else
/* DMA1 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
8001b16: 687b ldr r3, [r7, #4]
8001b18: 681b ldr r3, [r3, #0]
8001b1a: 461a mov r2, r3
8001b1c: 4b22 ldr r3, [pc, #136] ; (8001ba8 <HAL_DMA_Init+0xa8>)
8001b1e: 4413 add r3, r2
8001b20: 4a22 ldr r2, [pc, #136] ; (8001bac <HAL_DMA_Init+0xac>)
8001b22: fba2 2303 umull r2, r3, r2, r3
8001b26: 091b lsrs r3, r3, #4
8001b28: 009a lsls r2, r3, #2
8001b2a: 687b ldr r3, [r7, #4]
8001b2c: 641a str r2, [r3, #64] ; 0x40
hdma->DmaBaseAddress = DMA1;
8001b2e: 687b ldr r3, [r7, #4]
8001b30: 4a1f ldr r2, [pc, #124] ; (8001bb0 <HAL_DMA_Init+0xb0>)
8001b32: 63da str r2, [r3, #60] ; 0x3c
#endif /* DMA2 */
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
8001b34: 687b ldr r3, [r7, #4]
8001b36: 2202 movs r2, #2
8001b38: f883 2021 strb.w r2, [r3, #33] ; 0x21
/* Get the CR register value */
tmp = hdma->Instance->CCR;
8001b3c: 687b ldr r3, [r7, #4]
8001b3e: 681b ldr r3, [r3, #0]
8001b40: 681b ldr r3, [r3, #0]
8001b42: 60fb str r3, [r7, #12]
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
8001b44: 68fb ldr r3, [r7, #12]
8001b46: f423 537f bic.w r3, r3, #16320 ; 0x3fc0
8001b4a: f023 0330 bic.w r3, r3, #48 ; 0x30
8001b4e: 60fb str r3, [r7, #12]
DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
DMA_CCR_DIR));
/* Prepare the DMA Channel configuration */
tmp |= hdma->Init.Direction |
8001b50: 687b ldr r3, [r7, #4]
8001b52: 685a ldr r2, [r3, #4]
hdma->Init.PeriphInc | hdma->Init.MemInc |
8001b54: 687b ldr r3, [r7, #4]
8001b56: 689b ldr r3, [r3, #8]
tmp |= hdma->Init.Direction |
8001b58: 431a orrs r2, r3
hdma->Init.PeriphInc | hdma->Init.MemInc |
8001b5a: 687b ldr r3, [r7, #4]
8001b5c: 68db ldr r3, [r3, #12]
8001b5e: 431a orrs r2, r3
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
8001b60: 687b ldr r3, [r7, #4]
8001b62: 691b ldr r3, [r3, #16]
hdma->Init.PeriphInc | hdma->Init.MemInc |
8001b64: 431a orrs r2, r3
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
8001b66: 687b ldr r3, [r7, #4]
8001b68: 695b ldr r3, [r3, #20]
8001b6a: 431a orrs r2, r3
hdma->Init.Mode | hdma->Init.Priority;
8001b6c: 687b ldr r3, [r7, #4]
8001b6e: 699b ldr r3, [r3, #24]
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
8001b70: 431a orrs r2, r3
hdma->Init.Mode | hdma->Init.Priority;
8001b72: 687b ldr r3, [r7, #4]
8001b74: 69db ldr r3, [r3, #28]
8001b76: 4313 orrs r3, r2
tmp |= hdma->Init.Direction |
8001b78: 68fa ldr r2, [r7, #12]
8001b7a: 4313 orrs r3, r2
8001b7c: 60fb str r3, [r7, #12]
/* Write to DMA Channel CR register */
hdma->Instance->CCR = tmp;
8001b7e: 687b ldr r3, [r7, #4]
8001b80: 681b ldr r3, [r3, #0]
8001b82: 68fa ldr r2, [r7, #12]
8001b84: 601a str r2, [r3, #0]
/* Initialise the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
8001b86: 687b ldr r3, [r7, #4]
8001b88: 2200 movs r2, #0
8001b8a: 639a str r2, [r3, #56] ; 0x38
/* Initialize the DMA state*/
hdma->State = HAL_DMA_STATE_READY;
8001b8c: 687b ldr r3, [r7, #4]
8001b8e: 2201 movs r2, #1
8001b90: f883 2021 strb.w r2, [r3, #33] ; 0x21
/* Allocate lock resource and initialize it */
hdma->Lock = HAL_UNLOCKED;
8001b94: 687b ldr r3, [r7, #4]
8001b96: 2200 movs r2, #0
8001b98: f883 2020 strb.w r2, [r3, #32]
return HAL_OK;
8001b9c: 2300 movs r3, #0
}
8001b9e: 4618 mov r0, r3
8001ba0: 3714 adds r7, #20
8001ba2: 46bd mov sp, r7
8001ba4: bc80 pop {r7}
8001ba6: 4770 bx lr
8001ba8: bffdfff8 .word 0xbffdfff8
8001bac: cccccccd .word 0xcccccccd
8001bb0: 40020000 .word 0x40020000
08001bb4 <HAL_DMA_Start_IT>:
* @param DstAddress: The destination memory Buffer address
* @param DataLength: The length of data to be transferred from source to destination
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
8001bb4: b580 push {r7, lr}
8001bb6: b086 sub sp, #24
8001bb8: af00 add r7, sp, #0
8001bba: 60f8 str r0, [r7, #12]
8001bbc: 60b9 str r1, [r7, #8]
8001bbe: 607a str r2, [r7, #4]
8001bc0: 603b str r3, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
8001bc2: 2300 movs r3, #0
8001bc4: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
/* Process locked */
__HAL_LOCK(hdma);
8001bc6: 68fb ldr r3, [r7, #12]
8001bc8: f893 3020 ldrb.w r3, [r3, #32]
8001bcc: 2b01 cmp r3, #1
8001bce: d101 bne.n 8001bd4 <HAL_DMA_Start_IT+0x20>
8001bd0: 2302 movs r3, #2
8001bd2: e04a b.n 8001c6a <HAL_DMA_Start_IT+0xb6>
8001bd4: 68fb ldr r3, [r7, #12]
8001bd6: 2201 movs r2, #1
8001bd8: f883 2020 strb.w r2, [r3, #32]
if(HAL_DMA_STATE_READY == hdma->State)
8001bdc: 68fb ldr r3, [r7, #12]
8001bde: f893 3021 ldrb.w r3, [r3, #33] ; 0x21
8001be2: 2b01 cmp r3, #1
8001be4: d13a bne.n 8001c5c <HAL_DMA_Start_IT+0xa8>
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
8001be6: 68fb ldr r3, [r7, #12]
8001be8: 2202 movs r2, #2
8001bea: f883 2021 strb.w r2, [r3, #33] ; 0x21
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
8001bee: 68fb ldr r3, [r7, #12]
8001bf0: 2200 movs r2, #0
8001bf2: 639a str r2, [r3, #56] ; 0x38
/* Disable the peripheral */
__HAL_DMA_DISABLE(hdma);
8001bf4: 68fb ldr r3, [r7, #12]
8001bf6: 681b ldr r3, [r3, #0]
8001bf8: 681a ldr r2, [r3, #0]
8001bfa: 68fb ldr r3, [r7, #12]
8001bfc: 681b ldr r3, [r3, #0]
8001bfe: f022 0201 bic.w r2, r2, #1
8001c02: 601a str r2, [r3, #0]
/* Configure the source, destination address and the data length & clear flags*/
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
8001c04: 683b ldr r3, [r7, #0]
8001c06: 687a ldr r2, [r7, #4]
8001c08: 68b9 ldr r1, [r7, #8]
8001c0a: 68f8 ldr r0, [r7, #12]
8001c0c: f000 f9e8 bl 8001fe0 <DMA_SetConfig>
/* Enable the transfer complete interrupt */
/* Enable the transfer Error interrupt */
if(NULL != hdma->XferHalfCpltCallback)
8001c10: 68fb ldr r3, [r7, #12]
8001c12: 6adb ldr r3, [r3, #44] ; 0x2c
8001c14: 2b00 cmp r3, #0
8001c16: d008 beq.n 8001c2a <HAL_DMA_Start_IT+0x76>
{
/* Enable the Half transfer complete interrupt as well */
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
8001c18: 68fb ldr r3, [r7, #12]
8001c1a: 681b ldr r3, [r3, #0]
8001c1c: 681a ldr r2, [r3, #0]
8001c1e: 68fb ldr r3, [r7, #12]
8001c20: 681b ldr r3, [r3, #0]
8001c22: f042 020e orr.w r2, r2, #14
8001c26: 601a str r2, [r3, #0]
8001c28: e00f b.n 8001c4a <HAL_DMA_Start_IT+0x96>
}
else
{
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
8001c2a: 68fb ldr r3, [r7, #12]
8001c2c: 681b ldr r3, [r3, #0]
8001c2e: 681a ldr r2, [r3, #0]
8001c30: 68fb ldr r3, [r7, #12]
8001c32: 681b ldr r3, [r3, #0]
8001c34: f022 0204 bic.w r2, r2, #4
8001c38: 601a str r2, [r3, #0]
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
8001c3a: 68fb ldr r3, [r7, #12]
8001c3c: 681b ldr r3, [r3, #0]
8001c3e: 681a ldr r2, [r3, #0]
8001c40: 68fb ldr r3, [r7, #12]
8001c42: 681b ldr r3, [r3, #0]
8001c44: f042 020a orr.w r2, r2, #10
8001c48: 601a str r2, [r3, #0]
}
/* Enable the Peripheral */
__HAL_DMA_ENABLE(hdma);
8001c4a: 68fb ldr r3, [r7, #12]
8001c4c: 681b ldr r3, [r3, #0]
8001c4e: 681a ldr r2, [r3, #0]
8001c50: 68fb ldr r3, [r7, #12]
8001c52: 681b ldr r3, [r3, #0]
8001c54: f042 0201 orr.w r2, r2, #1
8001c58: 601a str r2, [r3, #0]
8001c5a: e005 b.n 8001c68 <HAL_DMA_Start_IT+0xb4>
}
else
{
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8001c5c: 68fb ldr r3, [r7, #12]
8001c5e: 2200 movs r2, #0
8001c60: f883 2020 strb.w r2, [r3, #32]
/* Remain BUSY */
status = HAL_BUSY;
8001c64: 2302 movs r3, #2
8001c66: 75fb strb r3, [r7, #23]
}
return status;
8001c68: 7dfb ldrb r3, [r7, #23]
}
8001c6a: 4618 mov r0, r3
8001c6c: 3718 adds r7, #24
8001c6e: 46bd mov sp, r7
8001c70: bd80 pop {r7, pc}
08001c72 <HAL_DMA_Abort>:
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
8001c72: b480 push {r7}
8001c74: b085 sub sp, #20
8001c76: af00 add r7, sp, #0
8001c78: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8001c7a: 2300 movs r3, #0
8001c7c: 73fb strb r3, [r7, #15]
if(hdma->State != HAL_DMA_STATE_BUSY)
8001c7e: 687b ldr r3, [r7, #4]
8001c80: f893 3021 ldrb.w r3, [r3, #33] ; 0x21
8001c84: 2b02 cmp r3, #2
8001c86: d008 beq.n 8001c9a <HAL_DMA_Abort+0x28>
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
8001c88: 687b ldr r3, [r7, #4]
8001c8a: 2204 movs r2, #4
8001c8c: 639a str r2, [r3, #56] ; 0x38
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8001c8e: 687b ldr r3, [r7, #4]
8001c90: 2200 movs r2, #0
8001c92: f883 2020 strb.w r2, [r3, #32]
return HAL_ERROR;
8001c96: 2301 movs r3, #1
8001c98: e020 b.n 8001cdc <HAL_DMA_Abort+0x6a>
}
else
{
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
8001c9a: 687b ldr r3, [r7, #4]
8001c9c: 681b ldr r3, [r3, #0]
8001c9e: 681a ldr r2, [r3, #0]
8001ca0: 687b ldr r3, [r7, #4]
8001ca2: 681b ldr r3, [r3, #0]
8001ca4: f022 020e bic.w r2, r2, #14
8001ca8: 601a str r2, [r3, #0]
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
8001caa: 687b ldr r3, [r7, #4]
8001cac: 681b ldr r3, [r3, #0]
8001cae: 681a ldr r2, [r3, #0]
8001cb0: 687b ldr r3, [r7, #4]
8001cb2: 681b ldr r3, [r3, #0]
8001cb4: f022 0201 bic.w r2, r2, #1
8001cb8: 601a str r2, [r3, #0]
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
8001cba: 687b ldr r3, [r7, #4]
8001cbc: 6c1a ldr r2, [r3, #64] ; 0x40
8001cbe: 687b ldr r3, [r7, #4]
8001cc0: 6bdb ldr r3, [r3, #60] ; 0x3c
8001cc2: 2101 movs r1, #1
8001cc4: fa01 f202 lsl.w r2, r1, r2
8001cc8: 605a str r2, [r3, #4]
}
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8001cca: 687b ldr r3, [r7, #4]
8001ccc: 2201 movs r2, #1
8001cce: f883 2021 strb.w r2, [r3, #33] ; 0x21
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8001cd2: 687b ldr r3, [r7, #4]
8001cd4: 2200 movs r2, #0
8001cd6: f883 2020 strb.w r2, [r3, #32]
return status;
8001cda: 7bfb ldrb r3, [r7, #15]
}
8001cdc: 4618 mov r0, r3
8001cde: 3714 adds r7, #20
8001ce0: 46bd mov sp, r7
8001ce2: bc80 pop {r7}
8001ce4: 4770 bx lr
...
08001ce8 <HAL_DMA_Abort_IT>:
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
8001ce8: b580 push {r7, lr}
8001cea: b084 sub sp, #16
8001cec: af00 add r7, sp, #0
8001cee: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8001cf0: 2300 movs r3, #0
8001cf2: 73fb strb r3, [r7, #15]
if(HAL_DMA_STATE_BUSY != hdma->State)
8001cf4: 687b ldr r3, [r7, #4]
8001cf6: f893 3021 ldrb.w r3, [r3, #33] ; 0x21
8001cfa: 2b02 cmp r3, #2
8001cfc: d005 beq.n 8001d0a <HAL_DMA_Abort_IT+0x22>
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
8001cfe: 687b ldr r3, [r7, #4]
8001d00: 2204 movs r2, #4
8001d02: 639a str r2, [r3, #56] ; 0x38
status = HAL_ERROR;
8001d04: 2301 movs r3, #1
8001d06: 73fb strb r3, [r7, #15]
8001d08: e051 b.n 8001dae <HAL_DMA_Abort_IT+0xc6>
}
else
{
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
8001d0a: 687b ldr r3, [r7, #4]
8001d0c: 681b ldr r3, [r3, #0]
8001d0e: 681a ldr r2, [r3, #0]
8001d10: 687b ldr r3, [r7, #4]
8001d12: 681b ldr r3, [r3, #0]
8001d14: f022 020e bic.w r2, r2, #14
8001d18: 601a str r2, [r3, #0]
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
8001d1a: 687b ldr r3, [r7, #4]
8001d1c: 681b ldr r3, [r3, #0]
8001d1e: 681a ldr r2, [r3, #0]
8001d20: 687b ldr r3, [r7, #4]
8001d22: 681b ldr r3, [r3, #0]
8001d24: f022 0201 bic.w r2, r2, #1
8001d28: 601a str r2, [r3, #0]
/* Clear all flags */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
8001d2a: 687b ldr r3, [r7, #4]
8001d2c: 681b ldr r3, [r3, #0]
8001d2e: 4a22 ldr r2, [pc, #136] ; (8001db8 <HAL_DMA_Abort_IT+0xd0>)
8001d30: 4293 cmp r3, r2
8001d32: d029 beq.n 8001d88 <HAL_DMA_Abort_IT+0xa0>
8001d34: 687b ldr r3, [r7, #4]
8001d36: 681b ldr r3, [r3, #0]
8001d38: 4a20 ldr r2, [pc, #128] ; (8001dbc <HAL_DMA_Abort_IT+0xd4>)
8001d3a: 4293 cmp r3, r2
8001d3c: d022 beq.n 8001d84 <HAL_DMA_Abort_IT+0x9c>
8001d3e: 687b ldr r3, [r7, #4]
8001d40: 681b ldr r3, [r3, #0]
8001d42: 4a1f ldr r2, [pc, #124] ; (8001dc0 <HAL_DMA_Abort_IT+0xd8>)
8001d44: 4293 cmp r3, r2
8001d46: d01a beq.n 8001d7e <HAL_DMA_Abort_IT+0x96>
8001d48: 687b ldr r3, [r7, #4]
8001d4a: 681b ldr r3, [r3, #0]
8001d4c: 4a1d ldr r2, [pc, #116] ; (8001dc4 <HAL_DMA_Abort_IT+0xdc>)
8001d4e: 4293 cmp r3, r2
8001d50: d012 beq.n 8001d78 <HAL_DMA_Abort_IT+0x90>
8001d52: 687b ldr r3, [r7, #4]
8001d54: 681b ldr r3, [r3, #0]
8001d56: 4a1c ldr r2, [pc, #112] ; (8001dc8 <HAL_DMA_Abort_IT+0xe0>)
8001d58: 4293 cmp r3, r2
8001d5a: d00a beq.n 8001d72 <HAL_DMA_Abort_IT+0x8a>
8001d5c: 687b ldr r3, [r7, #4]
8001d5e: 681b ldr r3, [r3, #0]
8001d60: 4a1a ldr r2, [pc, #104] ; (8001dcc <HAL_DMA_Abort_IT+0xe4>)
8001d62: 4293 cmp r3, r2
8001d64: d102 bne.n 8001d6c <HAL_DMA_Abort_IT+0x84>
8001d66: f44f 1380 mov.w r3, #1048576 ; 0x100000
8001d6a: e00e b.n 8001d8a <HAL_DMA_Abort_IT+0xa2>
8001d6c: f04f 7380 mov.w r3, #16777216 ; 0x1000000
8001d70: e00b b.n 8001d8a <HAL_DMA_Abort_IT+0xa2>
8001d72: f44f 3380 mov.w r3, #65536 ; 0x10000
8001d76: e008 b.n 8001d8a <HAL_DMA_Abort_IT+0xa2>
8001d78: f44f 5380 mov.w r3, #4096 ; 0x1000
8001d7c: e005 b.n 8001d8a <HAL_DMA_Abort_IT+0xa2>
8001d7e: f44f 7380 mov.w r3, #256 ; 0x100
8001d82: e002 b.n 8001d8a <HAL_DMA_Abort_IT+0xa2>
8001d84: 2310 movs r3, #16
8001d86: e000 b.n 8001d8a <HAL_DMA_Abort_IT+0xa2>
8001d88: 2301 movs r3, #1
8001d8a: 4a11 ldr r2, [pc, #68] ; (8001dd0 <HAL_DMA_Abort_IT+0xe8>)
8001d8c: 6053 str r3, [r2, #4]
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8001d8e: 687b ldr r3, [r7, #4]
8001d90: 2201 movs r2, #1
8001d92: f883 2021 strb.w r2, [r3, #33] ; 0x21
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8001d96: 687b ldr r3, [r7, #4]
8001d98: 2200 movs r2, #0
8001d9a: f883 2020 strb.w r2, [r3, #32]
/* Call User Abort callback */
if(hdma->XferAbortCallback != NULL)
8001d9e: 687b ldr r3, [r7, #4]
8001da0: 6b5b ldr r3, [r3, #52] ; 0x34
8001da2: 2b00 cmp r3, #0
8001da4: d003 beq.n 8001dae <HAL_DMA_Abort_IT+0xc6>
{
hdma->XferAbortCallback(hdma);
8001da6: 687b ldr r3, [r7, #4]
8001da8: 6b5b ldr r3, [r3, #52] ; 0x34
8001daa: 6878 ldr r0, [r7, #4]
8001dac: 4798 blx r3
}
}
return status;
8001dae: 7bfb ldrb r3, [r7, #15]
}
8001db0: 4618 mov r0, r3
8001db2: 3710 adds r7, #16
8001db4: 46bd mov sp, r7
8001db6: bd80 pop {r7, pc}
8001db8: 40020008 .word 0x40020008
8001dbc: 4002001c .word 0x4002001c
8001dc0: 40020030 .word 0x40020030
8001dc4: 40020044 .word 0x40020044
8001dc8: 40020058 .word 0x40020058
8001dcc: 4002006c .word 0x4002006c
8001dd0: 40020000 .word 0x40020000
08001dd4 <HAL_DMA_IRQHandler>:
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval None
*/
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{
8001dd4: b580 push {r7, lr}
8001dd6: b084 sub sp, #16
8001dd8: af00 add r7, sp, #0
8001dda: 6078 str r0, [r7, #4]
uint32_t flag_it = hdma->DmaBaseAddress->ISR;
8001ddc: 687b ldr r3, [r7, #4]
8001dde: 6bdb ldr r3, [r3, #60] ; 0x3c
8001de0: 681b ldr r3, [r3, #0]
8001de2: 60fb str r3, [r7, #12]
uint32_t source_it = hdma->Instance->CCR;
8001de4: 687b ldr r3, [r7, #4]
8001de6: 681b ldr r3, [r3, #0]
8001de8: 681b ldr r3, [r3, #0]
8001dea: 60bb str r3, [r7, #8]
/* Half Transfer Complete Interrupt management ******************************/
if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
8001dec: 687b ldr r3, [r7, #4]
8001dee: 6c1b ldr r3, [r3, #64] ; 0x40
8001df0: 2204 movs r2, #4
8001df2: 409a lsls r2, r3
8001df4: 68fb ldr r3, [r7, #12]
8001df6: 4013 ands r3, r2
8001df8: 2b00 cmp r3, #0
8001dfa: d04f beq.n 8001e9c <HAL_DMA_IRQHandler+0xc8>
8001dfc: 68bb ldr r3, [r7, #8]
8001dfe: f003 0304 and.w r3, r3, #4
8001e02: 2b00 cmp r3, #0
8001e04: d04a beq.n 8001e9c <HAL_DMA_IRQHandler+0xc8>
{
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
8001e06: 687b ldr r3, [r7, #4]
8001e08: 681b ldr r3, [r3, #0]
8001e0a: 681b ldr r3, [r3, #0]
8001e0c: f003 0320 and.w r3, r3, #32
8001e10: 2b00 cmp r3, #0
8001e12: d107 bne.n 8001e24 <HAL_DMA_IRQHandler+0x50>
{
/* Disable the half transfer interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
8001e14: 687b ldr r3, [r7, #4]
8001e16: 681b ldr r3, [r3, #0]
8001e18: 681a ldr r2, [r3, #0]
8001e1a: 687b ldr r3, [r7, #4]
8001e1c: 681b ldr r3, [r3, #0]
8001e1e: f022 0204 bic.w r2, r2, #4
8001e22: 601a str r2, [r3, #0]
}
/* Clear the half transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
8001e24: 687b ldr r3, [r7, #4]
8001e26: 681b ldr r3, [r3, #0]
8001e28: 4a66 ldr r2, [pc, #408] ; (8001fc4 <HAL_DMA_IRQHandler+0x1f0>)
8001e2a: 4293 cmp r3, r2
8001e2c: d029 beq.n 8001e82 <HAL_DMA_IRQHandler+0xae>
8001e2e: 687b ldr r3, [r7, #4]
8001e30: 681b ldr r3, [r3, #0]
8001e32: 4a65 ldr r2, [pc, #404] ; (8001fc8 <HAL_DMA_IRQHandler+0x1f4>)
8001e34: 4293 cmp r3, r2
8001e36: d022 beq.n 8001e7e <HAL_DMA_IRQHandler+0xaa>
8001e38: 687b ldr r3, [r7, #4]
8001e3a: 681b ldr r3, [r3, #0]
8001e3c: 4a63 ldr r2, [pc, #396] ; (8001fcc <HAL_DMA_IRQHandler+0x1f8>)
8001e3e: 4293 cmp r3, r2
8001e40: d01a beq.n 8001e78 <HAL_DMA_IRQHandler+0xa4>
8001e42: 687b ldr r3, [r7, #4]
8001e44: 681b ldr r3, [r3, #0]
8001e46: 4a62 ldr r2, [pc, #392] ; (8001fd0 <HAL_DMA_IRQHandler+0x1fc>)
8001e48: 4293 cmp r3, r2
8001e4a: d012 beq.n 8001e72 <HAL_DMA_IRQHandler+0x9e>
8001e4c: 687b ldr r3, [r7, #4]
8001e4e: 681b ldr r3, [r3, #0]
8001e50: 4a60 ldr r2, [pc, #384] ; (8001fd4 <HAL_DMA_IRQHandler+0x200>)
8001e52: 4293 cmp r3, r2
8001e54: d00a beq.n 8001e6c <HAL_DMA_IRQHandler+0x98>
8001e56: 687b ldr r3, [r7, #4]
8001e58: 681b ldr r3, [r3, #0]
8001e5a: 4a5f ldr r2, [pc, #380] ; (8001fd8 <HAL_DMA_IRQHandler+0x204>)
8001e5c: 4293 cmp r3, r2
8001e5e: d102 bne.n 8001e66 <HAL_DMA_IRQHandler+0x92>
8001e60: f44f 0380 mov.w r3, #4194304 ; 0x400000
8001e64: e00e b.n 8001e84 <HAL_DMA_IRQHandler+0xb0>
8001e66: f04f 6380 mov.w r3, #67108864 ; 0x4000000
8001e6a: e00b b.n 8001e84 <HAL_DMA_IRQHandler+0xb0>
8001e6c: f44f 2380 mov.w r3, #262144 ; 0x40000
8001e70: e008 b.n 8001e84 <HAL_DMA_IRQHandler+0xb0>
8001e72: f44f 4380 mov.w r3, #16384 ; 0x4000
8001e76: e005 b.n 8001e84 <HAL_DMA_IRQHandler+0xb0>
8001e78: f44f 6380 mov.w r3, #1024 ; 0x400
8001e7c: e002 b.n 8001e84 <HAL_DMA_IRQHandler+0xb0>
8001e7e: 2340 movs r3, #64 ; 0x40
8001e80: e000 b.n 8001e84 <HAL_DMA_IRQHandler+0xb0>
8001e82: 2304 movs r3, #4
8001e84: 4a55 ldr r2, [pc, #340] ; (8001fdc <HAL_DMA_IRQHandler+0x208>)
8001e86: 6053 str r3, [r2, #4]
/* DMA peripheral state is not updated in Half Transfer */
/* but in Transfer Complete case */
if(hdma->XferHalfCpltCallback != NULL)
8001e88: 687b ldr r3, [r7, #4]
8001e8a: 6adb ldr r3, [r3, #44] ; 0x2c
8001e8c: 2b00 cmp r3, #0
8001e8e: f000 8094 beq.w 8001fba <HAL_DMA_IRQHandler+0x1e6>
{
/* Half transfer callback */
hdma->XferHalfCpltCallback(hdma);
8001e92: 687b ldr r3, [r7, #4]
8001e94: 6adb ldr r3, [r3, #44] ; 0x2c
8001e96: 6878 ldr r0, [r7, #4]
8001e98: 4798 blx r3
if(hdma->XferHalfCpltCallback != NULL)
8001e9a: e08e b.n 8001fba <HAL_DMA_IRQHandler+0x1e6>
}
}
/* Transfer Complete Interrupt management ***********************************/
else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET))
8001e9c: 687b ldr r3, [r7, #4]
8001e9e: 6c1b ldr r3, [r3, #64] ; 0x40
8001ea0: 2202 movs r2, #2
8001ea2: 409a lsls r2, r3
8001ea4: 68fb ldr r3, [r7, #12]
8001ea6: 4013 ands r3, r2
8001ea8: 2b00 cmp r3, #0
8001eaa: d056 beq.n 8001f5a <HAL_DMA_IRQHandler+0x186>
8001eac: 68bb ldr r3, [r7, #8]
8001eae: f003 0302 and.w r3, r3, #2
8001eb2: 2b00 cmp r3, #0
8001eb4: d051 beq.n 8001f5a <HAL_DMA_IRQHandler+0x186>
{
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
8001eb6: 687b ldr r3, [r7, #4]
8001eb8: 681b ldr r3, [r3, #0]
8001eba: 681b ldr r3, [r3, #0]
8001ebc: f003 0320 and.w r3, r3, #32
8001ec0: 2b00 cmp r3, #0
8001ec2: d10b bne.n 8001edc <HAL_DMA_IRQHandler+0x108>
{
/* Disable the transfer complete and error interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
8001ec4: 687b ldr r3, [r7, #4]
8001ec6: 681b ldr r3, [r3, #0]
8001ec8: 681a ldr r2, [r3, #0]
8001eca: 687b ldr r3, [r7, #4]
8001ecc: 681b ldr r3, [r3, #0]
8001ece: f022 020a bic.w r2, r2, #10
8001ed2: 601a str r2, [r3, #0]
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8001ed4: 687b ldr r3, [r7, #4]
8001ed6: 2201 movs r2, #1
8001ed8: f883 2021 strb.w r2, [r3, #33] ; 0x21
}
/* Clear the transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
8001edc: 687b ldr r3, [r7, #4]
8001ede: 681b ldr r3, [r3, #0]
8001ee0: 4a38 ldr r2, [pc, #224] ; (8001fc4 <HAL_DMA_IRQHandler+0x1f0>)
8001ee2: 4293 cmp r3, r2
8001ee4: d029 beq.n 8001f3a <HAL_DMA_IRQHandler+0x166>
8001ee6: 687b ldr r3, [r7, #4]
8001ee8: 681b ldr r3, [r3, #0]
8001eea: 4a37 ldr r2, [pc, #220] ; (8001fc8 <HAL_DMA_IRQHandler+0x1f4>)
8001eec: 4293 cmp r3, r2
8001eee: d022 beq.n 8001f36 <HAL_DMA_IRQHandler+0x162>
8001ef0: 687b ldr r3, [r7, #4]
8001ef2: 681b ldr r3, [r3, #0]
8001ef4: 4a35 ldr r2, [pc, #212] ; (8001fcc <HAL_DMA_IRQHandler+0x1f8>)
8001ef6: 4293 cmp r3, r2
8001ef8: d01a beq.n 8001f30 <HAL_DMA_IRQHandler+0x15c>
8001efa: 687b ldr r3, [r7, #4]
8001efc: 681b ldr r3, [r3, #0]
8001efe: 4a34 ldr r2, [pc, #208] ; (8001fd0 <HAL_DMA_IRQHandler+0x1fc>)
8001f00: 4293 cmp r3, r2
8001f02: d012 beq.n 8001f2a <HAL_DMA_IRQHandler+0x156>
8001f04: 687b ldr r3, [r7, #4]
8001f06: 681b ldr r3, [r3, #0]
8001f08: 4a32 ldr r2, [pc, #200] ; (8001fd4 <HAL_DMA_IRQHandler+0x200>)
8001f0a: 4293 cmp r3, r2
8001f0c: d00a beq.n 8001f24 <HAL_DMA_IRQHandler+0x150>
8001f0e: 687b ldr r3, [r7, #4]
8001f10: 681b ldr r3, [r3, #0]
8001f12: 4a31 ldr r2, [pc, #196] ; (8001fd8 <HAL_DMA_IRQHandler+0x204>)
8001f14: 4293 cmp r3, r2
8001f16: d102 bne.n 8001f1e <HAL_DMA_IRQHandler+0x14a>
8001f18: f44f 1300 mov.w r3, #2097152 ; 0x200000
8001f1c: e00e b.n 8001f3c <HAL_DMA_IRQHandler+0x168>
8001f1e: f04f 7300 mov.w r3, #33554432 ; 0x2000000
8001f22: e00b b.n 8001f3c <HAL_DMA_IRQHandler+0x168>
8001f24: f44f 3300 mov.w r3, #131072 ; 0x20000
8001f28: e008 b.n 8001f3c <HAL_DMA_IRQHandler+0x168>
8001f2a: f44f 5300 mov.w r3, #8192 ; 0x2000
8001f2e: e005 b.n 8001f3c <HAL_DMA_IRQHandler+0x168>
8001f30: f44f 7300 mov.w r3, #512 ; 0x200
8001f34: e002 b.n 8001f3c <HAL_DMA_IRQHandler+0x168>
8001f36: 2320 movs r3, #32
8001f38: e000 b.n 8001f3c <HAL_DMA_IRQHandler+0x168>
8001f3a: 2302 movs r3, #2
8001f3c: 4a27 ldr r2, [pc, #156] ; (8001fdc <HAL_DMA_IRQHandler+0x208>)
8001f3e: 6053 str r3, [r2, #4]
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8001f40: 687b ldr r3, [r7, #4]
8001f42: 2200 movs r2, #0
8001f44: f883 2020 strb.w r2, [r3, #32]
if(hdma->XferCpltCallback != NULL)
8001f48: 687b ldr r3, [r7, #4]
8001f4a: 6a9b ldr r3, [r3, #40] ; 0x28
8001f4c: 2b00 cmp r3, #0
8001f4e: d034 beq.n 8001fba <HAL_DMA_IRQHandler+0x1e6>
{
/* Transfer complete callback */
hdma->XferCpltCallback(hdma);
8001f50: 687b ldr r3, [r7, #4]
8001f52: 6a9b ldr r3, [r3, #40] ; 0x28
8001f54: 6878 ldr r0, [r7, #4]
8001f56: 4798 blx r3
if(hdma->XferCpltCallback != NULL)
8001f58: e02f b.n 8001fba <HAL_DMA_IRQHandler+0x1e6>
}
}
/* Transfer Error Interrupt management **************************************/
else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
8001f5a: 687b ldr r3, [r7, #4]
8001f5c: 6c1b ldr r3, [r3, #64] ; 0x40
8001f5e: 2208 movs r2, #8
8001f60: 409a lsls r2, r3
8001f62: 68fb ldr r3, [r7, #12]
8001f64: 4013 ands r3, r2
8001f66: 2b00 cmp r3, #0
8001f68: d028 beq.n 8001fbc <HAL_DMA_IRQHandler+0x1e8>
8001f6a: 68bb ldr r3, [r7, #8]
8001f6c: f003 0308 and.w r3, r3, #8
8001f70: 2b00 cmp r3, #0
8001f72: d023 beq.n 8001fbc <HAL_DMA_IRQHandler+0x1e8>
{
/* When a DMA transfer error occurs */
/* A hardware clear of its EN bits is performed */
/* Disable ALL DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
8001f74: 687b ldr r3, [r7, #4]
8001f76: 681b ldr r3, [r3, #0]
8001f78: 681a ldr r2, [r3, #0]
8001f7a: 687b ldr r3, [r7, #4]
8001f7c: 681b ldr r3, [r3, #0]
8001f7e: f022 020e bic.w r2, r2, #14
8001f82: 601a str r2, [r3, #0]
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
8001f84: 687b ldr r3, [r7, #4]
8001f86: 6c1a ldr r2, [r3, #64] ; 0x40
8001f88: 687b ldr r3, [r7, #4]
8001f8a: 6bdb ldr r3, [r3, #60] ; 0x3c
8001f8c: 2101 movs r1, #1
8001f8e: fa01 f202 lsl.w r2, r1, r2
8001f92: 605a str r2, [r3, #4]
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TE;
8001f94: 687b ldr r3, [r7, #4]
8001f96: 2201 movs r2, #1
8001f98: 639a str r2, [r3, #56] ; 0x38
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8001f9a: 687b ldr r3, [r7, #4]
8001f9c: 2201 movs r2, #1
8001f9e: f883 2021 strb.w r2, [r3, #33] ; 0x21
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8001fa2: 687b ldr r3, [r7, #4]
8001fa4: 2200 movs r2, #0
8001fa6: f883 2020 strb.w r2, [r3, #32]
if (hdma->XferErrorCallback != NULL)
8001faa: 687b ldr r3, [r7, #4]
8001fac: 6b1b ldr r3, [r3, #48] ; 0x30
8001fae: 2b00 cmp r3, #0
8001fb0: d004 beq.n 8001fbc <HAL_DMA_IRQHandler+0x1e8>
{
/* Transfer error callback */
hdma->XferErrorCallback(hdma);
8001fb2: 687b ldr r3, [r7, #4]
8001fb4: 6b1b ldr r3, [r3, #48] ; 0x30
8001fb6: 6878 ldr r0, [r7, #4]
8001fb8: 4798 blx r3
}
}
return;
8001fba: bf00 nop
8001fbc: bf00 nop
}
8001fbe: 3710 adds r7, #16
8001fc0: 46bd mov sp, r7
8001fc2: bd80 pop {r7, pc}
8001fc4: 40020008 .word 0x40020008
8001fc8: 4002001c .word 0x4002001c
8001fcc: 40020030 .word 0x40020030
8001fd0: 40020044 .word 0x40020044
8001fd4: 40020058 .word 0x40020058
8001fd8: 4002006c .word 0x4002006c
8001fdc: 40020000 .word 0x40020000
08001fe0 <DMA_SetConfig>:
* @param DstAddress: The destination memory Buffer address
* @param DataLength: The length of data to be transferred from source to destination
* @retval HAL status
*/
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
8001fe0: b480 push {r7}
8001fe2: b085 sub sp, #20
8001fe4: af00 add r7, sp, #0
8001fe6: 60f8 str r0, [r7, #12]
8001fe8: 60b9 str r1, [r7, #8]
8001fea: 607a str r2, [r7, #4]
8001fec: 603b str r3, [r7, #0]
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
8001fee: 68fb ldr r3, [r7, #12]
8001ff0: 6c1a ldr r2, [r3, #64] ; 0x40
8001ff2: 68fb ldr r3, [r7, #12]
8001ff4: 6bdb ldr r3, [r3, #60] ; 0x3c
8001ff6: 2101 movs r1, #1
8001ff8: fa01 f202 lsl.w r2, r1, r2
8001ffc: 605a str r2, [r3, #4]
/* Configure DMA Channel data length */
hdma->Instance->CNDTR = DataLength;
8001ffe: 68fb ldr r3, [r7, #12]
8002000: 681b ldr r3, [r3, #0]
8002002: 683a ldr r2, [r7, #0]
8002004: 605a str r2, [r3, #4]
/* Memory to Peripheral */
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
8002006: 68fb ldr r3, [r7, #12]
8002008: 685b ldr r3, [r3, #4]
800200a: 2b10 cmp r3, #16
800200c: d108 bne.n 8002020 <DMA_SetConfig+0x40>
{
/* Configure DMA Channel destination address */
hdma->Instance->CPAR = DstAddress;
800200e: 68fb ldr r3, [r7, #12]
8002010: 681b ldr r3, [r3, #0]
8002012: 687a ldr r2, [r7, #4]
8002014: 609a str r2, [r3, #8]
/* Configure DMA Channel source address */
hdma->Instance->CMAR = SrcAddress;
8002016: 68fb ldr r3, [r7, #12]
8002018: 681b ldr r3, [r3, #0]
800201a: 68ba ldr r2, [r7, #8]
800201c: 60da str r2, [r3, #12]
hdma->Instance->CPAR = SrcAddress;
/* Configure DMA Channel destination address */
hdma->Instance->CMAR = DstAddress;
}
}
800201e: e007 b.n 8002030 <DMA_SetConfig+0x50>
hdma->Instance->CPAR = SrcAddress;
8002020: 68fb ldr r3, [r7, #12]
8002022: 681b ldr r3, [r3, #0]
8002024: 68ba ldr r2, [r7, #8]
8002026: 609a str r2, [r3, #8]
hdma->Instance->CMAR = DstAddress;
8002028: 68fb ldr r3, [r7, #12]
800202a: 681b ldr r3, [r3, #0]
800202c: 687a ldr r2, [r7, #4]
800202e: 60da str r2, [r3, #12]
}
8002030: bf00 nop
8002032: 3714 adds r7, #20
8002034: 46bd mov sp, r7
8002036: bc80 pop {r7}
8002038: 4770 bx lr
...
0800203c <HAL_GPIO_Init>:
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
800203c: b480 push {r7}
800203e: b08b sub sp, #44 ; 0x2c
8002040: af00 add r7, sp, #0
8002042: 6078 str r0, [r7, #4]
8002044: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
8002046: 2300 movs r3, #0
8002048: 627b str r3, [r7, #36] ; 0x24
uint32_t ioposition;
uint32_t iocurrent;
uint32_t temp;
uint32_t config = 0x00u;
800204a: 2300 movs r3, #0
800204c: 623b str r3, [r7, #32]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
800204e: e169 b.n 8002324 <HAL_GPIO_Init+0x2e8>
{
/* Get the IO position */
ioposition = (0x01uL << position);
8002050: 2201 movs r2, #1
8002052: 6a7b ldr r3, [r7, #36] ; 0x24
8002054: fa02 f303 lsl.w r3, r2, r3
8002058: 61fb str r3, [r7, #28]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
800205a: 683b ldr r3, [r7, #0]
800205c: 681b ldr r3, [r3, #0]
800205e: 69fa ldr r2, [r7, #28]
8002060: 4013 ands r3, r2
8002062: 61bb str r3, [r7, #24]
if (iocurrent == ioposition)
8002064: 69ba ldr r2, [r7, #24]
8002066: 69fb ldr r3, [r7, #28]
8002068: 429a cmp r2, r3
800206a: f040 8158 bne.w 800231e <HAL_GPIO_Init+0x2e2>
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
/* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
switch (GPIO_Init->Mode)
800206e: 683b ldr r3, [r7, #0]
8002070: 685b ldr r3, [r3, #4]
8002072: 4a9a ldr r2, [pc, #616] ; (80022dc <HAL_GPIO_Init+0x2a0>)
8002074: 4293 cmp r3, r2
8002076: d05e beq.n 8002136 <HAL_GPIO_Init+0xfa>
8002078: 4a98 ldr r2, [pc, #608] ; (80022dc <HAL_GPIO_Init+0x2a0>)
800207a: 4293 cmp r3, r2
800207c: d875 bhi.n 800216a <HAL_GPIO_Init+0x12e>
800207e: 4a98 ldr r2, [pc, #608] ; (80022e0 <HAL_GPIO_Init+0x2a4>)
8002080: 4293 cmp r3, r2
8002082: d058 beq.n 8002136 <HAL_GPIO_Init+0xfa>
8002084: 4a96 ldr r2, [pc, #600] ; (80022e0 <HAL_GPIO_Init+0x2a4>)
8002086: 4293 cmp r3, r2
8002088: d86f bhi.n 800216a <HAL_GPIO_Init+0x12e>
800208a: 4a96 ldr r2, [pc, #600] ; (80022e4 <HAL_GPIO_Init+0x2a8>)
800208c: 4293 cmp r3, r2
800208e: d052 beq.n 8002136 <HAL_GPIO_Init+0xfa>
8002090: 4a94 ldr r2, [pc, #592] ; (80022e4 <HAL_GPIO_Init+0x2a8>)
8002092: 4293 cmp r3, r2
8002094: d869 bhi.n 800216a <HAL_GPIO_Init+0x12e>
8002096: 4a94 ldr r2, [pc, #592] ; (80022e8 <HAL_GPIO_Init+0x2ac>)
8002098: 4293 cmp r3, r2
800209a: d04c beq.n 8002136 <HAL_GPIO_Init+0xfa>
800209c: 4a92 ldr r2, [pc, #584] ; (80022e8 <HAL_GPIO_Init+0x2ac>)
800209e: 4293 cmp r3, r2
80020a0: d863 bhi.n 800216a <HAL_GPIO_Init+0x12e>
80020a2: 4a92 ldr r2, [pc, #584] ; (80022ec <HAL_GPIO_Init+0x2b0>)
80020a4: 4293 cmp r3, r2
80020a6: d046 beq.n 8002136 <HAL_GPIO_Init+0xfa>
80020a8: 4a90 ldr r2, [pc, #576] ; (80022ec <HAL_GPIO_Init+0x2b0>)
80020aa: 4293 cmp r3, r2
80020ac: d85d bhi.n 800216a <HAL_GPIO_Init+0x12e>
80020ae: 2b12 cmp r3, #18
80020b0: d82a bhi.n 8002108 <HAL_GPIO_Init+0xcc>
80020b2: 2b12 cmp r3, #18
80020b4: d859 bhi.n 800216a <HAL_GPIO_Init+0x12e>
80020b6: a201 add r2, pc, #4 ; (adr r2, 80020bc <HAL_GPIO_Init+0x80>)
80020b8: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80020bc: 08002137 .word 0x08002137
80020c0: 08002111 .word 0x08002111
80020c4: 08002123 .word 0x08002123
80020c8: 08002165 .word 0x08002165
80020cc: 0800216b .word 0x0800216b
80020d0: 0800216b .word 0x0800216b
80020d4: 0800216b .word 0x0800216b
80020d8: 0800216b .word 0x0800216b
80020dc: 0800216b .word 0x0800216b
80020e0: 0800216b .word 0x0800216b
80020e4: 0800216b .word 0x0800216b
80020e8: 0800216b .word 0x0800216b
80020ec: 0800216b .word 0x0800216b
80020f0: 0800216b .word 0x0800216b
80020f4: 0800216b .word 0x0800216b
80020f8: 0800216b .word 0x0800216b
80020fc: 0800216b .word 0x0800216b
8002100: 08002119 .word 0x08002119
8002104: 0800212d .word 0x0800212d
8002108: 4a79 ldr r2, [pc, #484] ; (80022f0 <HAL_GPIO_Init+0x2b4>)
800210a: 4293 cmp r3, r2
800210c: d013 beq.n 8002136 <HAL_GPIO_Init+0xfa>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
break;
/* Parameters are checked with assert_param */
default:
break;
800210e: e02c b.n 800216a <HAL_GPIO_Init+0x12e>
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
8002110: 683b ldr r3, [r7, #0]
8002112: 68db ldr r3, [r3, #12]
8002114: 623b str r3, [r7, #32]
break;
8002116: e029 b.n 800216c <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
8002118: 683b ldr r3, [r7, #0]
800211a: 68db ldr r3, [r3, #12]
800211c: 3304 adds r3, #4
800211e: 623b str r3, [r7, #32]
break;
8002120: e024 b.n 800216c <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
8002122: 683b ldr r3, [r7, #0]
8002124: 68db ldr r3, [r3, #12]
8002126: 3308 adds r3, #8
8002128: 623b str r3, [r7, #32]
break;
800212a: e01f b.n 800216c <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
800212c: 683b ldr r3, [r7, #0]
800212e: 68db ldr r3, [r3, #12]
8002130: 330c adds r3, #12
8002132: 623b str r3, [r7, #32]
break;
8002134: e01a b.n 800216c <HAL_GPIO_Init+0x130>
if (GPIO_Init->Pull == GPIO_NOPULL)
8002136: 683b ldr r3, [r7, #0]
8002138: 689b ldr r3, [r3, #8]
800213a: 2b00 cmp r3, #0
800213c: d102 bne.n 8002144 <HAL_GPIO_Init+0x108>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
800213e: 2304 movs r3, #4
8002140: 623b str r3, [r7, #32]
break;
8002142: e013 b.n 800216c <HAL_GPIO_Init+0x130>
else if (GPIO_Init->Pull == GPIO_PULLUP)
8002144: 683b ldr r3, [r7, #0]
8002146: 689b ldr r3, [r3, #8]
8002148: 2b01 cmp r3, #1
800214a: d105 bne.n 8002158 <HAL_GPIO_Init+0x11c>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
800214c: 2308 movs r3, #8
800214e: 623b str r3, [r7, #32]
GPIOx->BSRR = ioposition;
8002150: 687b ldr r3, [r7, #4]
8002152: 69fa ldr r2, [r7, #28]
8002154: 611a str r2, [r3, #16]
break;
8002156: e009 b.n 800216c <HAL_GPIO_Init+0x130>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
8002158: 2308 movs r3, #8
800215a: 623b str r3, [r7, #32]
GPIOx->BRR = ioposition;
800215c: 687b ldr r3, [r7, #4]
800215e: 69fa ldr r2, [r7, #28]
8002160: 615a str r2, [r3, #20]
break;
8002162: e003 b.n 800216c <HAL_GPIO_Init+0x130>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
8002164: 2300 movs r3, #0
8002166: 623b str r3, [r7, #32]
break;
8002168: e000 b.n 800216c <HAL_GPIO_Init+0x130>
break;
800216a: bf00 nop
}
/* Check if the current bit belongs to first half or last half of the pin count number
in order to address CRH or CRL register*/
configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
800216c: 69bb ldr r3, [r7, #24]
800216e: 2bff cmp r3, #255 ; 0xff
8002170: d801 bhi.n 8002176 <HAL_GPIO_Init+0x13a>
8002172: 687b ldr r3, [r7, #4]
8002174: e001 b.n 800217a <HAL_GPIO_Init+0x13e>
8002176: 687b ldr r3, [r7, #4]
8002178: 3304 adds r3, #4
800217a: 617b str r3, [r7, #20]
registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
800217c: 69bb ldr r3, [r7, #24]
800217e: 2bff cmp r3, #255 ; 0xff
8002180: d802 bhi.n 8002188 <HAL_GPIO_Init+0x14c>
8002182: 6a7b ldr r3, [r7, #36] ; 0x24
8002184: 009b lsls r3, r3, #2
8002186: e002 b.n 800218e <HAL_GPIO_Init+0x152>
8002188: 6a7b ldr r3, [r7, #36] ; 0x24
800218a: 3b08 subs r3, #8
800218c: 009b lsls r3, r3, #2
800218e: 613b str r3, [r7, #16]
/* Apply the new configuration of the pin to the register */
MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
8002190: 697b ldr r3, [r7, #20]
8002192: 681a ldr r2, [r3, #0]
8002194: 210f movs r1, #15
8002196: 693b ldr r3, [r7, #16]
8002198: fa01 f303 lsl.w r3, r1, r3
800219c: 43db mvns r3, r3
800219e: 401a ands r2, r3
80021a0: 6a39 ldr r1, [r7, #32]
80021a2: 693b ldr r3, [r7, #16]
80021a4: fa01 f303 lsl.w r3, r1, r3
80021a8: 431a orrs r2, r3
80021aa: 697b ldr r3, [r7, #20]
80021ac: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
80021ae: 683b ldr r3, [r7, #0]
80021b0: 685b ldr r3, [r3, #4]
80021b2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
80021b6: 2b00 cmp r3, #0
80021b8: f000 80b1 beq.w 800231e <HAL_GPIO_Init+0x2e2>
{
/* Enable AFIO Clock */
__HAL_RCC_AFIO_CLK_ENABLE();
80021bc: 4b4d ldr r3, [pc, #308] ; (80022f4 <HAL_GPIO_Init+0x2b8>)
80021be: 699b ldr r3, [r3, #24]
80021c0: 4a4c ldr r2, [pc, #304] ; (80022f4 <HAL_GPIO_Init+0x2b8>)
80021c2: f043 0301 orr.w r3, r3, #1
80021c6: 6193 str r3, [r2, #24]
80021c8: 4b4a ldr r3, [pc, #296] ; (80022f4 <HAL_GPIO_Init+0x2b8>)
80021ca: 699b ldr r3, [r3, #24]
80021cc: f003 0301 and.w r3, r3, #1
80021d0: 60bb str r3, [r7, #8]
80021d2: 68bb ldr r3, [r7, #8]
temp = AFIO->EXTICR[position >> 2u];
80021d4: 4a48 ldr r2, [pc, #288] ; (80022f8 <HAL_GPIO_Init+0x2bc>)
80021d6: 6a7b ldr r3, [r7, #36] ; 0x24
80021d8: 089b lsrs r3, r3, #2
80021da: 3302 adds r3, #2
80021dc: f852 3023 ldr.w r3, [r2, r3, lsl #2]
80021e0: 60fb str r3, [r7, #12]
CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
80021e2: 6a7b ldr r3, [r7, #36] ; 0x24
80021e4: f003 0303 and.w r3, r3, #3
80021e8: 009b lsls r3, r3, #2
80021ea: 220f movs r2, #15
80021ec: fa02 f303 lsl.w r3, r2, r3
80021f0: 43db mvns r3, r3
80021f2: 68fa ldr r2, [r7, #12]
80021f4: 4013 ands r3, r2
80021f6: 60fb str r3, [r7, #12]
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
80021f8: 687b ldr r3, [r7, #4]
80021fa: 4a40 ldr r2, [pc, #256] ; (80022fc <HAL_GPIO_Init+0x2c0>)
80021fc: 4293 cmp r3, r2
80021fe: d013 beq.n 8002228 <HAL_GPIO_Init+0x1ec>
8002200: 687b ldr r3, [r7, #4]
8002202: 4a3f ldr r2, [pc, #252] ; (8002300 <HAL_GPIO_Init+0x2c4>)
8002204: 4293 cmp r3, r2
8002206: d00d beq.n 8002224 <HAL_GPIO_Init+0x1e8>
8002208: 687b ldr r3, [r7, #4]
800220a: 4a3e ldr r2, [pc, #248] ; (8002304 <HAL_GPIO_Init+0x2c8>)
800220c: 4293 cmp r3, r2
800220e: d007 beq.n 8002220 <HAL_GPIO_Init+0x1e4>
8002210: 687b ldr r3, [r7, #4]
8002212: 4a3d ldr r2, [pc, #244] ; (8002308 <HAL_GPIO_Init+0x2cc>)
8002214: 4293 cmp r3, r2
8002216: d101 bne.n 800221c <HAL_GPIO_Init+0x1e0>
8002218: 2303 movs r3, #3
800221a: e006 b.n 800222a <HAL_GPIO_Init+0x1ee>
800221c: 2304 movs r3, #4
800221e: e004 b.n 800222a <HAL_GPIO_Init+0x1ee>
8002220: 2302 movs r3, #2
8002222: e002 b.n 800222a <HAL_GPIO_Init+0x1ee>
8002224: 2301 movs r3, #1
8002226: e000 b.n 800222a <HAL_GPIO_Init+0x1ee>
8002228: 2300 movs r3, #0
800222a: 6a7a ldr r2, [r7, #36] ; 0x24
800222c: f002 0203 and.w r2, r2, #3
8002230: 0092 lsls r2, r2, #2
8002232: 4093 lsls r3, r2
8002234: 68fa ldr r2, [r7, #12]
8002236: 4313 orrs r3, r2
8002238: 60fb str r3, [r7, #12]
AFIO->EXTICR[position >> 2u] = temp;
800223a: 492f ldr r1, [pc, #188] ; (80022f8 <HAL_GPIO_Init+0x2bc>)
800223c: 6a7b ldr r3, [r7, #36] ; 0x24
800223e: 089b lsrs r3, r3, #2
8002240: 3302 adds r3, #2
8002242: 68fa ldr r2, [r7, #12]
8002244: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Configure the interrupt mask */
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
8002248: 683b ldr r3, [r7, #0]
800224a: 685b ldr r3, [r3, #4]
800224c: f403 3380 and.w r3, r3, #65536 ; 0x10000
8002250: 2b00 cmp r3, #0
8002252: d006 beq.n 8002262 <HAL_GPIO_Init+0x226>
{
SET_BIT(EXTI->IMR, iocurrent);
8002254: 4b2d ldr r3, [pc, #180] ; (800230c <HAL_GPIO_Init+0x2d0>)
8002256: 681a ldr r2, [r3, #0]
8002258: 492c ldr r1, [pc, #176] ; (800230c <HAL_GPIO_Init+0x2d0>)
800225a: 69bb ldr r3, [r7, #24]
800225c: 4313 orrs r3, r2
800225e: 600b str r3, [r1, #0]
8002260: e006 b.n 8002270 <HAL_GPIO_Init+0x234>
}
else
{
CLEAR_BIT(EXTI->IMR, iocurrent);
8002262: 4b2a ldr r3, [pc, #168] ; (800230c <HAL_GPIO_Init+0x2d0>)
8002264: 681a ldr r2, [r3, #0]
8002266: 69bb ldr r3, [r7, #24]
8002268: 43db mvns r3, r3
800226a: 4928 ldr r1, [pc, #160] ; (800230c <HAL_GPIO_Init+0x2d0>)
800226c: 4013 ands r3, r2
800226e: 600b str r3, [r1, #0]
}
/* Configure the event mask */
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
8002270: 683b ldr r3, [r7, #0]
8002272: 685b ldr r3, [r3, #4]
8002274: f403 3300 and.w r3, r3, #131072 ; 0x20000
8002278: 2b00 cmp r3, #0
800227a: d006 beq.n 800228a <HAL_GPIO_Init+0x24e>
{
SET_BIT(EXTI->EMR, iocurrent);
800227c: 4b23 ldr r3, [pc, #140] ; (800230c <HAL_GPIO_Init+0x2d0>)
800227e: 685a ldr r2, [r3, #4]
8002280: 4922 ldr r1, [pc, #136] ; (800230c <HAL_GPIO_Init+0x2d0>)
8002282: 69bb ldr r3, [r7, #24]
8002284: 4313 orrs r3, r2
8002286: 604b str r3, [r1, #4]
8002288: e006 b.n 8002298 <HAL_GPIO_Init+0x25c>
}
else
{
CLEAR_BIT(EXTI->EMR, iocurrent);
800228a: 4b20 ldr r3, [pc, #128] ; (800230c <HAL_GPIO_Init+0x2d0>)
800228c: 685a ldr r2, [r3, #4]
800228e: 69bb ldr r3, [r7, #24]
8002290: 43db mvns r3, r3
8002292: 491e ldr r1, [pc, #120] ; (800230c <HAL_GPIO_Init+0x2d0>)
8002294: 4013 ands r3, r2
8002296: 604b str r3, [r1, #4]
}
/* Enable or disable the rising trigger */
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
8002298: 683b ldr r3, [r7, #0]
800229a: 685b ldr r3, [r3, #4]
800229c: f403 1380 and.w r3, r3, #1048576 ; 0x100000
80022a0: 2b00 cmp r3, #0
80022a2: d006 beq.n 80022b2 <HAL_GPIO_Init+0x276>
{
SET_BIT(EXTI->RTSR, iocurrent);
80022a4: 4b19 ldr r3, [pc, #100] ; (800230c <HAL_GPIO_Init+0x2d0>)
80022a6: 689a ldr r2, [r3, #8]
80022a8: 4918 ldr r1, [pc, #96] ; (800230c <HAL_GPIO_Init+0x2d0>)
80022aa: 69bb ldr r3, [r7, #24]
80022ac: 4313 orrs r3, r2
80022ae: 608b str r3, [r1, #8]
80022b0: e006 b.n 80022c0 <HAL_GPIO_Init+0x284>
}
else
{
CLEAR_BIT(EXTI->RTSR, iocurrent);
80022b2: 4b16 ldr r3, [pc, #88] ; (800230c <HAL_GPIO_Init+0x2d0>)
80022b4: 689a ldr r2, [r3, #8]
80022b6: 69bb ldr r3, [r7, #24]
80022b8: 43db mvns r3, r3
80022ba: 4914 ldr r1, [pc, #80] ; (800230c <HAL_GPIO_Init+0x2d0>)
80022bc: 4013 ands r3, r2
80022be: 608b str r3, [r1, #8]
}
/* Enable or disable the falling trigger */
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
80022c0: 683b ldr r3, [r7, #0]
80022c2: 685b ldr r3, [r3, #4]
80022c4: f403 1300 and.w r3, r3, #2097152 ; 0x200000
80022c8: 2b00 cmp r3, #0
80022ca: d021 beq.n 8002310 <HAL_GPIO_Init+0x2d4>
{
SET_BIT(EXTI->FTSR, iocurrent);
80022cc: 4b0f ldr r3, [pc, #60] ; (800230c <HAL_GPIO_Init+0x2d0>)
80022ce: 68da ldr r2, [r3, #12]
80022d0: 490e ldr r1, [pc, #56] ; (800230c <HAL_GPIO_Init+0x2d0>)
80022d2: 69bb ldr r3, [r7, #24]
80022d4: 4313 orrs r3, r2
80022d6: 60cb str r3, [r1, #12]
80022d8: e021 b.n 800231e <HAL_GPIO_Init+0x2e2>
80022da: bf00 nop
80022dc: 10320000 .word 0x10320000
80022e0: 10310000 .word 0x10310000
80022e4: 10220000 .word 0x10220000
80022e8: 10210000 .word 0x10210000
80022ec: 10120000 .word 0x10120000
80022f0: 10110000 .word 0x10110000
80022f4: 40021000 .word 0x40021000
80022f8: 40010000 .word 0x40010000
80022fc: 40010800 .word 0x40010800
8002300: 40010c00 .word 0x40010c00
8002304: 40011000 .word 0x40011000
8002308: 40011400 .word 0x40011400
800230c: 40010400 .word 0x40010400
}
else
{
CLEAR_BIT(EXTI->FTSR, iocurrent);
8002310: 4b0b ldr r3, [pc, #44] ; (8002340 <HAL_GPIO_Init+0x304>)
8002312: 68da ldr r2, [r3, #12]
8002314: 69bb ldr r3, [r7, #24]
8002316: 43db mvns r3, r3
8002318: 4909 ldr r1, [pc, #36] ; (8002340 <HAL_GPIO_Init+0x304>)
800231a: 4013 ands r3, r2
800231c: 60cb str r3, [r1, #12]
}
}
}
position++;
800231e: 6a7b ldr r3, [r7, #36] ; 0x24
8002320: 3301 adds r3, #1
8002322: 627b str r3, [r7, #36] ; 0x24
while (((GPIO_Init->Pin) >> position) != 0x00u)
8002324: 683b ldr r3, [r7, #0]
8002326: 681a ldr r2, [r3, #0]
8002328: 6a7b ldr r3, [r7, #36] ; 0x24
800232a: fa22 f303 lsr.w r3, r2, r3
800232e: 2b00 cmp r3, #0
8002330: f47f ae8e bne.w 8002050 <HAL_GPIO_Init+0x14>
}
}
8002334: bf00 nop
8002336: bf00 nop
8002338: 372c adds r7, #44 ; 0x2c
800233a: 46bd mov sp, r7
800233c: bc80 pop {r7}
800233e: 4770 bx lr
8002340: 40010400 .word 0x40010400
08002344 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8002344: b480 push {r7}
8002346: b083 sub sp, #12
8002348: af00 add r7, sp, #0
800234a: 6078 str r0, [r7, #4]
800234c: 460b mov r3, r1
800234e: 807b strh r3, [r7, #2]
8002350: 4613 mov r3, r2
8002352: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
8002354: 787b ldrb r3, [r7, #1]
8002356: 2b00 cmp r3, #0
8002358: d003 beq.n 8002362 <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
800235a: 887a ldrh r2, [r7, #2]
800235c: 687b ldr r3, [r7, #4]
800235e: 611a str r2, [r3, #16]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
}
}
8002360: e003 b.n 800236a <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
8002362: 887b ldrh r3, [r7, #2]
8002364: 041a lsls r2, r3, #16
8002366: 687b ldr r3, [r7, #4]
8002368: 611a str r2, [r3, #16]
}
800236a: bf00 nop
800236c: 370c adds r7, #12
800236e: 46bd mov sp, r7
8002370: bc80 pop {r7}
8002372: 4770 bx lr
08002374 <HAL_PCD_Init>:
* parameters in the PCD_InitTypeDef and initialize the associated handle.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
{
8002374: b5f0 push {r4, r5, r6, r7, lr}
8002376: b08b sub sp, #44 ; 0x2c
8002378: af06 add r7, sp, #24
800237a: 6078 str r0, [r7, #4]
USB_OTG_GlobalTypeDef *USBx;
#endif /* defined (USB_OTG_FS) */
uint8_t i;
/* Check the PCD handle allocation */
if (hpcd == NULL)
800237c: 687b ldr r3, [r7, #4]
800237e: 2b00 cmp r3, #0
8002380: d101 bne.n 8002386 <HAL_PCD_Init+0x12>
{
return HAL_ERROR;
8002382: 2301 movs r3, #1
8002384: e0fd b.n 8002582 <HAL_PCD_Init+0x20e>
#if defined (USB_OTG_FS)
USBx = hpcd->Instance;
#endif /* defined (USB_OTG_FS) */
if (hpcd->State == HAL_PCD_STATE_RESET)
8002386: 687b ldr r3, [r7, #4]
8002388: f893 32a9 ldrb.w r3, [r3, #681] ; 0x2a9
800238c: b2db uxtb r3, r3
800238e: 2b00 cmp r3, #0
8002390: d106 bne.n 80023a0 <HAL_PCD_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hpcd->Lock = HAL_UNLOCKED;
8002392: 687b ldr r3, [r7, #4]
8002394: 2200 movs r2, #0
8002396: f883 22a8 strb.w r2, [r3, #680] ; 0x2a8
/* Init the low level hardware */
hpcd->MspInitCallback(hpcd);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_PCD_MspInit(hpcd);
800239a: 6878 ldr r0, [r7, #4]
800239c: f7ff f92a bl 80015f4 <HAL_PCD_MspInit>
#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
}
hpcd->State = HAL_PCD_STATE_BUSY;
80023a0: 687b ldr r3, [r7, #4]
80023a2: 2203 movs r2, #3
80023a4: f883 22a9 strb.w r2, [r3, #681] ; 0x2a9
hpcd->Init.dma_enable = 0U;
}
#endif /* defined (USB_OTG_FS) */
/* Disable the Interrupts */
__HAL_PCD_DISABLE(hpcd);
80023a8: 687b ldr r3, [r7, #4]
80023aa: 681b ldr r3, [r3, #0]
80023ac: 4618 mov r0, r3
80023ae: f002 fcb1 bl 8004d14 <USB_DisableGlobalInt>
/*Init the Core (common init.) */
if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)
80023b2: 687b ldr r3, [r7, #4]
80023b4: 681b ldr r3, [r3, #0]
80023b6: 603b str r3, [r7, #0]
80023b8: 687e ldr r6, [r7, #4]
80023ba: 466d mov r5, sp
80023bc: f106 0410 add.w r4, r6, #16
80023c0: cc0f ldmia r4!, {r0, r1, r2, r3}
80023c2: c50f stmia r5!, {r0, r1, r2, r3}
80023c4: 6823 ldr r3, [r4, #0]
80023c6: 602b str r3, [r5, #0]
80023c8: 1d33 adds r3, r6, #4
80023ca: cb0e ldmia r3, {r1, r2, r3}
80023cc: 6838 ldr r0, [r7, #0]
80023ce: f002 fc91 bl 8004cf4 <USB_CoreInit>
80023d2: 4603 mov r3, r0
80023d4: 2b00 cmp r3, #0
80023d6: d005 beq.n 80023e4 <HAL_PCD_Init+0x70>
{
hpcd->State = HAL_PCD_STATE_ERROR;
80023d8: 687b ldr r3, [r7, #4]
80023da: 2202 movs r2, #2
80023dc: f883 22a9 strb.w r2, [r3, #681] ; 0x2a9
return HAL_ERROR;
80023e0: 2301 movs r3, #1
80023e2: e0ce b.n 8002582 <HAL_PCD_Init+0x20e>
}
/* Force Device Mode*/
(void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE);
80023e4: 687b ldr r3, [r7, #4]
80023e6: 681b ldr r3, [r3, #0]
80023e8: 2100 movs r1, #0
80023ea: 4618 mov r0, r3
80023ec: f002 fcac bl 8004d48 <USB_SetCurrentMode>
/* Init endpoints structures */
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
80023f0: 2300 movs r3, #0
80023f2: 73fb strb r3, [r7, #15]
80023f4: e04c b.n 8002490 <HAL_PCD_Init+0x11c>
{
/* Init ep structure */
hpcd->IN_ep[i].is_in = 1U;
80023f6: 7bfb ldrb r3, [r7, #15]
80023f8: 6879 ldr r1, [r7, #4]
80023fa: 1c5a adds r2, r3, #1
80023fc: 4613 mov r3, r2
80023fe: 009b lsls r3, r3, #2
8002400: 4413 add r3, r2
8002402: 00db lsls r3, r3, #3
8002404: 440b add r3, r1
8002406: 3301 adds r3, #1
8002408: 2201 movs r2, #1
800240a: 701a strb r2, [r3, #0]
hpcd->IN_ep[i].num = i;
800240c: 7bfb ldrb r3, [r7, #15]
800240e: 6879 ldr r1, [r7, #4]
8002410: 1c5a adds r2, r3, #1
8002412: 4613 mov r3, r2
8002414: 009b lsls r3, r3, #2
8002416: 4413 add r3, r2
8002418: 00db lsls r3, r3, #3
800241a: 440b add r3, r1
800241c: 7bfa ldrb r2, [r7, #15]
800241e: 701a strb r2, [r3, #0]
hpcd->IN_ep[i].tx_fifo_num = i;
8002420: 7bfa ldrb r2, [r7, #15]
8002422: 7bfb ldrb r3, [r7, #15]
8002424: b298 uxth r0, r3
8002426: 6879 ldr r1, [r7, #4]
8002428: 4613 mov r3, r2
800242a: 009b lsls r3, r3, #2
800242c: 4413 add r3, r2
800242e: 00db lsls r3, r3, #3
8002430: 440b add r3, r1
8002432: 3336 adds r3, #54 ; 0x36
8002434: 4602 mov r2, r0
8002436: 801a strh r2, [r3, #0]
/* Control until ep is activated */
hpcd->IN_ep[i].type = EP_TYPE_CTRL;
8002438: 7bfb ldrb r3, [r7, #15]
800243a: 6879 ldr r1, [r7, #4]
800243c: 1c5a adds r2, r3, #1
800243e: 4613 mov r3, r2
8002440: 009b lsls r3, r3, #2
8002442: 4413 add r3, r2
8002444: 00db lsls r3, r3, #3
8002446: 440b add r3, r1
8002448: 3303 adds r3, #3
800244a: 2200 movs r2, #0
800244c: 701a strb r2, [r3, #0]
hpcd->IN_ep[i].maxpacket = 0U;
800244e: 7bfa ldrb r2, [r7, #15]
8002450: 6879 ldr r1, [r7, #4]
8002452: 4613 mov r3, r2
8002454: 009b lsls r3, r3, #2
8002456: 4413 add r3, r2
8002458: 00db lsls r3, r3, #3
800245a: 440b add r3, r1
800245c: 3338 adds r3, #56 ; 0x38
800245e: 2200 movs r2, #0
8002460: 601a str r2, [r3, #0]
hpcd->IN_ep[i].xfer_buff = 0U;
8002462: 7bfa ldrb r2, [r7, #15]
8002464: 6879 ldr r1, [r7, #4]
8002466: 4613 mov r3, r2
8002468: 009b lsls r3, r3, #2
800246a: 4413 add r3, r2
800246c: 00db lsls r3, r3, #3
800246e: 440b add r3, r1
8002470: 333c adds r3, #60 ; 0x3c
8002472: 2200 movs r2, #0
8002474: 601a str r2, [r3, #0]
hpcd->IN_ep[i].xfer_len = 0U;
8002476: 7bfa ldrb r2, [r7, #15]
8002478: 6879 ldr r1, [r7, #4]
800247a: 4613 mov r3, r2
800247c: 009b lsls r3, r3, #2
800247e: 4413 add r3, r2
8002480: 00db lsls r3, r3, #3
8002482: 440b add r3, r1
8002484: 3340 adds r3, #64 ; 0x40
8002486: 2200 movs r2, #0
8002488: 601a str r2, [r3, #0]
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
800248a: 7bfb ldrb r3, [r7, #15]
800248c: 3301 adds r3, #1
800248e: 73fb strb r3, [r7, #15]
8002490: 7bfa ldrb r2, [r7, #15]
8002492: 687b ldr r3, [r7, #4]
8002494: 685b ldr r3, [r3, #4]
8002496: 429a cmp r2, r3
8002498: d3ad bcc.n 80023f6 <HAL_PCD_Init+0x82>
}
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
800249a: 2300 movs r3, #0
800249c: 73fb strb r3, [r7, #15]
800249e: e044 b.n 800252a <HAL_PCD_Init+0x1b6>
{
hpcd->OUT_ep[i].is_in = 0U;
80024a0: 7bfa ldrb r2, [r7, #15]
80024a2: 6879 ldr r1, [r7, #4]
80024a4: 4613 mov r3, r2
80024a6: 009b lsls r3, r3, #2
80024a8: 4413 add r3, r2
80024aa: 00db lsls r3, r3, #3
80024ac: 440b add r3, r1
80024ae: f203 1369 addw r3, r3, #361 ; 0x169
80024b2: 2200 movs r2, #0
80024b4: 701a strb r2, [r3, #0]
hpcd->OUT_ep[i].num = i;
80024b6: 7bfa ldrb r2, [r7, #15]
80024b8: 6879 ldr r1, [r7, #4]
80024ba: 4613 mov r3, r2
80024bc: 009b lsls r3, r3, #2
80024be: 4413 add r3, r2
80024c0: 00db lsls r3, r3, #3
80024c2: 440b add r3, r1
80024c4: f503 73b4 add.w r3, r3, #360 ; 0x168
80024c8: 7bfa ldrb r2, [r7, #15]
80024ca: 701a strb r2, [r3, #0]
/* Control until ep is activated */
hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
80024cc: 7bfa ldrb r2, [r7, #15]
80024ce: 6879 ldr r1, [r7, #4]
80024d0: 4613 mov r3, r2
80024d2: 009b lsls r3, r3, #2
80024d4: 4413 add r3, r2
80024d6: 00db lsls r3, r3, #3
80024d8: 440b add r3, r1
80024da: f203 136b addw r3, r3, #363 ; 0x16b
80024de: 2200 movs r2, #0
80024e0: 701a strb r2, [r3, #0]
hpcd->OUT_ep[i].maxpacket = 0U;
80024e2: 7bfa ldrb r2, [r7, #15]
80024e4: 6879 ldr r1, [r7, #4]
80024e6: 4613 mov r3, r2
80024e8: 009b lsls r3, r3, #2
80024ea: 4413 add r3, r2
80024ec: 00db lsls r3, r3, #3
80024ee: 440b add r3, r1
80024f0: f503 73bc add.w r3, r3, #376 ; 0x178
80024f4: 2200 movs r2, #0
80024f6: 601a str r2, [r3, #0]
hpcd->OUT_ep[i].xfer_buff = 0U;
80024f8: 7bfa ldrb r2, [r7, #15]
80024fa: 6879 ldr r1, [r7, #4]
80024fc: 4613 mov r3, r2
80024fe: 009b lsls r3, r3, #2
8002500: 4413 add r3, r2
8002502: 00db lsls r3, r3, #3
8002504: 440b add r3, r1
8002506: f503 73be add.w r3, r3, #380 ; 0x17c
800250a: 2200 movs r2, #0
800250c: 601a str r2, [r3, #0]
hpcd->OUT_ep[i].xfer_len = 0U;
800250e: 7bfa ldrb r2, [r7, #15]
8002510: 6879 ldr r1, [r7, #4]
8002512: 4613 mov r3, r2
8002514: 009b lsls r3, r3, #2
8002516: 4413 add r3, r2
8002518: 00db lsls r3, r3, #3
800251a: 440b add r3, r1
800251c: f503 73c0 add.w r3, r3, #384 ; 0x180
8002520: 2200 movs r2, #0
8002522: 601a str r2, [r3, #0]
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8002524: 7bfb ldrb r3, [r7, #15]
8002526: 3301 adds r3, #1
8002528: 73fb strb r3, [r7, #15]
800252a: 7bfa ldrb r2, [r7, #15]
800252c: 687b ldr r3, [r7, #4]
800252e: 685b ldr r3, [r3, #4]
8002530: 429a cmp r2, r3
8002532: d3b5 bcc.n 80024a0 <HAL_PCD_Init+0x12c>
}
/* Init Device */
if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)
8002534: 687b ldr r3, [r7, #4]
8002536: 681b ldr r3, [r3, #0]
8002538: 603b str r3, [r7, #0]
800253a: 687e ldr r6, [r7, #4]
800253c: 466d mov r5, sp
800253e: f106 0410 add.w r4, r6, #16
8002542: cc0f ldmia r4!, {r0, r1, r2, r3}
8002544: c50f stmia r5!, {r0, r1, r2, r3}
8002546: 6823 ldr r3, [r4, #0]
8002548: 602b str r3, [r5, #0]
800254a: 1d33 adds r3, r6, #4
800254c: cb0e ldmia r3, {r1, r2, r3}
800254e: 6838 ldr r0, [r7, #0]
8002550: f002 fc06 bl 8004d60 <USB_DevInit>
8002554: 4603 mov r3, r0
8002556: 2b00 cmp r3, #0
8002558: d005 beq.n 8002566 <HAL_PCD_Init+0x1f2>
{
hpcd->State = HAL_PCD_STATE_ERROR;
800255a: 687b ldr r3, [r7, #4]
800255c: 2202 movs r2, #2
800255e: f883 22a9 strb.w r2, [r3, #681] ; 0x2a9
return HAL_ERROR;
8002562: 2301 movs r3, #1
8002564: e00d b.n 8002582 <HAL_PCD_Init+0x20e>
}
hpcd->USB_Address = 0U;
8002566: 687b ldr r3, [r7, #4]
8002568: 2200 movs r2, #0
800256a: f883 2024 strb.w r2, [r3, #36] ; 0x24
hpcd->State = HAL_PCD_STATE_READY;
800256e: 687b ldr r3, [r7, #4]
8002570: 2201 movs r2, #1
8002572: f883 22a9 strb.w r2, [r3, #681] ; 0x2a9
(void)USB_DevDisconnect(hpcd->Instance);
8002576: 687b ldr r3, [r7, #4]
8002578: 681b ldr r3, [r3, #0]
800257a: 4618 mov r0, r3
800257c: f002 fc10 bl 8004da0 <USB_DevDisconnect>
return HAL_OK;
8002580: 2300 movs r3, #0
}
8002582: 4618 mov r0, r3
8002584: 3714 adds r7, #20
8002586: 46bd mov sp, r7
8002588: bdf0 pop {r4, r5, r6, r7, pc}
...
0800258c <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
800258c: b580 push {r7, lr}
800258e: b086 sub sp, #24
8002590: af00 add r7, sp, #0
8002592: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
8002594: 687b ldr r3, [r7, #4]
8002596: 2b00 cmp r3, #0
8002598: d101 bne.n 800259e <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
800259a: 2301 movs r3, #1
800259c: e272 b.n 8002a84 <HAL_RCC_OscConfig+0x4f8>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
800259e: 687b ldr r3, [r7, #4]
80025a0: 681b ldr r3, [r3, #0]
80025a2: f003 0301 and.w r3, r3, #1
80025a6: 2b00 cmp r3, #0
80025a8: f000 8087 beq.w 80026ba <HAL_RCC_OscConfig+0x12e>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
80025ac: 4b92 ldr r3, [pc, #584] ; (80027f8 <HAL_RCC_OscConfig+0x26c>)
80025ae: 685b ldr r3, [r3, #4]
80025b0: f003 030c and.w r3, r3, #12
80025b4: 2b04 cmp r3, #4
80025b6: d00c beq.n 80025d2 <HAL_RCC_OscConfig+0x46>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
80025b8: 4b8f ldr r3, [pc, #572] ; (80027f8 <HAL_RCC_OscConfig+0x26c>)
80025ba: 685b ldr r3, [r3, #4]
80025bc: f003 030c and.w r3, r3, #12
80025c0: 2b08 cmp r3, #8
80025c2: d112 bne.n 80025ea <HAL_RCC_OscConfig+0x5e>
80025c4: 4b8c ldr r3, [pc, #560] ; (80027f8 <HAL_RCC_OscConfig+0x26c>)
80025c6: 685b ldr r3, [r3, #4]
80025c8: f403 3380 and.w r3, r3, #65536 ; 0x10000
80025cc: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
80025d0: d10b bne.n 80025ea <HAL_RCC_OscConfig+0x5e>
{
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80025d2: 4b89 ldr r3, [pc, #548] ; (80027f8 <HAL_RCC_OscConfig+0x26c>)
80025d4: 681b ldr r3, [r3, #0]
80025d6: f403 3300 and.w r3, r3, #131072 ; 0x20000
80025da: 2b00 cmp r3, #0
80025dc: d06c beq.n 80026b8 <HAL_RCC_OscConfig+0x12c>
80025de: 687b ldr r3, [r7, #4]
80025e0: 685b ldr r3, [r3, #4]
80025e2: 2b00 cmp r3, #0
80025e4: d168 bne.n 80026b8 <HAL_RCC_OscConfig+0x12c>
{
return HAL_ERROR;
80025e6: 2301 movs r3, #1
80025e8: e24c b.n 8002a84 <HAL_RCC_OscConfig+0x4f8>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
80025ea: 687b ldr r3, [r7, #4]
80025ec: 685b ldr r3, [r3, #4]
80025ee: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
80025f2: d106 bne.n 8002602 <HAL_RCC_OscConfig+0x76>
80025f4: 4b80 ldr r3, [pc, #512] ; (80027f8 <HAL_RCC_OscConfig+0x26c>)
80025f6: 681b ldr r3, [r3, #0]
80025f8: 4a7f ldr r2, [pc, #508] ; (80027f8 <HAL_RCC_OscConfig+0x26c>)
80025fa: f443 3380 orr.w r3, r3, #65536 ; 0x10000
80025fe: 6013 str r3, [r2, #0]
8002600: e02e b.n 8002660 <HAL_RCC_OscConfig+0xd4>
8002602: 687b ldr r3, [r7, #4]
8002604: 685b ldr r3, [r3, #4]
8002606: 2b00 cmp r3, #0
8002608: d10c bne.n 8002624 <HAL_RCC_OscConfig+0x98>
800260a: 4b7b ldr r3, [pc, #492] ; (80027f8 <HAL_RCC_OscConfig+0x26c>)
800260c: 681b ldr r3, [r3, #0]
800260e: 4a7a ldr r2, [pc, #488] ; (80027f8 <HAL_RCC_OscConfig+0x26c>)
8002610: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8002614: 6013 str r3, [r2, #0]
8002616: 4b78 ldr r3, [pc, #480] ; (80027f8 <HAL_RCC_OscConfig+0x26c>)
8002618: 681b ldr r3, [r3, #0]
800261a: 4a77 ldr r2, [pc, #476] ; (80027f8 <HAL_RCC_OscConfig+0x26c>)
800261c: f423 2380 bic.w r3, r3, #262144 ; 0x40000
8002620: 6013 str r3, [r2, #0]
8002622: e01d b.n 8002660 <HAL_RCC_OscConfig+0xd4>
8002624: 687b ldr r3, [r7, #4]
8002626: 685b ldr r3, [r3, #4]
8002628: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
800262c: d10c bne.n 8002648 <HAL_RCC_OscConfig+0xbc>
800262e: 4b72 ldr r3, [pc, #456] ; (80027f8 <HAL_RCC_OscConfig+0x26c>)
8002630: 681b ldr r3, [r3, #0]
8002632: 4a71 ldr r2, [pc, #452] ; (80027f8 <HAL_RCC_OscConfig+0x26c>)
8002634: f443 2380 orr.w r3, r3, #262144 ; 0x40000
8002638: 6013 str r3, [r2, #0]
800263a: 4b6f ldr r3, [pc, #444] ; (80027f8 <HAL_RCC_OscConfig+0x26c>)
800263c: 681b ldr r3, [r3, #0]
800263e: 4a6e ldr r2, [pc, #440] ; (80027f8 <HAL_RCC_OscConfig+0x26c>)
8002640: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8002644: 6013 str r3, [r2, #0]
8002646: e00b b.n 8002660 <HAL_RCC_OscConfig+0xd4>
8002648: 4b6b ldr r3, [pc, #428] ; (80027f8 <HAL_RCC_OscConfig+0x26c>)
800264a: 681b ldr r3, [r3, #0]
800264c: 4a6a ldr r2, [pc, #424] ; (80027f8 <HAL_RCC_OscConfig+0x26c>)
800264e: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8002652: 6013 str r3, [r2, #0]
8002654: 4b68 ldr r3, [pc, #416] ; (80027f8 <HAL_RCC_OscConfig+0x26c>)
8002656: 681b ldr r3, [r3, #0]
8002658: 4a67 ldr r2, [pc, #412] ; (80027f8 <HAL_RCC_OscConfig+0x26c>)
800265a: f423 2380 bic.w r3, r3, #262144 ; 0x40000
800265e: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8002660: 687b ldr r3, [r7, #4]
8002662: 685b ldr r3, [r3, #4]
8002664: 2b00 cmp r3, #0
8002666: d013 beq.n 8002690 <HAL_RCC_OscConfig+0x104>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8002668: f7ff f90e bl 8001888 <HAL_GetTick>
800266c: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800266e: e008 b.n 8002682 <HAL_RCC_OscConfig+0xf6>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8002670: f7ff f90a bl 8001888 <HAL_GetTick>
8002674: 4602 mov r2, r0
8002676: 693b ldr r3, [r7, #16]
8002678: 1ad3 subs r3, r2, r3
800267a: 2b64 cmp r3, #100 ; 0x64
800267c: d901 bls.n 8002682 <HAL_RCC_OscConfig+0xf6>
{
return HAL_TIMEOUT;
800267e: 2303 movs r3, #3
8002680: e200 b.n 8002a84 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8002682: 4b5d ldr r3, [pc, #372] ; (80027f8 <HAL_RCC_OscConfig+0x26c>)
8002684: 681b ldr r3, [r3, #0]
8002686: f403 3300 and.w r3, r3, #131072 ; 0x20000
800268a: 2b00 cmp r3, #0
800268c: d0f0 beq.n 8002670 <HAL_RCC_OscConfig+0xe4>
800268e: e014 b.n 80026ba <HAL_RCC_OscConfig+0x12e>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8002690: f7ff f8fa bl 8001888 <HAL_GetTick>
8002694: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8002696: e008 b.n 80026aa <HAL_RCC_OscConfig+0x11e>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8002698: f7ff f8f6 bl 8001888 <HAL_GetTick>
800269c: 4602 mov r2, r0
800269e: 693b ldr r3, [r7, #16]
80026a0: 1ad3 subs r3, r2, r3
80026a2: 2b64 cmp r3, #100 ; 0x64
80026a4: d901 bls.n 80026aa <HAL_RCC_OscConfig+0x11e>
{
return HAL_TIMEOUT;
80026a6: 2303 movs r3, #3
80026a8: e1ec b.n 8002a84 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
80026aa: 4b53 ldr r3, [pc, #332] ; (80027f8 <HAL_RCC_OscConfig+0x26c>)
80026ac: 681b ldr r3, [r3, #0]
80026ae: f403 3300 and.w r3, r3, #131072 ; 0x20000
80026b2: 2b00 cmp r3, #0
80026b4: d1f0 bne.n 8002698 <HAL_RCC_OscConfig+0x10c>
80026b6: e000 b.n 80026ba <HAL_RCC_OscConfig+0x12e>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80026b8: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
80026ba: 687b ldr r3, [r7, #4]
80026bc: 681b ldr r3, [r3, #0]
80026be: f003 0302 and.w r3, r3, #2
80026c2: 2b00 cmp r3, #0
80026c4: d063 beq.n 800278e <HAL_RCC_OscConfig+0x202>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
80026c6: 4b4c ldr r3, [pc, #304] ; (80027f8 <HAL_RCC_OscConfig+0x26c>)
80026c8: 685b ldr r3, [r3, #4]
80026ca: f003 030c and.w r3, r3, #12
80026ce: 2b00 cmp r3, #0
80026d0: d00b beq.n 80026ea <HAL_RCC_OscConfig+0x15e>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
80026d2: 4b49 ldr r3, [pc, #292] ; (80027f8 <HAL_RCC_OscConfig+0x26c>)
80026d4: 685b ldr r3, [r3, #4]
80026d6: f003 030c and.w r3, r3, #12
80026da: 2b08 cmp r3, #8
80026dc: d11c bne.n 8002718 <HAL_RCC_OscConfig+0x18c>
80026de: 4b46 ldr r3, [pc, #280] ; (80027f8 <HAL_RCC_OscConfig+0x26c>)
80026e0: 685b ldr r3, [r3, #4]
80026e2: f403 3380 and.w r3, r3, #65536 ; 0x10000
80026e6: 2b00 cmp r3, #0
80026e8: d116 bne.n 8002718 <HAL_RCC_OscConfig+0x18c>
{
/* When HSI is used as system clock it will not disabled */
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
80026ea: 4b43 ldr r3, [pc, #268] ; (80027f8 <HAL_RCC_OscConfig+0x26c>)
80026ec: 681b ldr r3, [r3, #0]
80026ee: f003 0302 and.w r3, r3, #2
80026f2: 2b00 cmp r3, #0
80026f4: d005 beq.n 8002702 <HAL_RCC_OscConfig+0x176>
80026f6: 687b ldr r3, [r7, #4]
80026f8: 691b ldr r3, [r3, #16]
80026fa: 2b01 cmp r3, #1
80026fc: d001 beq.n 8002702 <HAL_RCC_OscConfig+0x176>
{
return HAL_ERROR;
80026fe: 2301 movs r3, #1
8002700: e1c0 b.n 8002a84 <HAL_RCC_OscConfig+0x4f8>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8002702: 4b3d ldr r3, [pc, #244] ; (80027f8 <HAL_RCC_OscConfig+0x26c>)
8002704: 681b ldr r3, [r3, #0]
8002706: f023 02f8 bic.w r2, r3, #248 ; 0xf8
800270a: 687b ldr r3, [r7, #4]
800270c: 695b ldr r3, [r3, #20]
800270e: 00db lsls r3, r3, #3
8002710: 4939 ldr r1, [pc, #228] ; (80027f8 <HAL_RCC_OscConfig+0x26c>)
8002712: 4313 orrs r3, r2
8002714: 600b str r3, [r1, #0]
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8002716: e03a b.n 800278e <HAL_RCC_OscConfig+0x202>
}
}
else
{
/* Check the HSI State */
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8002718: 687b ldr r3, [r7, #4]
800271a: 691b ldr r3, [r3, #16]
800271c: 2b00 cmp r3, #0
800271e: d020 beq.n 8002762 <HAL_RCC_OscConfig+0x1d6>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8002720: 4b36 ldr r3, [pc, #216] ; (80027fc <HAL_RCC_OscConfig+0x270>)
8002722: 2201 movs r2, #1
8002724: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002726: f7ff f8af bl 8001888 <HAL_GetTick>
800272a: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
800272c: e008 b.n 8002740 <HAL_RCC_OscConfig+0x1b4>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
800272e: f7ff f8ab bl 8001888 <HAL_GetTick>
8002732: 4602 mov r2, r0
8002734: 693b ldr r3, [r7, #16]
8002736: 1ad3 subs r3, r2, r3
8002738: 2b02 cmp r3, #2
800273a: d901 bls.n 8002740 <HAL_RCC_OscConfig+0x1b4>
{
return HAL_TIMEOUT;
800273c: 2303 movs r3, #3
800273e: e1a1 b.n 8002a84 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8002740: 4b2d ldr r3, [pc, #180] ; (80027f8 <HAL_RCC_OscConfig+0x26c>)
8002742: 681b ldr r3, [r3, #0]
8002744: f003 0302 and.w r3, r3, #2
8002748: 2b00 cmp r3, #0
800274a: d0f0 beq.n 800272e <HAL_RCC_OscConfig+0x1a2>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
800274c: 4b2a ldr r3, [pc, #168] ; (80027f8 <HAL_RCC_OscConfig+0x26c>)
800274e: 681b ldr r3, [r3, #0]
8002750: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8002754: 687b ldr r3, [r7, #4]
8002756: 695b ldr r3, [r3, #20]
8002758: 00db lsls r3, r3, #3
800275a: 4927 ldr r1, [pc, #156] ; (80027f8 <HAL_RCC_OscConfig+0x26c>)
800275c: 4313 orrs r3, r2
800275e: 600b str r3, [r1, #0]
8002760: e015 b.n 800278e <HAL_RCC_OscConfig+0x202>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8002762: 4b26 ldr r3, [pc, #152] ; (80027fc <HAL_RCC_OscConfig+0x270>)
8002764: 2200 movs r2, #0
8002766: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002768: f7ff f88e bl 8001888 <HAL_GetTick>
800276c: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
800276e: e008 b.n 8002782 <HAL_RCC_OscConfig+0x1f6>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8002770: f7ff f88a bl 8001888 <HAL_GetTick>
8002774: 4602 mov r2, r0
8002776: 693b ldr r3, [r7, #16]
8002778: 1ad3 subs r3, r2, r3
800277a: 2b02 cmp r3, #2
800277c: d901 bls.n 8002782 <HAL_RCC_OscConfig+0x1f6>
{
return HAL_TIMEOUT;
800277e: 2303 movs r3, #3
8002780: e180 b.n 8002a84 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8002782: 4b1d ldr r3, [pc, #116] ; (80027f8 <HAL_RCC_OscConfig+0x26c>)
8002784: 681b ldr r3, [r3, #0]
8002786: f003 0302 and.w r3, r3, #2
800278a: 2b00 cmp r3, #0
800278c: d1f0 bne.n 8002770 <HAL_RCC_OscConfig+0x1e4>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
800278e: 687b ldr r3, [r7, #4]
8002790: 681b ldr r3, [r3, #0]
8002792: f003 0308 and.w r3, r3, #8
8002796: 2b00 cmp r3, #0
8002798: d03a beq.n 8002810 <HAL_RCC_OscConfig+0x284>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
800279a: 687b ldr r3, [r7, #4]
800279c: 699b ldr r3, [r3, #24]
800279e: 2b00 cmp r3, #0
80027a0: d019 beq.n 80027d6 <HAL_RCC_OscConfig+0x24a>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
80027a2: 4b17 ldr r3, [pc, #92] ; (8002800 <HAL_RCC_OscConfig+0x274>)
80027a4: 2201 movs r2, #1
80027a6: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80027a8: f7ff f86e bl 8001888 <HAL_GetTick>
80027ac: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
80027ae: e008 b.n 80027c2 <HAL_RCC_OscConfig+0x236>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
80027b0: f7ff f86a bl 8001888 <HAL_GetTick>
80027b4: 4602 mov r2, r0
80027b6: 693b ldr r3, [r7, #16]
80027b8: 1ad3 subs r3, r2, r3
80027ba: 2b02 cmp r3, #2
80027bc: d901 bls.n 80027c2 <HAL_RCC_OscConfig+0x236>
{
return HAL_TIMEOUT;
80027be: 2303 movs r3, #3
80027c0: e160 b.n 8002a84 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
80027c2: 4b0d ldr r3, [pc, #52] ; (80027f8 <HAL_RCC_OscConfig+0x26c>)
80027c4: 6a5b ldr r3, [r3, #36] ; 0x24
80027c6: f003 0302 and.w r3, r3, #2
80027ca: 2b00 cmp r3, #0
80027cc: d0f0 beq.n 80027b0 <HAL_RCC_OscConfig+0x224>
}
}
/* To have a fully stabilized clock in the specified range, a software delay of 1ms
should be added.*/
RCC_Delay(1);
80027ce: 2001 movs r0, #1
80027d0: f000 fad8 bl 8002d84 <RCC_Delay>
80027d4: e01c b.n 8002810 <HAL_RCC_OscConfig+0x284>
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
80027d6: 4b0a ldr r3, [pc, #40] ; (8002800 <HAL_RCC_OscConfig+0x274>)
80027d8: 2200 movs r2, #0
80027da: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80027dc: f7ff f854 bl 8001888 <HAL_GetTick>
80027e0: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
80027e2: e00f b.n 8002804 <HAL_RCC_OscConfig+0x278>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
80027e4: f7ff f850 bl 8001888 <HAL_GetTick>
80027e8: 4602 mov r2, r0
80027ea: 693b ldr r3, [r7, #16]
80027ec: 1ad3 subs r3, r2, r3
80027ee: 2b02 cmp r3, #2
80027f0: d908 bls.n 8002804 <HAL_RCC_OscConfig+0x278>
{
return HAL_TIMEOUT;
80027f2: 2303 movs r3, #3
80027f4: e146 b.n 8002a84 <HAL_RCC_OscConfig+0x4f8>
80027f6: bf00 nop
80027f8: 40021000 .word 0x40021000
80027fc: 42420000 .word 0x42420000
8002800: 42420480 .word 0x42420480
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8002804: 4b92 ldr r3, [pc, #584] ; (8002a50 <HAL_RCC_OscConfig+0x4c4>)
8002806: 6a5b ldr r3, [r3, #36] ; 0x24
8002808: f003 0302 and.w r3, r3, #2
800280c: 2b00 cmp r3, #0
800280e: d1e9 bne.n 80027e4 <HAL_RCC_OscConfig+0x258>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8002810: 687b ldr r3, [r7, #4]
8002812: 681b ldr r3, [r3, #0]
8002814: f003 0304 and.w r3, r3, #4
8002818: 2b00 cmp r3, #0
800281a: f000 80a6 beq.w 800296a <HAL_RCC_OscConfig+0x3de>
{
FlagStatus pwrclkchanged = RESET;
800281e: 2300 movs r3, #0
8002820: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
8002822: 4b8b ldr r3, [pc, #556] ; (8002a50 <HAL_RCC_OscConfig+0x4c4>)
8002824: 69db ldr r3, [r3, #28]
8002826: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
800282a: 2b00 cmp r3, #0
800282c: d10d bne.n 800284a <HAL_RCC_OscConfig+0x2be>
{
__HAL_RCC_PWR_CLK_ENABLE();
800282e: 4b88 ldr r3, [pc, #544] ; (8002a50 <HAL_RCC_OscConfig+0x4c4>)
8002830: 69db ldr r3, [r3, #28]
8002832: 4a87 ldr r2, [pc, #540] ; (8002a50 <HAL_RCC_OscConfig+0x4c4>)
8002834: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8002838: 61d3 str r3, [r2, #28]
800283a: 4b85 ldr r3, [pc, #532] ; (8002a50 <HAL_RCC_OscConfig+0x4c4>)
800283c: 69db ldr r3, [r3, #28]
800283e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8002842: 60bb str r3, [r7, #8]
8002844: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8002846: 2301 movs r3, #1
8002848: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
800284a: 4b82 ldr r3, [pc, #520] ; (8002a54 <HAL_RCC_OscConfig+0x4c8>)
800284c: 681b ldr r3, [r3, #0]
800284e: f403 7380 and.w r3, r3, #256 ; 0x100
8002852: 2b00 cmp r3, #0
8002854: d118 bne.n 8002888 <HAL_RCC_OscConfig+0x2fc>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8002856: 4b7f ldr r3, [pc, #508] ; (8002a54 <HAL_RCC_OscConfig+0x4c8>)
8002858: 681b ldr r3, [r3, #0]
800285a: 4a7e ldr r2, [pc, #504] ; (8002a54 <HAL_RCC_OscConfig+0x4c8>)
800285c: f443 7380 orr.w r3, r3, #256 ; 0x100
8002860: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8002862: f7ff f811 bl 8001888 <HAL_GetTick>
8002866: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8002868: e008 b.n 800287c <HAL_RCC_OscConfig+0x2f0>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
800286a: f7ff f80d bl 8001888 <HAL_GetTick>
800286e: 4602 mov r2, r0
8002870: 693b ldr r3, [r7, #16]
8002872: 1ad3 subs r3, r2, r3
8002874: 2b64 cmp r3, #100 ; 0x64
8002876: d901 bls.n 800287c <HAL_RCC_OscConfig+0x2f0>
{
return HAL_TIMEOUT;
8002878: 2303 movs r3, #3
800287a: e103 b.n 8002a84 <HAL_RCC_OscConfig+0x4f8>
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
800287c: 4b75 ldr r3, [pc, #468] ; (8002a54 <HAL_RCC_OscConfig+0x4c8>)
800287e: 681b ldr r3, [r3, #0]
8002880: f403 7380 and.w r3, r3, #256 ; 0x100
8002884: 2b00 cmp r3, #0
8002886: d0f0 beq.n 800286a <HAL_RCC_OscConfig+0x2de>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8002888: 687b ldr r3, [r7, #4]
800288a: 68db ldr r3, [r3, #12]
800288c: 2b01 cmp r3, #1
800288e: d106 bne.n 800289e <HAL_RCC_OscConfig+0x312>
8002890: 4b6f ldr r3, [pc, #444] ; (8002a50 <HAL_RCC_OscConfig+0x4c4>)
8002892: 6a1b ldr r3, [r3, #32]
8002894: 4a6e ldr r2, [pc, #440] ; (8002a50 <HAL_RCC_OscConfig+0x4c4>)
8002896: f043 0301 orr.w r3, r3, #1
800289a: 6213 str r3, [r2, #32]
800289c: e02d b.n 80028fa <HAL_RCC_OscConfig+0x36e>
800289e: 687b ldr r3, [r7, #4]
80028a0: 68db ldr r3, [r3, #12]
80028a2: 2b00 cmp r3, #0
80028a4: d10c bne.n 80028c0 <HAL_RCC_OscConfig+0x334>
80028a6: 4b6a ldr r3, [pc, #424] ; (8002a50 <HAL_RCC_OscConfig+0x4c4>)
80028a8: 6a1b ldr r3, [r3, #32]
80028aa: 4a69 ldr r2, [pc, #420] ; (8002a50 <HAL_RCC_OscConfig+0x4c4>)
80028ac: f023 0301 bic.w r3, r3, #1
80028b0: 6213 str r3, [r2, #32]
80028b2: 4b67 ldr r3, [pc, #412] ; (8002a50 <HAL_RCC_OscConfig+0x4c4>)
80028b4: 6a1b ldr r3, [r3, #32]
80028b6: 4a66 ldr r2, [pc, #408] ; (8002a50 <HAL_RCC_OscConfig+0x4c4>)
80028b8: f023 0304 bic.w r3, r3, #4
80028bc: 6213 str r3, [r2, #32]
80028be: e01c b.n 80028fa <HAL_RCC_OscConfig+0x36e>
80028c0: 687b ldr r3, [r7, #4]
80028c2: 68db ldr r3, [r3, #12]
80028c4: 2b05 cmp r3, #5
80028c6: d10c bne.n 80028e2 <HAL_RCC_OscConfig+0x356>
80028c8: 4b61 ldr r3, [pc, #388] ; (8002a50 <HAL_RCC_OscConfig+0x4c4>)
80028ca: 6a1b ldr r3, [r3, #32]
80028cc: 4a60 ldr r2, [pc, #384] ; (8002a50 <HAL_RCC_OscConfig+0x4c4>)
80028ce: f043 0304 orr.w r3, r3, #4
80028d2: 6213 str r3, [r2, #32]
80028d4: 4b5e ldr r3, [pc, #376] ; (8002a50 <HAL_RCC_OscConfig+0x4c4>)
80028d6: 6a1b ldr r3, [r3, #32]
80028d8: 4a5d ldr r2, [pc, #372] ; (8002a50 <HAL_RCC_OscConfig+0x4c4>)
80028da: f043 0301 orr.w r3, r3, #1
80028de: 6213 str r3, [r2, #32]
80028e0: e00b b.n 80028fa <HAL_RCC_OscConfig+0x36e>
80028e2: 4b5b ldr r3, [pc, #364] ; (8002a50 <HAL_RCC_OscConfig+0x4c4>)
80028e4: 6a1b ldr r3, [r3, #32]
80028e6: 4a5a ldr r2, [pc, #360] ; (8002a50 <HAL_RCC_OscConfig+0x4c4>)
80028e8: f023 0301 bic.w r3, r3, #1
80028ec: 6213 str r3, [r2, #32]
80028ee: 4b58 ldr r3, [pc, #352] ; (8002a50 <HAL_RCC_OscConfig+0x4c4>)
80028f0: 6a1b ldr r3, [r3, #32]
80028f2: 4a57 ldr r2, [pc, #348] ; (8002a50 <HAL_RCC_OscConfig+0x4c4>)
80028f4: f023 0304 bic.w r3, r3, #4
80028f8: 6213 str r3, [r2, #32]
/* Check the LSE State */
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
80028fa: 687b ldr r3, [r7, #4]
80028fc: 68db ldr r3, [r3, #12]
80028fe: 2b00 cmp r3, #0
8002900: d015 beq.n 800292e <HAL_RCC_OscConfig+0x3a2>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8002902: f7fe ffc1 bl 8001888 <HAL_GetTick>
8002906: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8002908: e00a b.n 8002920 <HAL_RCC_OscConfig+0x394>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
800290a: f7fe ffbd bl 8001888 <HAL_GetTick>
800290e: 4602 mov r2, r0
8002910: 693b ldr r3, [r7, #16]
8002912: 1ad3 subs r3, r2, r3
8002914: f241 3288 movw r2, #5000 ; 0x1388
8002918: 4293 cmp r3, r2
800291a: d901 bls.n 8002920 <HAL_RCC_OscConfig+0x394>
{
return HAL_TIMEOUT;
800291c: 2303 movs r3, #3
800291e: e0b1 b.n 8002a84 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8002920: 4b4b ldr r3, [pc, #300] ; (8002a50 <HAL_RCC_OscConfig+0x4c4>)
8002922: 6a1b ldr r3, [r3, #32]
8002924: f003 0302 and.w r3, r3, #2
8002928: 2b00 cmp r3, #0
800292a: d0ee beq.n 800290a <HAL_RCC_OscConfig+0x37e>
800292c: e014 b.n 8002958 <HAL_RCC_OscConfig+0x3cc>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800292e: f7fe ffab bl 8001888 <HAL_GetTick>
8002932: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8002934: e00a b.n 800294c <HAL_RCC_OscConfig+0x3c0>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8002936: f7fe ffa7 bl 8001888 <HAL_GetTick>
800293a: 4602 mov r2, r0
800293c: 693b ldr r3, [r7, #16]
800293e: 1ad3 subs r3, r2, r3
8002940: f241 3288 movw r2, #5000 ; 0x1388
8002944: 4293 cmp r3, r2
8002946: d901 bls.n 800294c <HAL_RCC_OscConfig+0x3c0>
{
return HAL_TIMEOUT;
8002948: 2303 movs r3, #3
800294a: e09b b.n 8002a84 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
800294c: 4b40 ldr r3, [pc, #256] ; (8002a50 <HAL_RCC_OscConfig+0x4c4>)
800294e: 6a1b ldr r3, [r3, #32]
8002950: f003 0302 and.w r3, r3, #2
8002954: 2b00 cmp r3, #0
8002956: d1ee bne.n 8002936 <HAL_RCC_OscConfig+0x3aa>
}
}
}
/* Require to disable power clock if necessary */
if (pwrclkchanged == SET)
8002958: 7dfb ldrb r3, [r7, #23]
800295a: 2b01 cmp r3, #1
800295c: d105 bne.n 800296a <HAL_RCC_OscConfig+0x3de>
{
__HAL_RCC_PWR_CLK_DISABLE();
800295e: 4b3c ldr r3, [pc, #240] ; (8002a50 <HAL_RCC_OscConfig+0x4c4>)
8002960: 69db ldr r3, [r3, #28]
8002962: 4a3b ldr r2, [pc, #236] ; (8002a50 <HAL_RCC_OscConfig+0x4c4>)
8002964: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
8002968: 61d3 str r3, [r2, #28]
#endif /* RCC_CR_PLL2ON */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
800296a: 687b ldr r3, [r7, #4]
800296c: 69db ldr r3, [r3, #28]
800296e: 2b00 cmp r3, #0
8002970: f000 8087 beq.w 8002a82 <HAL_RCC_OscConfig+0x4f6>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8002974: 4b36 ldr r3, [pc, #216] ; (8002a50 <HAL_RCC_OscConfig+0x4c4>)
8002976: 685b ldr r3, [r3, #4]
8002978: f003 030c and.w r3, r3, #12
800297c: 2b08 cmp r3, #8
800297e: d061 beq.n 8002a44 <HAL_RCC_OscConfig+0x4b8>
{
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8002980: 687b ldr r3, [r7, #4]
8002982: 69db ldr r3, [r3, #28]
8002984: 2b02 cmp r3, #2
8002986: d146 bne.n 8002a16 <HAL_RCC_OscConfig+0x48a>
/* Check the parameters */
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8002988: 4b33 ldr r3, [pc, #204] ; (8002a58 <HAL_RCC_OscConfig+0x4cc>)
800298a: 2200 movs r2, #0
800298c: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800298e: f7fe ff7b bl 8001888 <HAL_GetTick>
8002992: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8002994: e008 b.n 80029a8 <HAL_RCC_OscConfig+0x41c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8002996: f7fe ff77 bl 8001888 <HAL_GetTick>
800299a: 4602 mov r2, r0
800299c: 693b ldr r3, [r7, #16]
800299e: 1ad3 subs r3, r2, r3
80029a0: 2b02 cmp r3, #2
80029a2: d901 bls.n 80029a8 <HAL_RCC_OscConfig+0x41c>
{
return HAL_TIMEOUT;
80029a4: 2303 movs r3, #3
80029a6: e06d b.n 8002a84 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80029a8: 4b29 ldr r3, [pc, #164] ; (8002a50 <HAL_RCC_OscConfig+0x4c4>)
80029aa: 681b ldr r3, [r3, #0]
80029ac: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
80029b0: 2b00 cmp r3, #0
80029b2: d1f0 bne.n 8002996 <HAL_RCC_OscConfig+0x40a>
}
}
/* Configure the HSE prediv factor --------------------------------*/
/* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
80029b4: 687b ldr r3, [r7, #4]
80029b6: 6a1b ldr r3, [r3, #32]
80029b8: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
80029bc: d108 bne.n 80029d0 <HAL_RCC_OscConfig+0x444>
/* Set PREDIV1 source */
SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
#endif /* RCC_CFGR2_PREDIV1SRC */
/* Set PREDIV1 Value */
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
80029be: 4b24 ldr r3, [pc, #144] ; (8002a50 <HAL_RCC_OscConfig+0x4c4>)
80029c0: 685b ldr r3, [r3, #4]
80029c2: f423 3200 bic.w r2, r3, #131072 ; 0x20000
80029c6: 687b ldr r3, [r7, #4]
80029c8: 689b ldr r3, [r3, #8]
80029ca: 4921 ldr r1, [pc, #132] ; (8002a50 <HAL_RCC_OscConfig+0x4c4>)
80029cc: 4313 orrs r3, r2
80029ce: 604b str r3, [r1, #4]
}
/* Configure the main PLL clock source and multiplication factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
80029d0: 4b1f ldr r3, [pc, #124] ; (8002a50 <HAL_RCC_OscConfig+0x4c4>)
80029d2: 685b ldr r3, [r3, #4]
80029d4: f423 1274 bic.w r2, r3, #3997696 ; 0x3d0000
80029d8: 687b ldr r3, [r7, #4]
80029da: 6a19 ldr r1, [r3, #32]
80029dc: 687b ldr r3, [r7, #4]
80029de: 6a5b ldr r3, [r3, #36] ; 0x24
80029e0: 430b orrs r3, r1
80029e2: 491b ldr r1, [pc, #108] ; (8002a50 <HAL_RCC_OscConfig+0x4c4>)
80029e4: 4313 orrs r3, r2
80029e6: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLMUL);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
80029e8: 4b1b ldr r3, [pc, #108] ; (8002a58 <HAL_RCC_OscConfig+0x4cc>)
80029ea: 2201 movs r2, #1
80029ec: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80029ee: f7fe ff4b bl 8001888 <HAL_GetTick>
80029f2: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
80029f4: e008 b.n 8002a08 <HAL_RCC_OscConfig+0x47c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80029f6: f7fe ff47 bl 8001888 <HAL_GetTick>
80029fa: 4602 mov r2, r0
80029fc: 693b ldr r3, [r7, #16]
80029fe: 1ad3 subs r3, r2, r3
8002a00: 2b02 cmp r3, #2
8002a02: d901 bls.n 8002a08 <HAL_RCC_OscConfig+0x47c>
{
return HAL_TIMEOUT;
8002a04: 2303 movs r3, #3
8002a06: e03d b.n 8002a84 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8002a08: 4b11 ldr r3, [pc, #68] ; (8002a50 <HAL_RCC_OscConfig+0x4c4>)
8002a0a: 681b ldr r3, [r3, #0]
8002a0c: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8002a10: 2b00 cmp r3, #0
8002a12: d0f0 beq.n 80029f6 <HAL_RCC_OscConfig+0x46a>
8002a14: e035 b.n 8002a82 <HAL_RCC_OscConfig+0x4f6>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8002a16: 4b10 ldr r3, [pc, #64] ; (8002a58 <HAL_RCC_OscConfig+0x4cc>)
8002a18: 2200 movs r2, #0
8002a1a: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002a1c: f7fe ff34 bl 8001888 <HAL_GetTick>
8002a20: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8002a22: e008 b.n 8002a36 <HAL_RCC_OscConfig+0x4aa>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8002a24: f7fe ff30 bl 8001888 <HAL_GetTick>
8002a28: 4602 mov r2, r0
8002a2a: 693b ldr r3, [r7, #16]
8002a2c: 1ad3 subs r3, r2, r3
8002a2e: 2b02 cmp r3, #2
8002a30: d901 bls.n 8002a36 <HAL_RCC_OscConfig+0x4aa>
{
return HAL_TIMEOUT;
8002a32: 2303 movs r3, #3
8002a34: e026 b.n 8002a84 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8002a36: 4b06 ldr r3, [pc, #24] ; (8002a50 <HAL_RCC_OscConfig+0x4c4>)
8002a38: 681b ldr r3, [r3, #0]
8002a3a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8002a3e: 2b00 cmp r3, #0
8002a40: d1f0 bne.n 8002a24 <HAL_RCC_OscConfig+0x498>
8002a42: e01e b.n 8002a82 <HAL_RCC_OscConfig+0x4f6>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8002a44: 687b ldr r3, [r7, #4]
8002a46: 69db ldr r3, [r3, #28]
8002a48: 2b01 cmp r3, #1
8002a4a: d107 bne.n 8002a5c <HAL_RCC_OscConfig+0x4d0>
{
return HAL_ERROR;
8002a4c: 2301 movs r3, #1
8002a4e: e019 b.n 8002a84 <HAL_RCC_OscConfig+0x4f8>
8002a50: 40021000 .word 0x40021000
8002a54: 40007000 .word 0x40007000
8002a58: 42420060 .word 0x42420060
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
8002a5c: 4b0b ldr r3, [pc, #44] ; (8002a8c <HAL_RCC_OscConfig+0x500>)
8002a5e: 685b ldr r3, [r3, #4]
8002a60: 60fb str r3, [r7, #12]
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8002a62: 68fb ldr r3, [r7, #12]
8002a64: f403 3280 and.w r2, r3, #65536 ; 0x10000
8002a68: 687b ldr r3, [r7, #4]
8002a6a: 6a1b ldr r3, [r3, #32]
8002a6c: 429a cmp r2, r3
8002a6e: d106 bne.n 8002a7e <HAL_RCC_OscConfig+0x4f2>
(READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
8002a70: 68fb ldr r3, [r7, #12]
8002a72: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000
8002a76: 687b ldr r3, [r7, #4]
8002a78: 6a5b ldr r3, [r3, #36] ; 0x24
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8002a7a: 429a cmp r2, r3
8002a7c: d001 beq.n 8002a82 <HAL_RCC_OscConfig+0x4f6>
{
return HAL_ERROR;
8002a7e: 2301 movs r3, #1
8002a80: e000 b.n 8002a84 <HAL_RCC_OscConfig+0x4f8>
}
}
}
}
return HAL_OK;
8002a82: 2300 movs r3, #0
}
8002a84: 4618 mov r0, r3
8002a86: 3718 adds r7, #24
8002a88: 46bd mov sp, r7
8002a8a: bd80 pop {r7, pc}
8002a8c: 40021000 .word 0x40021000
08002a90 <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8002a90: b580 push {r7, lr}
8002a92: b084 sub sp, #16
8002a94: af00 add r7, sp, #0
8002a96: 6078 str r0, [r7, #4]
8002a98: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
8002a9a: 687b ldr r3, [r7, #4]
8002a9c: 2b00 cmp r3, #0
8002a9e: d101 bne.n 8002aa4 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8002aa0: 2301 movs r3, #1
8002aa2: e0d0 b.n 8002c46 <HAL_RCC_ClockConfig+0x1b6>
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
#if defined(FLASH_ACR_LATENCY)
/* Increasing the number of wait states because of higher CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
8002aa4: 4b6a ldr r3, [pc, #424] ; (8002c50 <HAL_RCC_ClockConfig+0x1c0>)
8002aa6: 681b ldr r3, [r3, #0]
8002aa8: f003 0307 and.w r3, r3, #7
8002aac: 683a ldr r2, [r7, #0]
8002aae: 429a cmp r2, r3
8002ab0: d910 bls.n 8002ad4 <HAL_RCC_ClockConfig+0x44>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8002ab2: 4b67 ldr r3, [pc, #412] ; (8002c50 <HAL_RCC_ClockConfig+0x1c0>)
8002ab4: 681b ldr r3, [r3, #0]
8002ab6: f023 0207 bic.w r2, r3, #7
8002aba: 4965 ldr r1, [pc, #404] ; (8002c50 <HAL_RCC_ClockConfig+0x1c0>)
8002abc: 683b ldr r3, [r7, #0]
8002abe: 4313 orrs r3, r2
8002ac0: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8002ac2: 4b63 ldr r3, [pc, #396] ; (8002c50 <HAL_RCC_ClockConfig+0x1c0>)
8002ac4: 681b ldr r3, [r3, #0]
8002ac6: f003 0307 and.w r3, r3, #7
8002aca: 683a ldr r2, [r7, #0]
8002acc: 429a cmp r2, r3
8002ace: d001 beq.n 8002ad4 <HAL_RCC_ClockConfig+0x44>
{
return HAL_ERROR;
8002ad0: 2301 movs r3, #1
8002ad2: e0b8 b.n 8002c46 <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8002ad4: 687b ldr r3, [r7, #4]
8002ad6: 681b ldr r3, [r3, #0]
8002ad8: f003 0302 and.w r3, r3, #2
8002adc: 2b00 cmp r3, #0
8002ade: d020 beq.n 8002b22 <HAL_RCC_ClockConfig+0x92>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8002ae0: 687b ldr r3, [r7, #4]
8002ae2: 681b ldr r3, [r3, #0]
8002ae4: f003 0304 and.w r3, r3, #4
8002ae8: 2b00 cmp r3, #0
8002aea: d005 beq.n 8002af8 <HAL_RCC_ClockConfig+0x68>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8002aec: 4b59 ldr r3, [pc, #356] ; (8002c54 <HAL_RCC_ClockConfig+0x1c4>)
8002aee: 685b ldr r3, [r3, #4]
8002af0: 4a58 ldr r2, [pc, #352] ; (8002c54 <HAL_RCC_ClockConfig+0x1c4>)
8002af2: f443 63e0 orr.w r3, r3, #1792 ; 0x700
8002af6: 6053 str r3, [r2, #4]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8002af8: 687b ldr r3, [r7, #4]
8002afa: 681b ldr r3, [r3, #0]
8002afc: f003 0308 and.w r3, r3, #8
8002b00: 2b00 cmp r3, #0
8002b02: d005 beq.n 8002b10 <HAL_RCC_ClockConfig+0x80>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
8002b04: 4b53 ldr r3, [pc, #332] ; (8002c54 <HAL_RCC_ClockConfig+0x1c4>)
8002b06: 685b ldr r3, [r3, #4]
8002b08: 4a52 ldr r2, [pc, #328] ; (8002c54 <HAL_RCC_ClockConfig+0x1c4>)
8002b0a: f443 5360 orr.w r3, r3, #14336 ; 0x3800
8002b0e: 6053 str r3, [r2, #4]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8002b10: 4b50 ldr r3, [pc, #320] ; (8002c54 <HAL_RCC_ClockConfig+0x1c4>)
8002b12: 685b ldr r3, [r3, #4]
8002b14: f023 02f0 bic.w r2, r3, #240 ; 0xf0
8002b18: 687b ldr r3, [r7, #4]
8002b1a: 689b ldr r3, [r3, #8]
8002b1c: 494d ldr r1, [pc, #308] ; (8002c54 <HAL_RCC_ClockConfig+0x1c4>)
8002b1e: 4313 orrs r3, r2
8002b20: 604b str r3, [r1, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8002b22: 687b ldr r3, [r7, #4]
8002b24: 681b ldr r3, [r3, #0]
8002b26: f003 0301 and.w r3, r3, #1
8002b2a: 2b00 cmp r3, #0
8002b2c: d040 beq.n 8002bb0 <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8002b2e: 687b ldr r3, [r7, #4]
8002b30: 685b ldr r3, [r3, #4]
8002b32: 2b01 cmp r3, #1
8002b34: d107 bne.n 8002b46 <HAL_RCC_ClockConfig+0xb6>
{
/* Check the HSE ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8002b36: 4b47 ldr r3, [pc, #284] ; (8002c54 <HAL_RCC_ClockConfig+0x1c4>)
8002b38: 681b ldr r3, [r3, #0]
8002b3a: f403 3300 and.w r3, r3, #131072 ; 0x20000
8002b3e: 2b00 cmp r3, #0
8002b40: d115 bne.n 8002b6e <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8002b42: 2301 movs r3, #1
8002b44: e07f b.n 8002c46 <HAL_RCC_ClockConfig+0x1b6>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8002b46: 687b ldr r3, [r7, #4]
8002b48: 685b ldr r3, [r3, #4]
8002b4a: 2b02 cmp r3, #2
8002b4c: d107 bne.n 8002b5e <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8002b4e: 4b41 ldr r3, [pc, #260] ; (8002c54 <HAL_RCC_ClockConfig+0x1c4>)
8002b50: 681b ldr r3, [r3, #0]
8002b52: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8002b56: 2b00 cmp r3, #0
8002b58: d109 bne.n 8002b6e <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8002b5a: 2301 movs r3, #1
8002b5c: e073 b.n 8002c46 <HAL_RCC_ClockConfig+0x1b6>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8002b5e: 4b3d ldr r3, [pc, #244] ; (8002c54 <HAL_RCC_ClockConfig+0x1c4>)
8002b60: 681b ldr r3, [r3, #0]
8002b62: f003 0302 and.w r3, r3, #2
8002b66: 2b00 cmp r3, #0
8002b68: d101 bne.n 8002b6e <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8002b6a: 2301 movs r3, #1
8002b6c: e06b b.n 8002c46 <HAL_RCC_ClockConfig+0x1b6>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8002b6e: 4b39 ldr r3, [pc, #228] ; (8002c54 <HAL_RCC_ClockConfig+0x1c4>)
8002b70: 685b ldr r3, [r3, #4]
8002b72: f023 0203 bic.w r2, r3, #3
8002b76: 687b ldr r3, [r7, #4]
8002b78: 685b ldr r3, [r3, #4]
8002b7a: 4936 ldr r1, [pc, #216] ; (8002c54 <HAL_RCC_ClockConfig+0x1c4>)
8002b7c: 4313 orrs r3, r2
8002b7e: 604b str r3, [r1, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002b80: f7fe fe82 bl 8001888 <HAL_GetTick>
8002b84: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8002b86: e00a b.n 8002b9e <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8002b88: f7fe fe7e bl 8001888 <HAL_GetTick>
8002b8c: 4602 mov r2, r0
8002b8e: 68fb ldr r3, [r7, #12]
8002b90: 1ad3 subs r3, r2, r3
8002b92: f241 3288 movw r2, #5000 ; 0x1388
8002b96: 4293 cmp r3, r2
8002b98: d901 bls.n 8002b9e <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
8002b9a: 2303 movs r3, #3
8002b9c: e053 b.n 8002c46 <HAL_RCC_ClockConfig+0x1b6>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8002b9e: 4b2d ldr r3, [pc, #180] ; (8002c54 <HAL_RCC_ClockConfig+0x1c4>)
8002ba0: 685b ldr r3, [r3, #4]
8002ba2: f003 020c and.w r2, r3, #12
8002ba6: 687b ldr r3, [r7, #4]
8002ba8: 685b ldr r3, [r3, #4]
8002baa: 009b lsls r3, r3, #2
8002bac: 429a cmp r2, r3
8002bae: d1eb bne.n 8002b88 <HAL_RCC_ClockConfig+0xf8>
}
}
#if defined(FLASH_ACR_LATENCY)
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
8002bb0: 4b27 ldr r3, [pc, #156] ; (8002c50 <HAL_RCC_ClockConfig+0x1c0>)
8002bb2: 681b ldr r3, [r3, #0]
8002bb4: f003 0307 and.w r3, r3, #7
8002bb8: 683a ldr r2, [r7, #0]
8002bba: 429a cmp r2, r3
8002bbc: d210 bcs.n 8002be0 <HAL_RCC_ClockConfig+0x150>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8002bbe: 4b24 ldr r3, [pc, #144] ; (8002c50 <HAL_RCC_ClockConfig+0x1c0>)
8002bc0: 681b ldr r3, [r3, #0]
8002bc2: f023 0207 bic.w r2, r3, #7
8002bc6: 4922 ldr r1, [pc, #136] ; (8002c50 <HAL_RCC_ClockConfig+0x1c0>)
8002bc8: 683b ldr r3, [r7, #0]
8002bca: 4313 orrs r3, r2
8002bcc: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8002bce: 4b20 ldr r3, [pc, #128] ; (8002c50 <HAL_RCC_ClockConfig+0x1c0>)
8002bd0: 681b ldr r3, [r3, #0]
8002bd2: f003 0307 and.w r3, r3, #7
8002bd6: 683a ldr r2, [r7, #0]
8002bd8: 429a cmp r2, r3
8002bda: d001 beq.n 8002be0 <HAL_RCC_ClockConfig+0x150>
{
return HAL_ERROR;
8002bdc: 2301 movs r3, #1
8002bde: e032 b.n 8002c46 <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8002be0: 687b ldr r3, [r7, #4]
8002be2: 681b ldr r3, [r3, #0]
8002be4: f003 0304 and.w r3, r3, #4
8002be8: 2b00 cmp r3, #0
8002bea: d008 beq.n 8002bfe <HAL_RCC_ClockConfig+0x16e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8002bec: 4b19 ldr r3, [pc, #100] ; (8002c54 <HAL_RCC_ClockConfig+0x1c4>)
8002bee: 685b ldr r3, [r3, #4]
8002bf0: f423 62e0 bic.w r2, r3, #1792 ; 0x700
8002bf4: 687b ldr r3, [r7, #4]
8002bf6: 68db ldr r3, [r3, #12]
8002bf8: 4916 ldr r1, [pc, #88] ; (8002c54 <HAL_RCC_ClockConfig+0x1c4>)
8002bfa: 4313 orrs r3, r2
8002bfc: 604b str r3, [r1, #4]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8002bfe: 687b ldr r3, [r7, #4]
8002c00: 681b ldr r3, [r3, #0]
8002c02: f003 0308 and.w r3, r3, #8
8002c06: 2b00 cmp r3, #0
8002c08: d009 beq.n 8002c1e <HAL_RCC_ClockConfig+0x18e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
8002c0a: 4b12 ldr r3, [pc, #72] ; (8002c54 <HAL_RCC_ClockConfig+0x1c4>)
8002c0c: 685b ldr r3, [r3, #4]
8002c0e: f423 5260 bic.w r2, r3, #14336 ; 0x3800
8002c12: 687b ldr r3, [r7, #4]
8002c14: 691b ldr r3, [r3, #16]
8002c16: 00db lsls r3, r3, #3
8002c18: 490e ldr r1, [pc, #56] ; (8002c54 <HAL_RCC_ClockConfig+0x1c4>)
8002c1a: 4313 orrs r3, r2
8002c1c: 604b str r3, [r1, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
8002c1e: f000 f821 bl 8002c64 <HAL_RCC_GetSysClockFreq>
8002c22: 4602 mov r2, r0
8002c24: 4b0b ldr r3, [pc, #44] ; (8002c54 <HAL_RCC_ClockConfig+0x1c4>)
8002c26: 685b ldr r3, [r3, #4]
8002c28: 091b lsrs r3, r3, #4
8002c2a: f003 030f and.w r3, r3, #15
8002c2e: 490a ldr r1, [pc, #40] ; (8002c58 <HAL_RCC_ClockConfig+0x1c8>)
8002c30: 5ccb ldrb r3, [r1, r3]
8002c32: fa22 f303 lsr.w r3, r2, r3
8002c36: 4a09 ldr r2, [pc, #36] ; (8002c5c <HAL_RCC_ClockConfig+0x1cc>)
8002c38: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick(uwTickPrio);
8002c3a: 4b09 ldr r3, [pc, #36] ; (8002c60 <HAL_RCC_ClockConfig+0x1d0>)
8002c3c: 681b ldr r3, [r3, #0]
8002c3e: 4618 mov r0, r3
8002c40: f7fe fde0 bl 8001804 <HAL_InitTick>
return HAL_OK;
8002c44: 2300 movs r3, #0
}
8002c46: 4618 mov r0, r3
8002c48: 3710 adds r7, #16
8002c4a: 46bd mov sp, r7
8002c4c: bd80 pop {r7, pc}
8002c4e: bf00 nop
8002c50: 40022000 .word 0x40022000
8002c54: 40021000 .word 0x40021000
8002c58: 08005a30 .word 0x08005a30
8002c5c: 20000000 .word 0x20000000
8002c60: 20000004 .word 0x20000004
08002c64 <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8002c64: b490 push {r4, r7}
8002c66: b08a sub sp, #40 ; 0x28
8002c68: af00 add r7, sp, #0
#if defined(RCC_CFGR2_PREDIV1SRC)
const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
#else
const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
8002c6a: 4b29 ldr r3, [pc, #164] ; (8002d10 <HAL_RCC_GetSysClockFreq+0xac>)
8002c6c: 1d3c adds r4, r7, #4
8002c6e: cb0f ldmia r3, {r0, r1, r2, r3}
8002c70: e884 000f stmia.w r4, {r0, r1, r2, r3}
#if defined(RCC_CFGR2_PREDIV1)
const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
#else
const uint8_t aPredivFactorTable[2] = {1, 2};
8002c74: f240 2301 movw r3, #513 ; 0x201
8002c78: 803b strh r3, [r7, #0]
#endif /*RCC_CFGR2_PREDIV1*/
#endif
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
8002c7a: 2300 movs r3, #0
8002c7c: 61fb str r3, [r7, #28]
8002c7e: 2300 movs r3, #0
8002c80: 61bb str r3, [r7, #24]
8002c82: 2300 movs r3, #0
8002c84: 627b str r3, [r7, #36] ; 0x24
8002c86: 2300 movs r3, #0
8002c88: 617b str r3, [r7, #20]
uint32_t sysclockfreq = 0U;
8002c8a: 2300 movs r3, #0
8002c8c: 623b str r3, [r7, #32]
#if defined(RCC_CFGR2_PREDIV1SRC)
uint32_t prediv2 = 0U, pll2mul = 0U;
#endif /*RCC_CFGR2_PREDIV1SRC*/
tmpreg = RCC->CFGR;
8002c8e: 4b21 ldr r3, [pc, #132] ; (8002d14 <HAL_RCC_GetSysClockFreq+0xb0>)
8002c90: 685b ldr r3, [r3, #4]
8002c92: 61fb str r3, [r7, #28]
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
8002c94: 69fb ldr r3, [r7, #28]
8002c96: f003 030c and.w r3, r3, #12
8002c9a: 2b04 cmp r3, #4
8002c9c: d002 beq.n 8002ca4 <HAL_RCC_GetSysClockFreq+0x40>
8002c9e: 2b08 cmp r3, #8
8002ca0: d003 beq.n 8002caa <HAL_RCC_GetSysClockFreq+0x46>
8002ca2: e02b b.n 8002cfc <HAL_RCC_GetSysClockFreq+0x98>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
8002ca4: 4b1c ldr r3, [pc, #112] ; (8002d18 <HAL_RCC_GetSysClockFreq+0xb4>)
8002ca6: 623b str r3, [r7, #32]
break;
8002ca8: e02b b.n 8002d02 <HAL_RCC_GetSysClockFreq+0x9e>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
8002caa: 69fb ldr r3, [r7, #28]
8002cac: 0c9b lsrs r3, r3, #18
8002cae: f003 030f and.w r3, r3, #15
8002cb2: 3328 adds r3, #40 ; 0x28
8002cb4: 443b add r3, r7
8002cb6: f813 3c24 ldrb.w r3, [r3, #-36]
8002cba: 617b str r3, [r7, #20]
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
8002cbc: 69fb ldr r3, [r7, #28]
8002cbe: f403 3380 and.w r3, r3, #65536 ; 0x10000
8002cc2: 2b00 cmp r3, #0
8002cc4: d012 beq.n 8002cec <HAL_RCC_GetSysClockFreq+0x88>
{
#if defined(RCC_CFGR2_PREDIV1)
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
#else
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
8002cc6: 4b13 ldr r3, [pc, #76] ; (8002d14 <HAL_RCC_GetSysClockFreq+0xb0>)
8002cc8: 685b ldr r3, [r3, #4]
8002cca: 0c5b lsrs r3, r3, #17
8002ccc: f003 0301 and.w r3, r3, #1
8002cd0: 3328 adds r3, #40 ; 0x28
8002cd2: 443b add r3, r7
8002cd4: f813 3c28 ldrb.w r3, [r3, #-40]
8002cd8: 61bb str r3, [r7, #24]
{
pllclk = pllclk / 2;
}
#else
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
8002cda: 697b ldr r3, [r7, #20]
8002cdc: 4a0e ldr r2, [pc, #56] ; (8002d18 <HAL_RCC_GetSysClockFreq+0xb4>)
8002cde: fb03 f202 mul.w r2, r3, r2
8002ce2: 69bb ldr r3, [r7, #24]
8002ce4: fbb2 f3f3 udiv r3, r2, r3
8002ce8: 627b str r3, [r7, #36] ; 0x24
8002cea: e004 b.n 8002cf6 <HAL_RCC_GetSysClockFreq+0x92>
#endif /*RCC_CFGR2_PREDIV1SRC*/
}
else
{
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
8002cec: 697b ldr r3, [r7, #20]
8002cee: 4a0b ldr r2, [pc, #44] ; (8002d1c <HAL_RCC_GetSysClockFreq+0xb8>)
8002cf0: fb02 f303 mul.w r3, r2, r3
8002cf4: 627b str r3, [r7, #36] ; 0x24
}
sysclockfreq = pllclk;
8002cf6: 6a7b ldr r3, [r7, #36] ; 0x24
8002cf8: 623b str r3, [r7, #32]
break;
8002cfa: e002 b.n 8002d02 <HAL_RCC_GetSysClockFreq+0x9e>
}
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
8002cfc: 4b06 ldr r3, [pc, #24] ; (8002d18 <HAL_RCC_GetSysClockFreq+0xb4>)
8002cfe: 623b str r3, [r7, #32]
break;
8002d00: bf00 nop
}
}
return sysclockfreq;
8002d02: 6a3b ldr r3, [r7, #32]
}
8002d04: 4618 mov r0, r3
8002d06: 3728 adds r7, #40 ; 0x28
8002d08: 46bd mov sp, r7
8002d0a: bc90 pop {r4, r7}
8002d0c: 4770 bx lr
8002d0e: bf00 nop
8002d10: 08005a00 .word 0x08005a00
8002d14: 40021000 .word 0x40021000
8002d18: 007a1200 .word 0x007a1200
8002d1c: 003d0900 .word 0x003d0900
08002d20 <HAL_RCC_GetHCLKFreq>:
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8002d20: b480 push {r7}
8002d22: af00 add r7, sp, #0
return SystemCoreClock;
8002d24: 4b02 ldr r3, [pc, #8] ; (8002d30 <HAL_RCC_GetHCLKFreq+0x10>)
8002d26: 681b ldr r3, [r3, #0]
}
8002d28: 4618 mov r0, r3
8002d2a: 46bd mov sp, r7
8002d2c: bc80 pop {r7}
8002d2e: 4770 bx lr
8002d30: 20000000 .word 0x20000000
08002d34 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8002d34: b580 push {r7, lr}
8002d36: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
8002d38: f7ff fff2 bl 8002d20 <HAL_RCC_GetHCLKFreq>
8002d3c: 4602 mov r2, r0
8002d3e: 4b05 ldr r3, [pc, #20] ; (8002d54 <HAL_RCC_GetPCLK1Freq+0x20>)
8002d40: 685b ldr r3, [r3, #4]
8002d42: 0a1b lsrs r3, r3, #8
8002d44: f003 0307 and.w r3, r3, #7
8002d48: 4903 ldr r1, [pc, #12] ; (8002d58 <HAL_RCC_GetPCLK1Freq+0x24>)
8002d4a: 5ccb ldrb r3, [r1, r3]
8002d4c: fa22 f303 lsr.w r3, r2, r3
}
8002d50: 4618 mov r0, r3
8002d52: bd80 pop {r7, pc}
8002d54: 40021000 .word 0x40021000
8002d58: 08005a40 .word 0x08005a40
08002d5c <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
8002d5c: b580 push {r7, lr}
8002d5e: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
8002d60: f7ff ffde bl 8002d20 <HAL_RCC_GetHCLKFreq>
8002d64: 4602 mov r2, r0
8002d66: 4b05 ldr r3, [pc, #20] ; (8002d7c <HAL_RCC_GetPCLK2Freq+0x20>)
8002d68: 685b ldr r3, [r3, #4]
8002d6a: 0adb lsrs r3, r3, #11
8002d6c: f003 0307 and.w r3, r3, #7
8002d70: 4903 ldr r1, [pc, #12] ; (8002d80 <HAL_RCC_GetPCLK2Freq+0x24>)
8002d72: 5ccb ldrb r3, [r1, r3]
8002d74: fa22 f303 lsr.w r3, r2, r3
}
8002d78: 4618 mov r0, r3
8002d7a: bd80 pop {r7, pc}
8002d7c: 40021000 .word 0x40021000
8002d80: 08005a40 .word 0x08005a40
08002d84 <RCC_Delay>:
* @brief This function provides delay (in milliseconds) based on CPU cycles method.
* @param mdelay: specifies the delay time length, in milliseconds.
* @retval None
*/
static void RCC_Delay(uint32_t mdelay)
{
8002d84: b480 push {r7}
8002d86: b085 sub sp, #20
8002d88: af00 add r7, sp, #0
8002d8a: 6078 str r0, [r7, #4]
__IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
8002d8c: 4b0a ldr r3, [pc, #40] ; (8002db8 <RCC_Delay+0x34>)
8002d8e: 681b ldr r3, [r3, #0]
8002d90: 4a0a ldr r2, [pc, #40] ; (8002dbc <RCC_Delay+0x38>)
8002d92: fba2 2303 umull r2, r3, r2, r3
8002d96: 0a5b lsrs r3, r3, #9
8002d98: 687a ldr r2, [r7, #4]
8002d9a: fb02 f303 mul.w r3, r2, r3
8002d9e: 60fb str r3, [r7, #12]
do
{
__NOP();
8002da0: bf00 nop
}
while (Delay --);
8002da2: 68fb ldr r3, [r7, #12]
8002da4: 1e5a subs r2, r3, #1
8002da6: 60fa str r2, [r7, #12]
8002da8: 2b00 cmp r3, #0
8002daa: d1f9 bne.n 8002da0 <RCC_Delay+0x1c>
}
8002dac: bf00 nop
8002dae: bf00 nop
8002db0: 3714 adds r7, #20
8002db2: 46bd mov sp, r7
8002db4: bc80 pop {r7}
8002db6: 4770 bx lr
8002db8: 20000000 .word 0x20000000
8002dbc: 10624dd3 .word 0x10624dd3
08002dc0 <HAL_RCCEx_PeriphCLKConfig>:
* manually disable it.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
8002dc0: b580 push {r7, lr}
8002dc2: b086 sub sp, #24
8002dc4: af00 add r7, sp, #0
8002dc6: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U, temp_reg = 0U;
8002dc8: 2300 movs r3, #0
8002dca: 613b str r3, [r7, #16]
8002dcc: 2300 movs r3, #0
8002dce: 60fb str r3, [r7, #12]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*------------------------------- RTC/LCD Configuration ------------------------*/
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
8002dd0: 687b ldr r3, [r7, #4]
8002dd2: 681b ldr r3, [r3, #0]
8002dd4: f003 0301 and.w r3, r3, #1
8002dd8: 2b00 cmp r3, #0
8002dda: d07d beq.n 8002ed8 <HAL_RCCEx_PeriphCLKConfig+0x118>
{
FlagStatus pwrclkchanged = RESET;
8002ddc: 2300 movs r3, #0
8002dde: 75fb strb r3, [r7, #23]
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* As soon as function is called to change RTC clock source, activation of the
power domain is done. */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
8002de0: 4b4f ldr r3, [pc, #316] ; (8002f20 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8002de2: 69db ldr r3, [r3, #28]
8002de4: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8002de8: 2b00 cmp r3, #0
8002dea: d10d bne.n 8002e08 <HAL_RCCEx_PeriphCLKConfig+0x48>
{
__HAL_RCC_PWR_CLK_ENABLE();
8002dec: 4b4c ldr r3, [pc, #304] ; (8002f20 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8002dee: 69db ldr r3, [r3, #28]
8002df0: 4a4b ldr r2, [pc, #300] ; (8002f20 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8002df2: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8002df6: 61d3 str r3, [r2, #28]
8002df8: 4b49 ldr r3, [pc, #292] ; (8002f20 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8002dfa: 69db ldr r3, [r3, #28]
8002dfc: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8002e00: 60bb str r3, [r7, #8]
8002e02: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8002e04: 2301 movs r3, #1
8002e06: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8002e08: 4b46 ldr r3, [pc, #280] ; (8002f24 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8002e0a: 681b ldr r3, [r3, #0]
8002e0c: f403 7380 and.w r3, r3, #256 ; 0x100
8002e10: 2b00 cmp r3, #0
8002e12: d118 bne.n 8002e46 <HAL_RCCEx_PeriphCLKConfig+0x86>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8002e14: 4b43 ldr r3, [pc, #268] ; (8002f24 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8002e16: 681b ldr r3, [r3, #0]
8002e18: 4a42 ldr r2, [pc, #264] ; (8002f24 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8002e1a: f443 7380 orr.w r3, r3, #256 ; 0x100
8002e1e: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8002e20: f7fe fd32 bl 8001888 <HAL_GetTick>
8002e24: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8002e26: e008 b.n 8002e3a <HAL_RCCEx_PeriphCLKConfig+0x7a>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8002e28: f7fe fd2e bl 8001888 <HAL_GetTick>
8002e2c: 4602 mov r2, r0
8002e2e: 693b ldr r3, [r7, #16]
8002e30: 1ad3 subs r3, r2, r3
8002e32: 2b64 cmp r3, #100 ; 0x64
8002e34: d901 bls.n 8002e3a <HAL_RCCEx_PeriphCLKConfig+0x7a>
{
return HAL_TIMEOUT;
8002e36: 2303 movs r3, #3
8002e38: e06d b.n 8002f16 <HAL_RCCEx_PeriphCLKConfig+0x156>
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8002e3a: 4b3a ldr r3, [pc, #232] ; (8002f24 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8002e3c: 681b ldr r3, [r3, #0]
8002e3e: f403 7380 and.w r3, r3, #256 ; 0x100
8002e42: 2b00 cmp r3, #0
8002e44: d0f0 beq.n 8002e28 <HAL_RCCEx_PeriphCLKConfig+0x68>
}
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
8002e46: 4b36 ldr r3, [pc, #216] ; (8002f20 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8002e48: 6a1b ldr r3, [r3, #32]
8002e4a: f403 7340 and.w r3, r3, #768 ; 0x300
8002e4e: 60fb str r3, [r7, #12]
if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
8002e50: 68fb ldr r3, [r7, #12]
8002e52: 2b00 cmp r3, #0
8002e54: d02e beq.n 8002eb4 <HAL_RCCEx_PeriphCLKConfig+0xf4>
8002e56: 687b ldr r3, [r7, #4]
8002e58: 685b ldr r3, [r3, #4]
8002e5a: f403 7340 and.w r3, r3, #768 ; 0x300
8002e5e: 68fa ldr r2, [r7, #12]
8002e60: 429a cmp r2, r3
8002e62: d027 beq.n 8002eb4 <HAL_RCCEx_PeriphCLKConfig+0xf4>
{
/* Store the content of BDCR register before the reset of Backup Domain */
temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
8002e64: 4b2e ldr r3, [pc, #184] ; (8002f20 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8002e66: 6a1b ldr r3, [r3, #32]
8002e68: f423 7340 bic.w r3, r3, #768 ; 0x300
8002e6c: 60fb str r3, [r7, #12]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
8002e6e: 4b2e ldr r3, [pc, #184] ; (8002f28 <HAL_RCCEx_PeriphCLKConfig+0x168>)
8002e70: 2201 movs r2, #1
8002e72: 601a str r2, [r3, #0]
__HAL_RCC_BACKUPRESET_RELEASE();
8002e74: 4b2c ldr r3, [pc, #176] ; (8002f28 <HAL_RCCEx_PeriphCLKConfig+0x168>)
8002e76: 2200 movs r2, #0
8002e78: 601a str r2, [r3, #0]
/* Restore the Content of BDCR register */
RCC->BDCR = temp_reg;
8002e7a: 4a29 ldr r2, [pc, #164] ; (8002f20 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8002e7c: 68fb ldr r3, [r7, #12]
8002e7e: 6213 str r3, [r2, #32]
/* Wait for LSERDY if LSE was enabled */
if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
8002e80: 68fb ldr r3, [r7, #12]
8002e82: f003 0301 and.w r3, r3, #1
8002e86: 2b00 cmp r3, #0
8002e88: d014 beq.n 8002eb4 <HAL_RCCEx_PeriphCLKConfig+0xf4>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8002e8a: f7fe fcfd bl 8001888 <HAL_GetTick>
8002e8e: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8002e90: e00a b.n 8002ea8 <HAL_RCCEx_PeriphCLKConfig+0xe8>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8002e92: f7fe fcf9 bl 8001888 <HAL_GetTick>
8002e96: 4602 mov r2, r0
8002e98: 693b ldr r3, [r7, #16]
8002e9a: 1ad3 subs r3, r2, r3
8002e9c: f241 3288 movw r2, #5000 ; 0x1388
8002ea0: 4293 cmp r3, r2
8002ea2: d901 bls.n 8002ea8 <HAL_RCCEx_PeriphCLKConfig+0xe8>
{
return HAL_TIMEOUT;
8002ea4: 2303 movs r3, #3
8002ea6: e036 b.n 8002f16 <HAL_RCCEx_PeriphCLKConfig+0x156>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8002ea8: 4b1d ldr r3, [pc, #116] ; (8002f20 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8002eaa: 6a1b ldr r3, [r3, #32]
8002eac: f003 0302 and.w r3, r3, #2
8002eb0: 2b00 cmp r3, #0
8002eb2: d0ee beq.n 8002e92 <HAL_RCCEx_PeriphCLKConfig+0xd2>
}
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
8002eb4: 4b1a ldr r3, [pc, #104] ; (8002f20 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8002eb6: 6a1b ldr r3, [r3, #32]
8002eb8: f423 7240 bic.w r2, r3, #768 ; 0x300
8002ebc: 687b ldr r3, [r7, #4]
8002ebe: 685b ldr r3, [r3, #4]
8002ec0: 4917 ldr r1, [pc, #92] ; (8002f20 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8002ec2: 4313 orrs r3, r2
8002ec4: 620b str r3, [r1, #32]
/* Require to disable power clock if necessary */
if (pwrclkchanged == SET)
8002ec6: 7dfb ldrb r3, [r7, #23]
8002ec8: 2b01 cmp r3, #1
8002eca: d105 bne.n 8002ed8 <HAL_RCCEx_PeriphCLKConfig+0x118>
{
__HAL_RCC_PWR_CLK_DISABLE();
8002ecc: 4b14 ldr r3, [pc, #80] ; (8002f20 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8002ece: 69db ldr r3, [r3, #28]
8002ed0: 4a13 ldr r2, [pc, #76] ; (8002f20 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8002ed2: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
8002ed6: 61d3 str r3, [r2, #28]
}
}
/*------------------------------ ADC clock Configuration ------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
8002ed8: 687b ldr r3, [r7, #4]
8002eda: 681b ldr r3, [r3, #0]
8002edc: f003 0302 and.w r3, r3, #2
8002ee0: 2b00 cmp r3, #0
8002ee2: d008 beq.n 8002ef6 <HAL_RCCEx_PeriphCLKConfig+0x136>
{
/* Check the parameters */
assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
/* Configure the ADC clock source */
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
8002ee4: 4b0e ldr r3, [pc, #56] ; (8002f20 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8002ee6: 685b ldr r3, [r3, #4]
8002ee8: f423 4240 bic.w r2, r3, #49152 ; 0xc000
8002eec: 687b ldr r3, [r7, #4]
8002eee: 689b ldr r3, [r3, #8]
8002ef0: 490b ldr r1, [pc, #44] ; (8002f20 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8002ef2: 4313 orrs r3, r2
8002ef4: 604b str r3, [r1, #4]
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|| defined(STM32F105xC) || defined(STM32F107xC)
/*------------------------------ USB clock Configuration ------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
8002ef6: 687b ldr r3, [r7, #4]
8002ef8: 681b ldr r3, [r3, #0]
8002efa: f003 0310 and.w r3, r3, #16
8002efe: 2b00 cmp r3, #0
8002f00: d008 beq.n 8002f14 <HAL_RCCEx_PeriphCLKConfig+0x154>
{
/* Check the parameters */
assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
/* Configure the USB clock source */
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
8002f02: 4b07 ldr r3, [pc, #28] ; (8002f20 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8002f04: 685b ldr r3, [r3, #4]
8002f06: f423 0280 bic.w r2, r3, #4194304 ; 0x400000
8002f0a: 687b ldr r3, [r7, #4]
8002f0c: 68db ldr r3, [r3, #12]
8002f0e: 4904 ldr r1, [pc, #16] ; (8002f20 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8002f10: 4313 orrs r3, r2
8002f12: 604b str r3, [r1, #4]
}
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
return HAL_OK;
8002f14: 2300 movs r3, #0
}
8002f16: 4618 mov r0, r3
8002f18: 3718 adds r7, #24
8002f1a: 46bd mov sp, r7
8002f1c: bd80 pop {r7, pc}
8002f1e: bf00 nop
8002f20: 40021000 .word 0x40021000
8002f24: 40007000 .word 0x40007000
8002f28: 42420440 .word 0x42420440
08002f2c <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
8002f2c: b580 push {r7, lr}
8002f2e: b082 sub sp, #8
8002f30: af00 add r7, sp, #0
8002f32: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8002f34: 687b ldr r3, [r7, #4]
8002f36: 2b00 cmp r3, #0
8002f38: d101 bne.n 8002f3e <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
8002f3a: 2301 movs r3, #1
8002f3c: e041 b.n 8002fc2 <HAL_TIM_Base_Init+0x96>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8002f3e: 687b ldr r3, [r7, #4]
8002f40: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8002f44: b2db uxtb r3, r3
8002f46: 2b00 cmp r3, #0
8002f48: d106 bne.n 8002f58 <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8002f4a: 687b ldr r3, [r7, #4]
8002f4c: 2200 movs r2, #0
8002f4e: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
8002f52: 6878 ldr r0, [r7, #4]
8002f54: f7fe f9fa bl 800134c <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8002f58: 687b ldr r3, [r7, #4]
8002f5a: 2202 movs r2, #2
8002f5c: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8002f60: 687b ldr r3, [r7, #4]
8002f62: 681a ldr r2, [r3, #0]
8002f64: 687b ldr r3, [r7, #4]
8002f66: 3304 adds r3, #4
8002f68: 4619 mov r1, r3
8002f6a: 4610 mov r0, r2
8002f6c: f000 fd48 bl 8003a00 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8002f70: 687b ldr r3, [r7, #4]
8002f72: 2201 movs r2, #1
8002f74: f883 2046 strb.w r2, [r3, #70] ; 0x46
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8002f78: 687b ldr r3, [r7, #4]
8002f7a: 2201 movs r2, #1
8002f7c: f883 203e strb.w r2, [r3, #62] ; 0x3e
8002f80: 687b ldr r3, [r7, #4]
8002f82: 2201 movs r2, #1
8002f84: f883 203f strb.w r2, [r3, #63] ; 0x3f
8002f88: 687b ldr r3, [r7, #4]
8002f8a: 2201 movs r2, #1
8002f8c: f883 2040 strb.w r2, [r3, #64] ; 0x40
8002f90: 687b ldr r3, [r7, #4]
8002f92: 2201 movs r2, #1
8002f94: f883 2041 strb.w r2, [r3, #65] ; 0x41
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8002f98: 687b ldr r3, [r7, #4]
8002f9a: 2201 movs r2, #1
8002f9c: f883 2042 strb.w r2, [r3, #66] ; 0x42
8002fa0: 687b ldr r3, [r7, #4]
8002fa2: 2201 movs r2, #1
8002fa4: f883 2043 strb.w r2, [r3, #67] ; 0x43
8002fa8: 687b ldr r3, [r7, #4]
8002faa: 2201 movs r2, #1
8002fac: f883 2044 strb.w r2, [r3, #68] ; 0x44
8002fb0: 687b ldr r3, [r7, #4]
8002fb2: 2201 movs r2, #1
8002fb4: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8002fb8: 687b ldr r3, [r7, #4]
8002fba: 2201 movs r2, #1
8002fbc: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
8002fc0: 2300 movs r3, #0
}
8002fc2: 4618 mov r0, r3
8002fc4: 3708 adds r7, #8
8002fc6: 46bd mov sp, r7
8002fc8: bd80 pop {r7, pc}
...
08002fcc <HAL_TIM_Base_Start>:
* @brief Starts the TIM Base generation.
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
{
8002fcc: b480 push {r7}
8002fce: b085 sub sp, #20
8002fd0: af00 add r7, sp, #0
8002fd2: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Check the TIM state */
if (htim->State != HAL_TIM_STATE_READY)
8002fd4: 687b ldr r3, [r7, #4]
8002fd6: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8002fda: b2db uxtb r3, r3
8002fdc: 2b01 cmp r3, #1
8002fde: d001 beq.n 8002fe4 <HAL_TIM_Base_Start+0x18>
{
return HAL_ERROR;
8002fe0: 2301 movs r3, #1
8002fe2: e032 b.n 800304a <HAL_TIM_Base_Start+0x7e>
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8002fe4: 687b ldr r3, [r7, #4]
8002fe6: 2202 movs r2, #2
8002fe8: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8002fec: 687b ldr r3, [r7, #4]
8002fee: 681b ldr r3, [r3, #0]
8002ff0: 4a18 ldr r2, [pc, #96] ; (8003054 <HAL_TIM_Base_Start+0x88>)
8002ff2: 4293 cmp r3, r2
8002ff4: d00e beq.n 8003014 <HAL_TIM_Base_Start+0x48>
8002ff6: 687b ldr r3, [r7, #4]
8002ff8: 681b ldr r3, [r3, #0]
8002ffa: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8002ffe: d009 beq.n 8003014 <HAL_TIM_Base_Start+0x48>
8003000: 687b ldr r3, [r7, #4]
8003002: 681b ldr r3, [r3, #0]
8003004: 4a14 ldr r2, [pc, #80] ; (8003058 <HAL_TIM_Base_Start+0x8c>)
8003006: 4293 cmp r3, r2
8003008: d004 beq.n 8003014 <HAL_TIM_Base_Start+0x48>
800300a: 687b ldr r3, [r7, #4]
800300c: 681b ldr r3, [r3, #0]
800300e: 4a13 ldr r2, [pc, #76] ; (800305c <HAL_TIM_Base_Start+0x90>)
8003010: 4293 cmp r3, r2
8003012: d111 bne.n 8003038 <HAL_TIM_Base_Start+0x6c>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
8003014: 687b ldr r3, [r7, #4]
8003016: 681b ldr r3, [r3, #0]
8003018: 689b ldr r3, [r3, #8]
800301a: f003 0307 and.w r3, r3, #7
800301e: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8003020: 68fb ldr r3, [r7, #12]
8003022: 2b06 cmp r3, #6
8003024: d010 beq.n 8003048 <HAL_TIM_Base_Start+0x7c>
{
__HAL_TIM_ENABLE(htim);
8003026: 687b ldr r3, [r7, #4]
8003028: 681b ldr r3, [r3, #0]
800302a: 681a ldr r2, [r3, #0]
800302c: 687b ldr r3, [r7, #4]
800302e: 681b ldr r3, [r3, #0]
8003030: f042 0201 orr.w r2, r2, #1
8003034: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8003036: e007 b.n 8003048 <HAL_TIM_Base_Start+0x7c>
}
}
else
{
__HAL_TIM_ENABLE(htim);
8003038: 687b ldr r3, [r7, #4]
800303a: 681b ldr r3, [r3, #0]
800303c: 681a ldr r2, [r3, #0]
800303e: 687b ldr r3, [r7, #4]
8003040: 681b ldr r3, [r3, #0]
8003042: f042 0201 orr.w r2, r2, #1
8003046: 601a str r2, [r3, #0]
}
/* Return function status */
return HAL_OK;
8003048: 2300 movs r3, #0
}
800304a: 4618 mov r0, r3
800304c: 3714 adds r7, #20
800304e: 46bd mov sp, r7
8003050: bc80 pop {r7}
8003052: 4770 bx lr
8003054: 40012c00 .word 0x40012c00
8003058: 40000400 .word 0x40000400
800305c: 40000800 .word 0x40000800
08003060 <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
8003060: b580 push {r7, lr}
8003062: b082 sub sp, #8
8003064: af00 add r7, sp, #0
8003066: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8003068: 687b ldr r3, [r7, #4]
800306a: 2b00 cmp r3, #0
800306c: d101 bne.n 8003072 <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
800306e: 2301 movs r3, #1
8003070: e041 b.n 80030f6 <HAL_TIM_PWM_Init+0x96>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8003072: 687b ldr r3, [r7, #4]
8003074: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8003078: b2db uxtb r3, r3
800307a: 2b00 cmp r3, #0
800307c: d106 bne.n 800308c <HAL_TIM_PWM_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
800307e: 687b ldr r3, [r7, #4]
8003080: 2200 movs r2, #0
8003082: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
8003086: 6878 ldr r0, [r7, #4]
8003088: f7fe f944 bl 8001314 <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
800308c: 687b ldr r3, [r7, #4]
800308e: 2202 movs r2, #2
8003090: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8003094: 687b ldr r3, [r7, #4]
8003096: 681a ldr r2, [r3, #0]
8003098: 687b ldr r3, [r7, #4]
800309a: 3304 adds r3, #4
800309c: 4619 mov r1, r3
800309e: 4610 mov r0, r2
80030a0: f000 fcae bl 8003a00 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
80030a4: 687b ldr r3, [r7, #4]
80030a6: 2201 movs r2, #1
80030a8: f883 2046 strb.w r2, [r3, #70] ; 0x46
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
80030ac: 687b ldr r3, [r7, #4]
80030ae: 2201 movs r2, #1
80030b0: f883 203e strb.w r2, [r3, #62] ; 0x3e
80030b4: 687b ldr r3, [r7, #4]
80030b6: 2201 movs r2, #1
80030b8: f883 203f strb.w r2, [r3, #63] ; 0x3f
80030bc: 687b ldr r3, [r7, #4]
80030be: 2201 movs r2, #1
80030c0: f883 2040 strb.w r2, [r3, #64] ; 0x40
80030c4: 687b ldr r3, [r7, #4]
80030c6: 2201 movs r2, #1
80030c8: f883 2041 strb.w r2, [r3, #65] ; 0x41
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
80030cc: 687b ldr r3, [r7, #4]
80030ce: 2201 movs r2, #1
80030d0: f883 2042 strb.w r2, [r3, #66] ; 0x42
80030d4: 687b ldr r3, [r7, #4]
80030d6: 2201 movs r2, #1
80030d8: f883 2043 strb.w r2, [r3, #67] ; 0x43
80030dc: 687b ldr r3, [r7, #4]
80030de: 2201 movs r2, #1
80030e0: f883 2044 strb.w r2, [r3, #68] ; 0x44
80030e4: 687b ldr r3, [r7, #4]
80030e6: 2201 movs r2, #1
80030e8: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
80030ec: 687b ldr r3, [r7, #4]
80030ee: 2201 movs r2, #1
80030f0: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
80030f4: 2300 movs r3, #0
}
80030f6: 4618 mov r0, r3
80030f8: 3708 adds r7, #8
80030fa: 46bd mov sp, r7
80030fc: bd80 pop {r7, pc}
...
08003100 <HAL_TIM_PWM_Start>:
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
8003100: b580 push {r7, lr}
8003102: b084 sub sp, #16
8003104: af00 add r7, sp, #0
8003106: 6078 str r0, [r7, #4]
8003108: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Check the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
800310a: 683b ldr r3, [r7, #0]
800310c: 2b00 cmp r3, #0
800310e: d109 bne.n 8003124 <HAL_TIM_PWM_Start+0x24>
8003110: 687b ldr r3, [r7, #4]
8003112: f893 303e ldrb.w r3, [r3, #62] ; 0x3e
8003116: b2db uxtb r3, r3
8003118: 2b01 cmp r3, #1
800311a: bf14 ite ne
800311c: 2301 movne r3, #1
800311e: 2300 moveq r3, #0
8003120: b2db uxtb r3, r3
8003122: e022 b.n 800316a <HAL_TIM_PWM_Start+0x6a>
8003124: 683b ldr r3, [r7, #0]
8003126: 2b04 cmp r3, #4
8003128: d109 bne.n 800313e <HAL_TIM_PWM_Start+0x3e>
800312a: 687b ldr r3, [r7, #4]
800312c: f893 303f ldrb.w r3, [r3, #63] ; 0x3f
8003130: b2db uxtb r3, r3
8003132: 2b01 cmp r3, #1
8003134: bf14 ite ne
8003136: 2301 movne r3, #1
8003138: 2300 moveq r3, #0
800313a: b2db uxtb r3, r3
800313c: e015 b.n 800316a <HAL_TIM_PWM_Start+0x6a>
800313e: 683b ldr r3, [r7, #0]
8003140: 2b08 cmp r3, #8
8003142: d109 bne.n 8003158 <HAL_TIM_PWM_Start+0x58>
8003144: 687b ldr r3, [r7, #4]
8003146: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
800314a: b2db uxtb r3, r3
800314c: 2b01 cmp r3, #1
800314e: bf14 ite ne
8003150: 2301 movne r3, #1
8003152: 2300 moveq r3, #0
8003154: b2db uxtb r3, r3
8003156: e008 b.n 800316a <HAL_TIM_PWM_Start+0x6a>
8003158: 687b ldr r3, [r7, #4]
800315a: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
800315e: b2db uxtb r3, r3
8003160: 2b01 cmp r3, #1
8003162: bf14 ite ne
8003164: 2301 movne r3, #1
8003166: 2300 moveq r3, #0
8003168: b2db uxtb r3, r3
800316a: 2b00 cmp r3, #0
800316c: d001 beq.n 8003172 <HAL_TIM_PWM_Start+0x72>
{
return HAL_ERROR;
800316e: 2301 movs r3, #1
8003170: e05e b.n 8003230 <HAL_TIM_PWM_Start+0x130>
}
/* Set the TIM channel state */
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
8003172: 683b ldr r3, [r7, #0]
8003174: 2b00 cmp r3, #0
8003176: d104 bne.n 8003182 <HAL_TIM_PWM_Start+0x82>
8003178: 687b ldr r3, [r7, #4]
800317a: 2202 movs r2, #2
800317c: f883 203e strb.w r2, [r3, #62] ; 0x3e
8003180: e013 b.n 80031aa <HAL_TIM_PWM_Start+0xaa>
8003182: 683b ldr r3, [r7, #0]
8003184: 2b04 cmp r3, #4
8003186: d104 bne.n 8003192 <HAL_TIM_PWM_Start+0x92>
8003188: 687b ldr r3, [r7, #4]
800318a: 2202 movs r2, #2
800318c: f883 203f strb.w r2, [r3, #63] ; 0x3f
8003190: e00b b.n 80031aa <HAL_TIM_PWM_Start+0xaa>
8003192: 683b ldr r3, [r7, #0]
8003194: 2b08 cmp r3, #8
8003196: d104 bne.n 80031a2 <HAL_TIM_PWM_Start+0xa2>
8003198: 687b ldr r3, [r7, #4]
800319a: 2202 movs r2, #2
800319c: f883 2040 strb.w r2, [r3, #64] ; 0x40
80031a0: e003 b.n 80031aa <HAL_TIM_PWM_Start+0xaa>
80031a2: 687b ldr r3, [r7, #4]
80031a4: 2202 movs r2, #2
80031a6: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
80031aa: 687b ldr r3, [r7, #4]
80031ac: 681b ldr r3, [r3, #0]
80031ae: 2201 movs r2, #1
80031b0: 6839 ldr r1, [r7, #0]
80031b2: 4618 mov r0, r3
80031b4: f000 fea4 bl 8003f00 <TIM_CCxChannelCmd>
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
80031b8: 687b ldr r3, [r7, #4]
80031ba: 681b ldr r3, [r3, #0]
80031bc: 4a1e ldr r2, [pc, #120] ; (8003238 <HAL_TIM_PWM_Start+0x138>)
80031be: 4293 cmp r3, r2
80031c0: d107 bne.n 80031d2 <HAL_TIM_PWM_Start+0xd2>
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
80031c2: 687b ldr r3, [r7, #4]
80031c4: 681b ldr r3, [r3, #0]
80031c6: 6c5a ldr r2, [r3, #68] ; 0x44
80031c8: 687b ldr r3, [r7, #4]
80031ca: 681b ldr r3, [r3, #0]
80031cc: f442 4200 orr.w r2, r2, #32768 ; 0x8000
80031d0: 645a str r2, [r3, #68] ; 0x44
}
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
80031d2: 687b ldr r3, [r7, #4]
80031d4: 681b ldr r3, [r3, #0]
80031d6: 4a18 ldr r2, [pc, #96] ; (8003238 <HAL_TIM_PWM_Start+0x138>)
80031d8: 4293 cmp r3, r2
80031da: d00e beq.n 80031fa <HAL_TIM_PWM_Start+0xfa>
80031dc: 687b ldr r3, [r7, #4]
80031de: 681b ldr r3, [r3, #0]
80031e0: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
80031e4: d009 beq.n 80031fa <HAL_TIM_PWM_Start+0xfa>
80031e6: 687b ldr r3, [r7, #4]
80031e8: 681b ldr r3, [r3, #0]
80031ea: 4a14 ldr r2, [pc, #80] ; (800323c <HAL_TIM_PWM_Start+0x13c>)
80031ec: 4293 cmp r3, r2
80031ee: d004 beq.n 80031fa <HAL_TIM_PWM_Start+0xfa>
80031f0: 687b ldr r3, [r7, #4]
80031f2: 681b ldr r3, [r3, #0]
80031f4: 4a12 ldr r2, [pc, #72] ; (8003240 <HAL_TIM_PWM_Start+0x140>)
80031f6: 4293 cmp r3, r2
80031f8: d111 bne.n 800321e <HAL_TIM_PWM_Start+0x11e>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
80031fa: 687b ldr r3, [r7, #4]
80031fc: 681b ldr r3, [r3, #0]
80031fe: 689b ldr r3, [r3, #8]
8003200: f003 0307 and.w r3, r3, #7
8003204: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8003206: 68fb ldr r3, [r7, #12]
8003208: 2b06 cmp r3, #6
800320a: d010 beq.n 800322e <HAL_TIM_PWM_Start+0x12e>
{
__HAL_TIM_ENABLE(htim);
800320c: 687b ldr r3, [r7, #4]
800320e: 681b ldr r3, [r3, #0]
8003210: 681a ldr r2, [r3, #0]
8003212: 687b ldr r3, [r7, #4]
8003214: 681b ldr r3, [r3, #0]
8003216: f042 0201 orr.w r2, r2, #1
800321a: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
800321c: e007 b.n 800322e <HAL_TIM_PWM_Start+0x12e>
}
}
else
{
__HAL_TIM_ENABLE(htim);
800321e: 687b ldr r3, [r7, #4]
8003220: 681b ldr r3, [r3, #0]
8003222: 681a ldr r2, [r3, #0]
8003224: 687b ldr r3, [r7, #4]
8003226: 681b ldr r3, [r3, #0]
8003228: f042 0201 orr.w r2, r2, #1
800322c: 601a str r2, [r3, #0]
}
/* Return function status */
return HAL_OK;
800322e: 2300 movs r3, #0
}
8003230: 4618 mov r0, r3
8003232: 3710 adds r7, #16
8003234: 46bd mov sp, r7
8003236: bd80 pop {r7, pc}
8003238: 40012c00 .word 0x40012c00
800323c: 40000400 .word 0x40000400
8003240: 40000800 .word 0x40000800
08003244 <HAL_TIM_Encoder_Init>:
* @param htim TIM Encoder Interface handle
* @param sConfig TIM Encoder Interface configuration structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
{
8003244: b580 push {r7, lr}
8003246: b086 sub sp, #24
8003248: af00 add r7, sp, #0
800324a: 6078 str r0, [r7, #4]
800324c: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Check the TIM handle allocation */
if (htim == NULL)
800324e: 687b ldr r3, [r7, #4]
8003250: 2b00 cmp r3, #0
8003252: d101 bne.n 8003258 <HAL_TIM_Encoder_Init+0x14>
{
return HAL_ERROR;
8003254: 2301 movs r3, #1
8003256: e093 b.n 8003380 <HAL_TIM_Encoder_Init+0x13c>
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
if (htim->State == HAL_TIM_STATE_RESET)
8003258: 687b ldr r3, [r7, #4]
800325a: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
800325e: b2db uxtb r3, r3
8003260: 2b00 cmp r3, #0
8003262: d106 bne.n 8003272 <HAL_TIM_Encoder_Init+0x2e>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8003264: 687b ldr r3, [r7, #4]
8003266: 2200 movs r2, #0
8003268: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Encoder_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_Encoder_MspInit(htim);
800326c: 6878 ldr r0, [r7, #4]
800326e: f7fd ffe5 bl 800123c <HAL_TIM_Encoder_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8003272: 687b ldr r3, [r7, #4]
8003274: 2202 movs r2, #2
8003276: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Reset the SMS and ECE bits */
htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
800327a: 687b ldr r3, [r7, #4]
800327c: 681b ldr r3, [r3, #0]
800327e: 689b ldr r3, [r3, #8]
8003280: 687a ldr r2, [r7, #4]
8003282: 6812 ldr r2, [r2, #0]
8003284: f423 4380 bic.w r3, r3, #16384 ; 0x4000
8003288: f023 0307 bic.w r3, r3, #7
800328c: 6093 str r3, [r2, #8]
/* Configure the Time base in the Encoder Mode */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
800328e: 687b ldr r3, [r7, #4]
8003290: 681a ldr r2, [r3, #0]
8003292: 687b ldr r3, [r7, #4]
8003294: 3304 adds r3, #4
8003296: 4619 mov r1, r3
8003298: 4610 mov r0, r2
800329a: f000 fbb1 bl 8003a00 <TIM_Base_SetConfig>
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
800329e: 687b ldr r3, [r7, #4]
80032a0: 681b ldr r3, [r3, #0]
80032a2: 689b ldr r3, [r3, #8]
80032a4: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmr1 = htim->Instance->CCMR1;
80032a6: 687b ldr r3, [r7, #4]
80032a8: 681b ldr r3, [r3, #0]
80032aa: 699b ldr r3, [r3, #24]
80032ac: 613b str r3, [r7, #16]
/* Get the TIMx CCER register value */
tmpccer = htim->Instance->CCER;
80032ae: 687b ldr r3, [r7, #4]
80032b0: 681b ldr r3, [r3, #0]
80032b2: 6a1b ldr r3, [r3, #32]
80032b4: 60fb str r3, [r7, #12]
/* Set the encoder Mode */
tmpsmcr |= sConfig->EncoderMode;
80032b6: 683b ldr r3, [r7, #0]
80032b8: 681b ldr r3, [r3, #0]
80032ba: 697a ldr r2, [r7, #20]
80032bc: 4313 orrs r3, r2
80032be: 617b str r3, [r7, #20]
/* Select the Capture Compare 1 and the Capture Compare 2 as input */
tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
80032c0: 693b ldr r3, [r7, #16]
80032c2: f423 7340 bic.w r3, r3, #768 ; 0x300
80032c6: f023 0303 bic.w r3, r3, #3
80032ca: 613b str r3, [r7, #16]
tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
80032cc: 683b ldr r3, [r7, #0]
80032ce: 689a ldr r2, [r3, #8]
80032d0: 683b ldr r3, [r7, #0]
80032d2: 699b ldr r3, [r3, #24]
80032d4: 021b lsls r3, r3, #8
80032d6: 4313 orrs r3, r2
80032d8: 693a ldr r2, [r7, #16]
80032da: 4313 orrs r3, r2
80032dc: 613b str r3, [r7, #16]
/* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
80032de: 693b ldr r3, [r7, #16]
80032e0: f423 6340 bic.w r3, r3, #3072 ; 0xc00
80032e4: f023 030c bic.w r3, r3, #12
80032e8: 613b str r3, [r7, #16]
tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
80032ea: 693b ldr r3, [r7, #16]
80032ec: f423 4370 bic.w r3, r3, #61440 ; 0xf000
80032f0: f023 03f0 bic.w r3, r3, #240 ; 0xf0
80032f4: 613b str r3, [r7, #16]
tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
80032f6: 683b ldr r3, [r7, #0]
80032f8: 68da ldr r2, [r3, #12]
80032fa: 683b ldr r3, [r7, #0]
80032fc: 69db ldr r3, [r3, #28]
80032fe: 021b lsls r3, r3, #8
8003300: 4313 orrs r3, r2
8003302: 693a ldr r2, [r7, #16]
8003304: 4313 orrs r3, r2
8003306: 613b str r3, [r7, #16]
tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
8003308: 683b ldr r3, [r7, #0]
800330a: 691b ldr r3, [r3, #16]
800330c: 011a lsls r2, r3, #4
800330e: 683b ldr r3, [r7, #0]
8003310: 6a1b ldr r3, [r3, #32]
8003312: 031b lsls r3, r3, #12
8003314: 4313 orrs r3, r2
8003316: 693a ldr r2, [r7, #16]
8003318: 4313 orrs r3, r2
800331a: 613b str r3, [r7, #16]
/* Set the TI1 and the TI2 Polarities */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
800331c: 68fb ldr r3, [r7, #12]
800331e: f023 0322 bic.w r3, r3, #34 ; 0x22
8003322: 60fb str r3, [r7, #12]
tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
8003324: 683b ldr r3, [r7, #0]
8003326: 685a ldr r2, [r3, #4]
8003328: 683b ldr r3, [r7, #0]
800332a: 695b ldr r3, [r3, #20]
800332c: 011b lsls r3, r3, #4
800332e: 4313 orrs r3, r2
8003330: 68fa ldr r2, [r7, #12]
8003332: 4313 orrs r3, r2
8003334: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8003336: 687b ldr r3, [r7, #4]
8003338: 681b ldr r3, [r3, #0]
800333a: 697a ldr r2, [r7, #20]
800333c: 609a str r2, [r3, #8]
/* Write to TIMx CCMR1 */
htim->Instance->CCMR1 = tmpccmr1;
800333e: 687b ldr r3, [r7, #4]
8003340: 681b ldr r3, [r3, #0]
8003342: 693a ldr r2, [r7, #16]
8003344: 619a str r2, [r3, #24]
/* Write to TIMx CCER */
htim->Instance->CCER = tmpccer;
8003346: 687b ldr r3, [r7, #4]
8003348: 681b ldr r3, [r3, #0]
800334a: 68fa ldr r2, [r7, #12]
800334c: 621a str r2, [r3, #32]
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
800334e: 687b ldr r3, [r7, #4]
8003350: 2201 movs r2, #1
8003352: f883 2046 strb.w r2, [r3, #70] ; 0x46
/* Set the TIM channels state */
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
8003356: 687b ldr r3, [r7, #4]
8003358: 2201 movs r2, #1
800335a: f883 203e strb.w r2, [r3, #62] ; 0x3e
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
800335e: 687b ldr r3, [r7, #4]
8003360: 2201 movs r2, #1
8003362: f883 203f strb.w r2, [r3, #63] ; 0x3f
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
8003366: 687b ldr r3, [r7, #4]
8003368: 2201 movs r2, #1
800336a: f883 2042 strb.w r2, [r3, #66] ; 0x42
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
800336e: 687b ldr r3, [r7, #4]
8003370: 2201 movs r2, #1
8003372: f883 2043 strb.w r2, [r3, #67] ; 0x43
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8003376: 687b ldr r3, [r7, #4]
8003378: 2201 movs r2, #1
800337a: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
800337e: 2300 movs r3, #0
}
8003380: 4618 mov r0, r3
8003382: 3718 adds r7, #24
8003384: 46bd mov sp, r7
8003386: bd80 pop {r7, pc}
08003388 <HAL_TIM_Encoder_Start>:
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
8003388: b580 push {r7, lr}
800338a: b084 sub sp, #16
800338c: af00 add r7, sp, #0
800338e: 6078 str r0, [r7, #4]
8003390: 6039 str r1, [r7, #0]
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
8003392: 687b ldr r3, [r7, #4]
8003394: f893 303e ldrb.w r3, [r3, #62] ; 0x3e
8003398: 73fb strb r3, [r7, #15]
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
800339a: 687b ldr r3, [r7, #4]
800339c: f893 303f ldrb.w r3, [r3, #63] ; 0x3f
80033a0: 73bb strb r3, [r7, #14]
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
80033a2: 687b ldr r3, [r7, #4]
80033a4: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
80033a8: 737b strb r3, [r7, #13]
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
80033aa: 687b ldr r3, [r7, #4]
80033ac: f893 3043 ldrb.w r3, [r3, #67] ; 0x43
80033b0: 733b strb r3, [r7, #12]
/* Check the parameters */
assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Set the TIM channel(s) state */
if (Channel == TIM_CHANNEL_1)
80033b2: 683b ldr r3, [r7, #0]
80033b4: 2b00 cmp r3, #0
80033b6: d110 bne.n 80033da <HAL_TIM_Encoder_Start+0x52>
{
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
80033b8: 7bfb ldrb r3, [r7, #15]
80033ba: 2b01 cmp r3, #1
80033bc: d102 bne.n 80033c4 <HAL_TIM_Encoder_Start+0x3c>
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
80033be: 7b7b ldrb r3, [r7, #13]
80033c0: 2b01 cmp r3, #1
80033c2: d001 beq.n 80033c8 <HAL_TIM_Encoder_Start+0x40>
{
return HAL_ERROR;
80033c4: 2301 movs r3, #1
80033c6: e069 b.n 800349c <HAL_TIM_Encoder_Start+0x114>
}
else
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
80033c8: 687b ldr r3, [r7, #4]
80033ca: 2202 movs r2, #2
80033cc: f883 203e strb.w r2, [r3, #62] ; 0x3e
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
80033d0: 687b ldr r3, [r7, #4]
80033d2: 2202 movs r2, #2
80033d4: f883 2042 strb.w r2, [r3, #66] ; 0x42
80033d8: e031 b.n 800343e <HAL_TIM_Encoder_Start+0xb6>
}
}
else if (Channel == TIM_CHANNEL_2)
80033da: 683b ldr r3, [r7, #0]
80033dc: 2b04 cmp r3, #4
80033de: d110 bne.n 8003402 <HAL_TIM_Encoder_Start+0x7a>
{
if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
80033e0: 7bbb ldrb r3, [r7, #14]
80033e2: 2b01 cmp r3, #1
80033e4: d102 bne.n 80033ec <HAL_TIM_Encoder_Start+0x64>
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
80033e6: 7b3b ldrb r3, [r7, #12]
80033e8: 2b01 cmp r3, #1
80033ea: d001 beq.n 80033f0 <HAL_TIM_Encoder_Start+0x68>
{
return HAL_ERROR;
80033ec: 2301 movs r3, #1
80033ee: e055 b.n 800349c <HAL_TIM_Encoder_Start+0x114>
}
else
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
80033f0: 687b ldr r3, [r7, #4]
80033f2: 2202 movs r2, #2
80033f4: f883 203f strb.w r2, [r3, #63] ; 0x3f
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
80033f8: 687b ldr r3, [r7, #4]
80033fa: 2202 movs r2, #2
80033fc: f883 2043 strb.w r2, [r3, #67] ; 0x43
8003400: e01d b.n 800343e <HAL_TIM_Encoder_Start+0xb6>
}
}
else
{
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
8003402: 7bfb ldrb r3, [r7, #15]
8003404: 2b01 cmp r3, #1
8003406: d108 bne.n 800341a <HAL_TIM_Encoder_Start+0x92>
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
8003408: 7bbb ldrb r3, [r7, #14]
800340a: 2b01 cmp r3, #1
800340c: d105 bne.n 800341a <HAL_TIM_Encoder_Start+0x92>
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
800340e: 7b7b ldrb r3, [r7, #13]
8003410: 2b01 cmp r3, #1
8003412: d102 bne.n 800341a <HAL_TIM_Encoder_Start+0x92>
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
8003414: 7b3b ldrb r3, [r7, #12]
8003416: 2b01 cmp r3, #1
8003418: d001 beq.n 800341e <HAL_TIM_Encoder_Start+0x96>
{
return HAL_ERROR;
800341a: 2301 movs r3, #1
800341c: e03e b.n 800349c <HAL_TIM_Encoder_Start+0x114>
}
else
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
800341e: 687b ldr r3, [r7, #4]
8003420: 2202 movs r2, #2
8003422: f883 203e strb.w r2, [r3, #62] ; 0x3e
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
8003426: 687b ldr r3, [r7, #4]
8003428: 2202 movs r2, #2
800342a: f883 203f strb.w r2, [r3, #63] ; 0x3f
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
800342e: 687b ldr r3, [r7, #4]
8003430: 2202 movs r2, #2
8003432: f883 2042 strb.w r2, [r3, #66] ; 0x42
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
8003436: 687b ldr r3, [r7, #4]
8003438: 2202 movs r2, #2
800343a: f883 2043 strb.w r2, [r3, #67] ; 0x43
}
}
/* Enable the encoder interface channels */
switch (Channel)
800343e: 683b ldr r3, [r7, #0]
8003440: 2b00 cmp r3, #0
8003442: d003 beq.n 800344c <HAL_TIM_Encoder_Start+0xc4>
8003444: 683b ldr r3, [r7, #0]
8003446: 2b04 cmp r3, #4
8003448: d008 beq.n 800345c <HAL_TIM_Encoder_Start+0xd4>
800344a: e00f b.n 800346c <HAL_TIM_Encoder_Start+0xe4>
{
case TIM_CHANNEL_1:
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
800344c: 687b ldr r3, [r7, #4]
800344e: 681b ldr r3, [r3, #0]
8003450: 2201 movs r2, #1
8003452: 2100 movs r1, #0
8003454: 4618 mov r0, r3
8003456: f000 fd53 bl 8003f00 <TIM_CCxChannelCmd>
break;
800345a: e016 b.n 800348a <HAL_TIM_Encoder_Start+0x102>
}
case TIM_CHANNEL_2:
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
800345c: 687b ldr r3, [r7, #4]
800345e: 681b ldr r3, [r3, #0]
8003460: 2201 movs r2, #1
8003462: 2104 movs r1, #4
8003464: 4618 mov r0, r3
8003466: f000 fd4b bl 8003f00 <TIM_CCxChannelCmd>
break;
800346a: e00e b.n 800348a <HAL_TIM_Encoder_Start+0x102>
}
default :
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
800346c: 687b ldr r3, [r7, #4]
800346e: 681b ldr r3, [r3, #0]
8003470: 2201 movs r2, #1
8003472: 2100 movs r1, #0
8003474: 4618 mov r0, r3
8003476: f000 fd43 bl 8003f00 <TIM_CCxChannelCmd>
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
800347a: 687b ldr r3, [r7, #4]
800347c: 681b ldr r3, [r3, #0]
800347e: 2201 movs r2, #1
8003480: 2104 movs r1, #4
8003482: 4618 mov r0, r3
8003484: f000 fd3c bl 8003f00 <TIM_CCxChannelCmd>
break;
8003488: bf00 nop
}
}
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
800348a: 687b ldr r3, [r7, #4]
800348c: 681b ldr r3, [r3, #0]
800348e: 681a ldr r2, [r3, #0]
8003490: 687b ldr r3, [r7, #4]
8003492: 681b ldr r3, [r3, #0]
8003494: f042 0201 orr.w r2, r2, #1
8003498: 601a str r2, [r3, #0]
/* Return function status */
return HAL_OK;
800349a: 2300 movs r3, #0
}
800349c: 4618 mov r0, r3
800349e: 3710 adds r7, #16
80034a0: 46bd mov sp, r7
80034a2: bd80 pop {r7, pc}
080034a4 <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
80034a4: b580 push {r7, lr}
80034a6: b082 sub sp, #8
80034a8: af00 add r7, sp, #0
80034aa: 6078 str r0, [r7, #4]
/* Capture compare 1 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
80034ac: 687b ldr r3, [r7, #4]
80034ae: 681b ldr r3, [r3, #0]
80034b0: 691b ldr r3, [r3, #16]
80034b2: f003 0302 and.w r3, r3, #2
80034b6: 2b02 cmp r3, #2
80034b8: d122 bne.n 8003500 <HAL_TIM_IRQHandler+0x5c>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
80034ba: 687b ldr r3, [r7, #4]
80034bc: 681b ldr r3, [r3, #0]
80034be: 68db ldr r3, [r3, #12]
80034c0: f003 0302 and.w r3, r3, #2
80034c4: 2b02 cmp r3, #2
80034c6: d11b bne.n 8003500 <HAL_TIM_IRQHandler+0x5c>
{
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
80034c8: 687b ldr r3, [r7, #4]
80034ca: 681b ldr r3, [r3, #0]
80034cc: f06f 0202 mvn.w r2, #2
80034d0: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
80034d2: 687b ldr r3, [r7, #4]
80034d4: 2201 movs r2, #1
80034d6: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
80034d8: 687b ldr r3, [r7, #4]
80034da: 681b ldr r3, [r3, #0]
80034dc: 699b ldr r3, [r3, #24]
80034de: f003 0303 and.w r3, r3, #3
80034e2: 2b00 cmp r3, #0
80034e4: d003 beq.n 80034ee <HAL_TIM_IRQHandler+0x4a>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
80034e6: 6878 ldr r0, [r7, #4]
80034e8: f000 fa6f bl 80039ca <HAL_TIM_IC_CaptureCallback>
80034ec: e005 b.n 80034fa <HAL_TIM_IRQHandler+0x56>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
80034ee: 6878 ldr r0, [r7, #4]
80034f0: f000 fa62 bl 80039b8 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
80034f4: 6878 ldr r0, [r7, #4]
80034f6: f000 fa71 bl 80039dc <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
80034fa: 687b ldr r3, [r7, #4]
80034fc: 2200 movs r2, #0
80034fe: 771a strb r2, [r3, #28]
}
}
}
/* Capture compare 2 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
8003500: 687b ldr r3, [r7, #4]
8003502: 681b ldr r3, [r3, #0]
8003504: 691b ldr r3, [r3, #16]
8003506: f003 0304 and.w r3, r3, #4
800350a: 2b04 cmp r3, #4
800350c: d122 bne.n 8003554 <HAL_TIM_IRQHandler+0xb0>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
800350e: 687b ldr r3, [r7, #4]
8003510: 681b ldr r3, [r3, #0]
8003512: 68db ldr r3, [r3, #12]
8003514: f003 0304 and.w r3, r3, #4
8003518: 2b04 cmp r3, #4
800351a: d11b bne.n 8003554 <HAL_TIM_IRQHandler+0xb0>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
800351c: 687b ldr r3, [r7, #4]
800351e: 681b ldr r3, [r3, #0]
8003520: f06f 0204 mvn.w r2, #4
8003524: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
8003526: 687b ldr r3, [r7, #4]
8003528: 2202 movs r2, #2
800352a: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
800352c: 687b ldr r3, [r7, #4]
800352e: 681b ldr r3, [r3, #0]
8003530: 699b ldr r3, [r3, #24]
8003532: f403 7340 and.w r3, r3, #768 ; 0x300
8003536: 2b00 cmp r3, #0
8003538: d003 beq.n 8003542 <HAL_TIM_IRQHandler+0x9e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
800353a: 6878 ldr r0, [r7, #4]
800353c: f000 fa45 bl 80039ca <HAL_TIM_IC_CaptureCallback>
8003540: e005 b.n 800354e <HAL_TIM_IRQHandler+0xaa>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8003542: 6878 ldr r0, [r7, #4]
8003544: f000 fa38 bl 80039b8 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8003548: 6878 ldr r0, [r7, #4]
800354a: f000 fa47 bl 80039dc <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
800354e: 687b ldr r3, [r7, #4]
8003550: 2200 movs r2, #0
8003552: 771a strb r2, [r3, #28]
}
}
/* Capture compare 3 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
8003554: 687b ldr r3, [r7, #4]
8003556: 681b ldr r3, [r3, #0]
8003558: 691b ldr r3, [r3, #16]
800355a: f003 0308 and.w r3, r3, #8
800355e: 2b08 cmp r3, #8
8003560: d122 bne.n 80035a8 <HAL_TIM_IRQHandler+0x104>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
8003562: 687b ldr r3, [r7, #4]
8003564: 681b ldr r3, [r3, #0]
8003566: 68db ldr r3, [r3, #12]
8003568: f003 0308 and.w r3, r3, #8
800356c: 2b08 cmp r3, #8
800356e: d11b bne.n 80035a8 <HAL_TIM_IRQHandler+0x104>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
8003570: 687b ldr r3, [r7, #4]
8003572: 681b ldr r3, [r3, #0]
8003574: f06f 0208 mvn.w r2, #8
8003578: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
800357a: 687b ldr r3, [r7, #4]
800357c: 2204 movs r2, #4
800357e: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
8003580: 687b ldr r3, [r7, #4]
8003582: 681b ldr r3, [r3, #0]
8003584: 69db ldr r3, [r3, #28]
8003586: f003 0303 and.w r3, r3, #3
800358a: 2b00 cmp r3, #0
800358c: d003 beq.n 8003596 <HAL_TIM_IRQHandler+0xf2>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
800358e: 6878 ldr r0, [r7, #4]
8003590: f000 fa1b bl 80039ca <HAL_TIM_IC_CaptureCallback>
8003594: e005 b.n 80035a2 <HAL_TIM_IRQHandler+0xfe>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8003596: 6878 ldr r0, [r7, #4]
8003598: f000 fa0e bl 80039b8 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
800359c: 6878 ldr r0, [r7, #4]
800359e: f000 fa1d bl 80039dc <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
80035a2: 687b ldr r3, [r7, #4]
80035a4: 2200 movs r2, #0
80035a6: 771a strb r2, [r3, #28]
}
}
/* Capture compare 4 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
80035a8: 687b ldr r3, [r7, #4]
80035aa: 681b ldr r3, [r3, #0]
80035ac: 691b ldr r3, [r3, #16]
80035ae: f003 0310 and.w r3, r3, #16
80035b2: 2b10 cmp r3, #16
80035b4: d122 bne.n 80035fc <HAL_TIM_IRQHandler+0x158>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
80035b6: 687b ldr r3, [r7, #4]
80035b8: 681b ldr r3, [r3, #0]
80035ba: 68db ldr r3, [r3, #12]
80035bc: f003 0310 and.w r3, r3, #16
80035c0: 2b10 cmp r3, #16
80035c2: d11b bne.n 80035fc <HAL_TIM_IRQHandler+0x158>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
80035c4: 687b ldr r3, [r7, #4]
80035c6: 681b ldr r3, [r3, #0]
80035c8: f06f 0210 mvn.w r2, #16
80035cc: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
80035ce: 687b ldr r3, [r7, #4]
80035d0: 2208 movs r2, #8
80035d2: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
80035d4: 687b ldr r3, [r7, #4]
80035d6: 681b ldr r3, [r3, #0]
80035d8: 69db ldr r3, [r3, #28]
80035da: f403 7340 and.w r3, r3, #768 ; 0x300
80035de: 2b00 cmp r3, #0
80035e0: d003 beq.n 80035ea <HAL_TIM_IRQHandler+0x146>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
80035e2: 6878 ldr r0, [r7, #4]
80035e4: f000 f9f1 bl 80039ca <HAL_TIM_IC_CaptureCallback>
80035e8: e005 b.n 80035f6 <HAL_TIM_IRQHandler+0x152>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
80035ea: 6878 ldr r0, [r7, #4]
80035ec: f000 f9e4 bl 80039b8 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
80035f0: 6878 ldr r0, [r7, #4]
80035f2: f000 f9f3 bl 80039dc <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
80035f6: 687b ldr r3, [r7, #4]
80035f8: 2200 movs r2, #0
80035fa: 771a strb r2, [r3, #28]
}
}
/* TIM Update event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
80035fc: 687b ldr r3, [r7, #4]
80035fe: 681b ldr r3, [r3, #0]
8003600: 691b ldr r3, [r3, #16]
8003602: f003 0301 and.w r3, r3, #1
8003606: 2b01 cmp r3, #1
8003608: d10e bne.n 8003628 <HAL_TIM_IRQHandler+0x184>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
800360a: 687b ldr r3, [r7, #4]
800360c: 681b ldr r3, [r3, #0]
800360e: 68db ldr r3, [r3, #12]
8003610: f003 0301 and.w r3, r3, #1
8003614: 2b01 cmp r3, #1
8003616: d107 bne.n 8003628 <HAL_TIM_IRQHandler+0x184>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
8003618: 687b ldr r3, [r7, #4]
800361a: 681b ldr r3, [r3, #0]
800361c: f06f 0201 mvn.w r2, #1
8003620: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
8003622: 6878 ldr r0, [r7, #4]
8003624: f7fd f902 bl 800082c <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
8003628: 687b ldr r3, [r7, #4]
800362a: 681b ldr r3, [r3, #0]
800362c: 691b ldr r3, [r3, #16]
800362e: f003 0380 and.w r3, r3, #128 ; 0x80
8003632: 2b80 cmp r3, #128 ; 0x80
8003634: d10e bne.n 8003654 <HAL_TIM_IRQHandler+0x1b0>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
8003636: 687b ldr r3, [r7, #4]
8003638: 681b ldr r3, [r3, #0]
800363a: 68db ldr r3, [r3, #12]
800363c: f003 0380 and.w r3, r3, #128 ; 0x80
8003640: 2b80 cmp r3, #128 ; 0x80
8003642: d107 bne.n 8003654 <HAL_TIM_IRQHandler+0x1b0>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
8003644: 687b ldr r3, [r7, #4]
8003646: 681b ldr r3, [r3, #0]
8003648: f06f 0280 mvn.w r2, #128 ; 0x80
800364c: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
HAL_TIMEx_BreakCallback(htim);
800364e: 6878 ldr r0, [r7, #4]
8003650: f000 fce1 bl 8004016 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
8003654: 687b ldr r3, [r7, #4]
8003656: 681b ldr r3, [r3, #0]
8003658: 691b ldr r3, [r3, #16]
800365a: f003 0340 and.w r3, r3, #64 ; 0x40
800365e: 2b40 cmp r3, #64 ; 0x40
8003660: d10e bne.n 8003680 <HAL_TIM_IRQHandler+0x1dc>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
8003662: 687b ldr r3, [r7, #4]
8003664: 681b ldr r3, [r3, #0]
8003666: 68db ldr r3, [r3, #12]
8003668: f003 0340 and.w r3, r3, #64 ; 0x40
800366c: 2b40 cmp r3, #64 ; 0x40
800366e: d107 bne.n 8003680 <HAL_TIM_IRQHandler+0x1dc>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
8003670: 687b ldr r3, [r7, #4]
8003672: 681b ldr r3, [r3, #0]
8003674: f06f 0240 mvn.w r2, #64 ; 0x40
8003678: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
800367a: 6878 ldr r0, [r7, #4]
800367c: f000 f9b7 bl 80039ee <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
8003680: 687b ldr r3, [r7, #4]
8003682: 681b ldr r3, [r3, #0]
8003684: 691b ldr r3, [r3, #16]
8003686: f003 0320 and.w r3, r3, #32
800368a: 2b20 cmp r3, #32
800368c: d10e bne.n 80036ac <HAL_TIM_IRQHandler+0x208>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
800368e: 687b ldr r3, [r7, #4]
8003690: 681b ldr r3, [r3, #0]
8003692: 68db ldr r3, [r3, #12]
8003694: f003 0320 and.w r3, r3, #32
8003698: 2b20 cmp r3, #32
800369a: d107 bne.n 80036ac <HAL_TIM_IRQHandler+0x208>
{
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
800369c: 687b ldr r3, [r7, #4]
800369e: 681b ldr r3, [r3, #0]
80036a0: f06f 0220 mvn.w r2, #32
80036a4: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
HAL_TIMEx_CommutCallback(htim);
80036a6: 6878 ldr r0, [r7, #4]
80036a8: f000 fcac bl 8004004 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
80036ac: bf00 nop
80036ae: 3708 adds r7, #8
80036b0: 46bd mov sp, r7
80036b2: bd80 pop {r7, pc}
080036b4 <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
80036b4: b580 push {r7, lr}
80036b6: b084 sub sp, #16
80036b8: af00 add r7, sp, #0
80036ba: 60f8 str r0, [r7, #12]
80036bc: 60b9 str r1, [r7, #8]
80036be: 607a str r2, [r7, #4]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
80036c0: 68fb ldr r3, [r7, #12]
80036c2: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
80036c6: 2b01 cmp r3, #1
80036c8: d101 bne.n 80036ce <HAL_TIM_PWM_ConfigChannel+0x1a>
80036ca: 2302 movs r3, #2
80036cc: e0ac b.n 8003828 <HAL_TIM_PWM_ConfigChannel+0x174>
80036ce: 68fb ldr r3, [r7, #12]
80036d0: 2201 movs r2, #1
80036d2: f883 203c strb.w r2, [r3, #60] ; 0x3c
switch (Channel)
80036d6: 687b ldr r3, [r7, #4]
80036d8: 2b0c cmp r3, #12
80036da: f200 809f bhi.w 800381c <HAL_TIM_PWM_ConfigChannel+0x168>
80036de: a201 add r2, pc, #4 ; (adr r2, 80036e4 <HAL_TIM_PWM_ConfigChannel+0x30>)
80036e0: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80036e4: 08003719 .word 0x08003719
80036e8: 0800381d .word 0x0800381d
80036ec: 0800381d .word 0x0800381d
80036f0: 0800381d .word 0x0800381d
80036f4: 08003759 .word 0x08003759
80036f8: 0800381d .word 0x0800381d
80036fc: 0800381d .word 0x0800381d
8003700: 0800381d .word 0x0800381d
8003704: 0800379b .word 0x0800379b
8003708: 0800381d .word 0x0800381d
800370c: 0800381d .word 0x0800381d
8003710: 0800381d .word 0x0800381d
8003714: 080037db .word 0x080037db
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
8003718: 68fb ldr r3, [r7, #12]
800371a: 681b ldr r3, [r3, #0]
800371c: 68b9 ldr r1, [r7, #8]
800371e: 4618 mov r0, r3
8003720: f000 f9d0 bl 8003ac4 <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
8003724: 68fb ldr r3, [r7, #12]
8003726: 681b ldr r3, [r3, #0]
8003728: 699a ldr r2, [r3, #24]
800372a: 68fb ldr r3, [r7, #12]
800372c: 681b ldr r3, [r3, #0]
800372e: f042 0208 orr.w r2, r2, #8
8003732: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
8003734: 68fb ldr r3, [r7, #12]
8003736: 681b ldr r3, [r3, #0]
8003738: 699a ldr r2, [r3, #24]
800373a: 68fb ldr r3, [r7, #12]
800373c: 681b ldr r3, [r3, #0]
800373e: f022 0204 bic.w r2, r2, #4
8003742: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
8003744: 68fb ldr r3, [r7, #12]
8003746: 681b ldr r3, [r3, #0]
8003748: 6999 ldr r1, [r3, #24]
800374a: 68bb ldr r3, [r7, #8]
800374c: 691a ldr r2, [r3, #16]
800374e: 68fb ldr r3, [r7, #12]
8003750: 681b ldr r3, [r3, #0]
8003752: 430a orrs r2, r1
8003754: 619a str r2, [r3, #24]
break;
8003756: e062 b.n 800381e <HAL_TIM_PWM_ConfigChannel+0x16a>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
8003758: 68fb ldr r3, [r7, #12]
800375a: 681b ldr r3, [r3, #0]
800375c: 68b9 ldr r1, [r7, #8]
800375e: 4618 mov r0, r3
8003760: f000 fa16 bl 8003b90 <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
8003764: 68fb ldr r3, [r7, #12]
8003766: 681b ldr r3, [r3, #0]
8003768: 699a ldr r2, [r3, #24]
800376a: 68fb ldr r3, [r7, #12]
800376c: 681b ldr r3, [r3, #0]
800376e: f442 6200 orr.w r2, r2, #2048 ; 0x800
8003772: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
8003774: 68fb ldr r3, [r7, #12]
8003776: 681b ldr r3, [r3, #0]
8003778: 699a ldr r2, [r3, #24]
800377a: 68fb ldr r3, [r7, #12]
800377c: 681b ldr r3, [r3, #0]
800377e: f422 6280 bic.w r2, r2, #1024 ; 0x400
8003782: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
8003784: 68fb ldr r3, [r7, #12]
8003786: 681b ldr r3, [r3, #0]
8003788: 6999 ldr r1, [r3, #24]
800378a: 68bb ldr r3, [r7, #8]
800378c: 691b ldr r3, [r3, #16]
800378e: 021a lsls r2, r3, #8
8003790: 68fb ldr r3, [r7, #12]
8003792: 681b ldr r3, [r3, #0]
8003794: 430a orrs r2, r1
8003796: 619a str r2, [r3, #24]
break;
8003798: e041 b.n 800381e <HAL_TIM_PWM_ConfigChannel+0x16a>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
800379a: 68fb ldr r3, [r7, #12]
800379c: 681b ldr r3, [r3, #0]
800379e: 68b9 ldr r1, [r7, #8]
80037a0: 4618 mov r0, r3
80037a2: f000 fa5f bl 8003c64 <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
80037a6: 68fb ldr r3, [r7, #12]
80037a8: 681b ldr r3, [r3, #0]
80037aa: 69da ldr r2, [r3, #28]
80037ac: 68fb ldr r3, [r7, #12]
80037ae: 681b ldr r3, [r3, #0]
80037b0: f042 0208 orr.w r2, r2, #8
80037b4: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
80037b6: 68fb ldr r3, [r7, #12]
80037b8: 681b ldr r3, [r3, #0]
80037ba: 69da ldr r2, [r3, #28]
80037bc: 68fb ldr r3, [r7, #12]
80037be: 681b ldr r3, [r3, #0]
80037c0: f022 0204 bic.w r2, r2, #4
80037c4: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
80037c6: 68fb ldr r3, [r7, #12]
80037c8: 681b ldr r3, [r3, #0]
80037ca: 69d9 ldr r1, [r3, #28]
80037cc: 68bb ldr r3, [r7, #8]
80037ce: 691a ldr r2, [r3, #16]
80037d0: 68fb ldr r3, [r7, #12]
80037d2: 681b ldr r3, [r3, #0]
80037d4: 430a orrs r2, r1
80037d6: 61da str r2, [r3, #28]
break;
80037d8: e021 b.n 800381e <HAL_TIM_PWM_ConfigChannel+0x16a>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
80037da: 68fb ldr r3, [r7, #12]
80037dc: 681b ldr r3, [r3, #0]
80037de: 68b9 ldr r1, [r7, #8]
80037e0: 4618 mov r0, r3
80037e2: f000 faa9 bl 8003d38 <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
80037e6: 68fb ldr r3, [r7, #12]
80037e8: 681b ldr r3, [r3, #0]
80037ea: 69da ldr r2, [r3, #28]
80037ec: 68fb ldr r3, [r7, #12]
80037ee: 681b ldr r3, [r3, #0]
80037f0: f442 6200 orr.w r2, r2, #2048 ; 0x800
80037f4: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
80037f6: 68fb ldr r3, [r7, #12]
80037f8: 681b ldr r3, [r3, #0]
80037fa: 69da ldr r2, [r3, #28]
80037fc: 68fb ldr r3, [r7, #12]
80037fe: 681b ldr r3, [r3, #0]
8003800: f422 6280 bic.w r2, r2, #1024 ; 0x400
8003804: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
8003806: 68fb ldr r3, [r7, #12]
8003808: 681b ldr r3, [r3, #0]
800380a: 69d9 ldr r1, [r3, #28]
800380c: 68bb ldr r3, [r7, #8]
800380e: 691b ldr r3, [r3, #16]
8003810: 021a lsls r2, r3, #8
8003812: 68fb ldr r3, [r7, #12]
8003814: 681b ldr r3, [r3, #0]
8003816: 430a orrs r2, r1
8003818: 61da str r2, [r3, #28]
break;
800381a: e000 b.n 800381e <HAL_TIM_PWM_ConfigChannel+0x16a>
}
default:
break;
800381c: bf00 nop
}
__HAL_UNLOCK(htim);
800381e: 68fb ldr r3, [r7, #12]
8003820: 2200 movs r2, #0
8003822: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
8003826: 2300 movs r3, #0
}
8003828: 4618 mov r0, r3
800382a: 3710 adds r7, #16
800382c: 46bd mov sp, r7
800382e: bd80 pop {r7, pc}
08003830 <HAL_TIM_ConfigClockSource>:
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
{
8003830: b580 push {r7, lr}
8003832: b084 sub sp, #16
8003834: af00 add r7, sp, #0
8003836: 6078 str r0, [r7, #4]
8003838: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
800383a: 687b ldr r3, [r7, #4]
800383c: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8003840: 2b01 cmp r3, #1
8003842: d101 bne.n 8003848 <HAL_TIM_ConfigClockSource+0x18>
8003844: 2302 movs r3, #2
8003846: e0b3 b.n 80039b0 <HAL_TIM_ConfigClockSource+0x180>
8003848: 687b ldr r3, [r7, #4]
800384a: 2201 movs r2, #1
800384c: f883 203c strb.w r2, [r3, #60] ; 0x3c
htim->State = HAL_TIM_STATE_BUSY;
8003850: 687b ldr r3, [r7, #4]
8003852: 2202 movs r2, #2
8003854: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
8003858: 687b ldr r3, [r7, #4]
800385a: 681b ldr r3, [r3, #0]
800385c: 689b ldr r3, [r3, #8]
800385e: 60fb str r3, [r7, #12]
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
8003860: 68fb ldr r3, [r7, #12]
8003862: f023 0377 bic.w r3, r3, #119 ; 0x77
8003866: 60fb str r3, [r7, #12]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8003868: 68fb ldr r3, [r7, #12]
800386a: f423 437f bic.w r3, r3, #65280 ; 0xff00
800386e: 60fb str r3, [r7, #12]
htim->Instance->SMCR = tmpsmcr;
8003870: 687b ldr r3, [r7, #4]
8003872: 681b ldr r3, [r3, #0]
8003874: 68fa ldr r2, [r7, #12]
8003876: 609a str r2, [r3, #8]
switch (sClockSourceConfig->ClockSource)
8003878: 683b ldr r3, [r7, #0]
800387a: 681b ldr r3, [r3, #0]
800387c: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
8003880: d03e beq.n 8003900 <HAL_TIM_ConfigClockSource+0xd0>
8003882: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
8003886: f200 8087 bhi.w 8003998 <HAL_TIM_ConfigClockSource+0x168>
800388a: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
800388e: f000 8085 beq.w 800399c <HAL_TIM_ConfigClockSource+0x16c>
8003892: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8003896: d87f bhi.n 8003998 <HAL_TIM_ConfigClockSource+0x168>
8003898: 2b70 cmp r3, #112 ; 0x70
800389a: d01a beq.n 80038d2 <HAL_TIM_ConfigClockSource+0xa2>
800389c: 2b70 cmp r3, #112 ; 0x70
800389e: d87b bhi.n 8003998 <HAL_TIM_ConfigClockSource+0x168>
80038a0: 2b60 cmp r3, #96 ; 0x60
80038a2: d050 beq.n 8003946 <HAL_TIM_ConfigClockSource+0x116>
80038a4: 2b60 cmp r3, #96 ; 0x60
80038a6: d877 bhi.n 8003998 <HAL_TIM_ConfigClockSource+0x168>
80038a8: 2b50 cmp r3, #80 ; 0x50
80038aa: d03c beq.n 8003926 <HAL_TIM_ConfigClockSource+0xf6>
80038ac: 2b50 cmp r3, #80 ; 0x50
80038ae: d873 bhi.n 8003998 <HAL_TIM_ConfigClockSource+0x168>
80038b0: 2b40 cmp r3, #64 ; 0x40
80038b2: d058 beq.n 8003966 <HAL_TIM_ConfigClockSource+0x136>
80038b4: 2b40 cmp r3, #64 ; 0x40
80038b6: d86f bhi.n 8003998 <HAL_TIM_ConfigClockSource+0x168>
80038b8: 2b30 cmp r3, #48 ; 0x30
80038ba: d064 beq.n 8003986 <HAL_TIM_ConfigClockSource+0x156>
80038bc: 2b30 cmp r3, #48 ; 0x30
80038be: d86b bhi.n 8003998 <HAL_TIM_ConfigClockSource+0x168>
80038c0: 2b20 cmp r3, #32
80038c2: d060 beq.n 8003986 <HAL_TIM_ConfigClockSource+0x156>
80038c4: 2b20 cmp r3, #32
80038c6: d867 bhi.n 8003998 <HAL_TIM_ConfigClockSource+0x168>
80038c8: 2b00 cmp r3, #0
80038ca: d05c beq.n 8003986 <HAL_TIM_ConfigClockSource+0x156>
80038cc: 2b10 cmp r3, #16
80038ce: d05a beq.n 8003986 <HAL_TIM_ConfigClockSource+0x156>
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
break;
}
default:
break;
80038d0: e062 b.n 8003998 <HAL_TIM_ConfigClockSource+0x168>
TIM_ETR_SetConfig(htim->Instance,
80038d2: 687b ldr r3, [r7, #4]
80038d4: 6818 ldr r0, [r3, #0]
80038d6: 683b ldr r3, [r7, #0]
80038d8: 6899 ldr r1, [r3, #8]
80038da: 683b ldr r3, [r7, #0]
80038dc: 685a ldr r2, [r3, #4]
80038de: 683b ldr r3, [r7, #0]
80038e0: 68db ldr r3, [r3, #12]
80038e2: f000 faee bl 8003ec2 <TIM_ETR_SetConfig>
tmpsmcr = htim->Instance->SMCR;
80038e6: 687b ldr r3, [r7, #4]
80038e8: 681b ldr r3, [r3, #0]
80038ea: 689b ldr r3, [r3, #8]
80038ec: 60fb str r3, [r7, #12]
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
80038ee: 68fb ldr r3, [r7, #12]
80038f0: f043 0377 orr.w r3, r3, #119 ; 0x77
80038f4: 60fb str r3, [r7, #12]
htim->Instance->SMCR = tmpsmcr;
80038f6: 687b ldr r3, [r7, #4]
80038f8: 681b ldr r3, [r3, #0]
80038fa: 68fa ldr r2, [r7, #12]
80038fc: 609a str r2, [r3, #8]
break;
80038fe: e04e b.n 800399e <HAL_TIM_ConfigClockSource+0x16e>
TIM_ETR_SetConfig(htim->Instance,
8003900: 687b ldr r3, [r7, #4]
8003902: 6818 ldr r0, [r3, #0]
8003904: 683b ldr r3, [r7, #0]
8003906: 6899 ldr r1, [r3, #8]
8003908: 683b ldr r3, [r7, #0]
800390a: 685a ldr r2, [r3, #4]
800390c: 683b ldr r3, [r7, #0]
800390e: 68db ldr r3, [r3, #12]
8003910: f000 fad7 bl 8003ec2 <TIM_ETR_SetConfig>
htim->Instance->SMCR |= TIM_SMCR_ECE;
8003914: 687b ldr r3, [r7, #4]
8003916: 681b ldr r3, [r3, #0]
8003918: 689a ldr r2, [r3, #8]
800391a: 687b ldr r3, [r7, #4]
800391c: 681b ldr r3, [r3, #0]
800391e: f442 4280 orr.w r2, r2, #16384 ; 0x4000
8003922: 609a str r2, [r3, #8]
break;
8003924: e03b b.n 800399e <HAL_TIM_ConfigClockSource+0x16e>
TIM_TI1_ConfigInputStage(htim->Instance,
8003926: 687b ldr r3, [r7, #4]
8003928: 6818 ldr r0, [r3, #0]
800392a: 683b ldr r3, [r7, #0]
800392c: 6859 ldr r1, [r3, #4]
800392e: 683b ldr r3, [r7, #0]
8003930: 68db ldr r3, [r3, #12]
8003932: 461a mov r2, r3
8003934: f000 fa4e bl 8003dd4 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
8003938: 687b ldr r3, [r7, #4]
800393a: 681b ldr r3, [r3, #0]
800393c: 2150 movs r1, #80 ; 0x50
800393e: 4618 mov r0, r3
8003940: f000 faa5 bl 8003e8e <TIM_ITRx_SetConfig>
break;
8003944: e02b b.n 800399e <HAL_TIM_ConfigClockSource+0x16e>
TIM_TI2_ConfigInputStage(htim->Instance,
8003946: 687b ldr r3, [r7, #4]
8003948: 6818 ldr r0, [r3, #0]
800394a: 683b ldr r3, [r7, #0]
800394c: 6859 ldr r1, [r3, #4]
800394e: 683b ldr r3, [r7, #0]
8003950: 68db ldr r3, [r3, #12]
8003952: 461a mov r2, r3
8003954: f000 fa6c bl 8003e30 <TIM_TI2_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
8003958: 687b ldr r3, [r7, #4]
800395a: 681b ldr r3, [r3, #0]
800395c: 2160 movs r1, #96 ; 0x60
800395e: 4618 mov r0, r3
8003960: f000 fa95 bl 8003e8e <TIM_ITRx_SetConfig>
break;
8003964: e01b b.n 800399e <HAL_TIM_ConfigClockSource+0x16e>
TIM_TI1_ConfigInputStage(htim->Instance,
8003966: 687b ldr r3, [r7, #4]
8003968: 6818 ldr r0, [r3, #0]
800396a: 683b ldr r3, [r7, #0]
800396c: 6859 ldr r1, [r3, #4]
800396e: 683b ldr r3, [r7, #0]
8003970: 68db ldr r3, [r3, #12]
8003972: 461a mov r2, r3
8003974: f000 fa2e bl 8003dd4 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
8003978: 687b ldr r3, [r7, #4]
800397a: 681b ldr r3, [r3, #0]
800397c: 2140 movs r1, #64 ; 0x40
800397e: 4618 mov r0, r3
8003980: f000 fa85 bl 8003e8e <TIM_ITRx_SetConfig>
break;
8003984: e00b b.n 800399e <HAL_TIM_ConfigClockSource+0x16e>
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
8003986: 687b ldr r3, [r7, #4]
8003988: 681a ldr r2, [r3, #0]
800398a: 683b ldr r3, [r7, #0]
800398c: 681b ldr r3, [r3, #0]
800398e: 4619 mov r1, r3
8003990: 4610 mov r0, r2
8003992: f000 fa7c bl 8003e8e <TIM_ITRx_SetConfig>
break;
8003996: e002 b.n 800399e <HAL_TIM_ConfigClockSource+0x16e>
break;
8003998: bf00 nop
800399a: e000 b.n 800399e <HAL_TIM_ConfigClockSource+0x16e>
break;
800399c: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
800399e: 687b ldr r3, [r7, #4]
80039a0: 2201 movs r2, #1
80039a2: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
80039a6: 687b ldr r3, [r7, #4]
80039a8: 2200 movs r2, #0
80039aa: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
80039ae: 2300 movs r3, #0
}
80039b0: 4618 mov r0, r3
80039b2: 3710 adds r7, #16
80039b4: 46bd mov sp, r7
80039b6: bd80 pop {r7, pc}
080039b8 <HAL_TIM_OC_DelayElapsedCallback>:
* @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
80039b8: b480 push {r7}
80039ba: b083 sub sp, #12
80039bc: af00 add r7, sp, #0
80039be: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
80039c0: bf00 nop
80039c2: 370c adds r7, #12
80039c4: 46bd mov sp, r7
80039c6: bc80 pop {r7}
80039c8: 4770 bx lr
080039ca <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
80039ca: b480 push {r7}
80039cc: b083 sub sp, #12
80039ce: af00 add r7, sp, #0
80039d0: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
80039d2: bf00 nop
80039d4: 370c adds r7, #12
80039d6: 46bd mov sp, r7
80039d8: bc80 pop {r7}
80039da: 4770 bx lr
080039dc <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
80039dc: b480 push {r7}
80039de: b083 sub sp, #12
80039e0: af00 add r7, sp, #0
80039e2: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
80039e4: bf00 nop
80039e6: 370c adds r7, #12
80039e8: 46bd mov sp, r7
80039ea: bc80 pop {r7}
80039ec: 4770 bx lr
080039ee <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
80039ee: b480 push {r7}
80039f0: b083 sub sp, #12
80039f2: af00 add r7, sp, #0
80039f4: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
80039f6: bf00 nop
80039f8: 370c adds r7, #12
80039fa: 46bd mov sp, r7
80039fc: bc80 pop {r7}
80039fe: 4770 bx lr
08003a00 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
{
8003a00: b480 push {r7}
8003a02: b085 sub sp, #20
8003a04: af00 add r7, sp, #0
8003a06: 6078 str r0, [r7, #4]
8003a08: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
8003a0a: 687b ldr r3, [r7, #4]
8003a0c: 681b ldr r3, [r3, #0]
8003a0e: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8003a10: 687b ldr r3, [r7, #4]
8003a12: 4a29 ldr r2, [pc, #164] ; (8003ab8 <TIM_Base_SetConfig+0xb8>)
8003a14: 4293 cmp r3, r2
8003a16: d00b beq.n 8003a30 <TIM_Base_SetConfig+0x30>
8003a18: 687b ldr r3, [r7, #4]
8003a1a: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8003a1e: d007 beq.n 8003a30 <TIM_Base_SetConfig+0x30>
8003a20: 687b ldr r3, [r7, #4]
8003a22: 4a26 ldr r2, [pc, #152] ; (8003abc <TIM_Base_SetConfig+0xbc>)
8003a24: 4293 cmp r3, r2
8003a26: d003 beq.n 8003a30 <TIM_Base_SetConfig+0x30>
8003a28: 687b ldr r3, [r7, #4]
8003a2a: 4a25 ldr r2, [pc, #148] ; (8003ac0 <TIM_Base_SetConfig+0xc0>)
8003a2c: 4293 cmp r3, r2
8003a2e: d108 bne.n 8003a42 <TIM_Base_SetConfig+0x42>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
8003a30: 68fb ldr r3, [r7, #12]
8003a32: f023 0370 bic.w r3, r3, #112 ; 0x70
8003a36: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
8003a38: 683b ldr r3, [r7, #0]
8003a3a: 685b ldr r3, [r3, #4]
8003a3c: 68fa ldr r2, [r7, #12]
8003a3e: 4313 orrs r3, r2
8003a40: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
8003a42: 687b ldr r3, [r7, #4]
8003a44: 4a1c ldr r2, [pc, #112] ; (8003ab8 <TIM_Base_SetConfig+0xb8>)
8003a46: 4293 cmp r3, r2
8003a48: d00b beq.n 8003a62 <TIM_Base_SetConfig+0x62>
8003a4a: 687b ldr r3, [r7, #4]
8003a4c: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8003a50: d007 beq.n 8003a62 <TIM_Base_SetConfig+0x62>
8003a52: 687b ldr r3, [r7, #4]
8003a54: 4a19 ldr r2, [pc, #100] ; (8003abc <TIM_Base_SetConfig+0xbc>)
8003a56: 4293 cmp r3, r2
8003a58: d003 beq.n 8003a62 <TIM_Base_SetConfig+0x62>
8003a5a: 687b ldr r3, [r7, #4]
8003a5c: 4a18 ldr r2, [pc, #96] ; (8003ac0 <TIM_Base_SetConfig+0xc0>)
8003a5e: 4293 cmp r3, r2
8003a60: d108 bne.n 8003a74 <TIM_Base_SetConfig+0x74>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
8003a62: 68fb ldr r3, [r7, #12]
8003a64: f423 7340 bic.w r3, r3, #768 ; 0x300
8003a68: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
8003a6a: 683b ldr r3, [r7, #0]
8003a6c: 68db ldr r3, [r3, #12]
8003a6e: 68fa ldr r2, [r7, #12]
8003a70: 4313 orrs r3, r2
8003a72: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
8003a74: 68fb ldr r3, [r7, #12]
8003a76: f023 0280 bic.w r2, r3, #128 ; 0x80
8003a7a: 683b ldr r3, [r7, #0]
8003a7c: 695b ldr r3, [r3, #20]
8003a7e: 4313 orrs r3, r2
8003a80: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
8003a82: 687b ldr r3, [r7, #4]
8003a84: 68fa ldr r2, [r7, #12]
8003a86: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
8003a88: 683b ldr r3, [r7, #0]
8003a8a: 689a ldr r2, [r3, #8]
8003a8c: 687b ldr r3, [r7, #4]
8003a8e: 62da str r2, [r3, #44] ; 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
8003a90: 683b ldr r3, [r7, #0]
8003a92: 681a ldr r2, [r3, #0]
8003a94: 687b ldr r3, [r7, #4]
8003a96: 629a str r2, [r3, #40] ; 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
8003a98: 687b ldr r3, [r7, #4]
8003a9a: 4a07 ldr r2, [pc, #28] ; (8003ab8 <TIM_Base_SetConfig+0xb8>)
8003a9c: 4293 cmp r3, r2
8003a9e: d103 bne.n 8003aa8 <TIM_Base_SetConfig+0xa8>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
8003aa0: 683b ldr r3, [r7, #0]
8003aa2: 691a ldr r2, [r3, #16]
8003aa4: 687b ldr r3, [r7, #4]
8003aa6: 631a str r2, [r3, #48] ; 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
8003aa8: 687b ldr r3, [r7, #4]
8003aaa: 2201 movs r2, #1
8003aac: 615a str r2, [r3, #20]
}
8003aae: bf00 nop
8003ab0: 3714 adds r7, #20
8003ab2: 46bd mov sp, r7
8003ab4: bc80 pop {r7}
8003ab6: 4770 bx lr
8003ab8: 40012c00 .word 0x40012c00
8003abc: 40000400 .word 0x40000400
8003ac0: 40000800 .word 0x40000800
08003ac4 <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
8003ac4: b480 push {r7}
8003ac6: b087 sub sp, #28
8003ac8: af00 add r7, sp, #0
8003aca: 6078 str r0, [r7, #4]
8003acc: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
8003ace: 687b ldr r3, [r7, #4]
8003ad0: 6a1b ldr r3, [r3, #32]
8003ad2: f023 0201 bic.w r2, r3, #1
8003ad6: 687b ldr r3, [r7, #4]
8003ad8: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8003ada: 687b ldr r3, [r7, #4]
8003adc: 6a1b ldr r3, [r3, #32]
8003ade: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8003ae0: 687b ldr r3, [r7, #4]
8003ae2: 685b ldr r3, [r3, #4]
8003ae4: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8003ae6: 687b ldr r3, [r7, #4]
8003ae8: 699b ldr r3, [r3, #24]
8003aea: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
8003aec: 68fb ldr r3, [r7, #12]
8003aee: f023 0370 bic.w r3, r3, #112 ; 0x70
8003af2: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
8003af4: 68fb ldr r3, [r7, #12]
8003af6: f023 0303 bic.w r3, r3, #3
8003afa: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8003afc: 683b ldr r3, [r7, #0]
8003afe: 681b ldr r3, [r3, #0]
8003b00: 68fa ldr r2, [r7, #12]
8003b02: 4313 orrs r3, r2
8003b04: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
8003b06: 697b ldr r3, [r7, #20]
8003b08: f023 0302 bic.w r3, r3, #2
8003b0c: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
8003b0e: 683b ldr r3, [r7, #0]
8003b10: 689b ldr r3, [r3, #8]
8003b12: 697a ldr r2, [r7, #20]
8003b14: 4313 orrs r3, r2
8003b16: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
8003b18: 687b ldr r3, [r7, #4]
8003b1a: 4a1c ldr r2, [pc, #112] ; (8003b8c <TIM_OC1_SetConfig+0xc8>)
8003b1c: 4293 cmp r3, r2
8003b1e: d10c bne.n 8003b3a <TIM_OC1_SetConfig+0x76>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
8003b20: 697b ldr r3, [r7, #20]
8003b22: f023 0308 bic.w r3, r3, #8
8003b26: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
8003b28: 683b ldr r3, [r7, #0]
8003b2a: 68db ldr r3, [r3, #12]
8003b2c: 697a ldr r2, [r7, #20]
8003b2e: 4313 orrs r3, r2
8003b30: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
8003b32: 697b ldr r3, [r7, #20]
8003b34: f023 0304 bic.w r3, r3, #4
8003b38: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8003b3a: 687b ldr r3, [r7, #4]
8003b3c: 4a13 ldr r2, [pc, #76] ; (8003b8c <TIM_OC1_SetConfig+0xc8>)
8003b3e: 4293 cmp r3, r2
8003b40: d111 bne.n 8003b66 <TIM_OC1_SetConfig+0xa2>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
8003b42: 693b ldr r3, [r7, #16]
8003b44: f423 7380 bic.w r3, r3, #256 ; 0x100
8003b48: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS1N;
8003b4a: 693b ldr r3, [r7, #16]
8003b4c: f423 7300 bic.w r3, r3, #512 ; 0x200
8003b50: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
8003b52: 683b ldr r3, [r7, #0]
8003b54: 695b ldr r3, [r3, #20]
8003b56: 693a ldr r2, [r7, #16]
8003b58: 4313 orrs r3, r2
8003b5a: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
8003b5c: 683b ldr r3, [r7, #0]
8003b5e: 699b ldr r3, [r3, #24]
8003b60: 693a ldr r2, [r7, #16]
8003b62: 4313 orrs r3, r2
8003b64: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8003b66: 687b ldr r3, [r7, #4]
8003b68: 693a ldr r2, [r7, #16]
8003b6a: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8003b6c: 687b ldr r3, [r7, #4]
8003b6e: 68fa ldr r2, [r7, #12]
8003b70: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
8003b72: 683b ldr r3, [r7, #0]
8003b74: 685a ldr r2, [r3, #4]
8003b76: 687b ldr r3, [r7, #4]
8003b78: 635a str r2, [r3, #52] ; 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8003b7a: 687b ldr r3, [r7, #4]
8003b7c: 697a ldr r2, [r7, #20]
8003b7e: 621a str r2, [r3, #32]
}
8003b80: bf00 nop
8003b82: 371c adds r7, #28
8003b84: 46bd mov sp, r7
8003b86: bc80 pop {r7}
8003b88: 4770 bx lr
8003b8a: bf00 nop
8003b8c: 40012c00 .word 0x40012c00
08003b90 <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
8003b90: b480 push {r7}
8003b92: b087 sub sp, #28
8003b94: af00 add r7, sp, #0
8003b96: 6078 str r0, [r7, #4]
8003b98: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
8003b9a: 687b ldr r3, [r7, #4]
8003b9c: 6a1b ldr r3, [r3, #32]
8003b9e: f023 0210 bic.w r2, r3, #16
8003ba2: 687b ldr r3, [r7, #4]
8003ba4: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8003ba6: 687b ldr r3, [r7, #4]
8003ba8: 6a1b ldr r3, [r3, #32]
8003baa: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8003bac: 687b ldr r3, [r7, #4]
8003bae: 685b ldr r3, [r3, #4]
8003bb0: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8003bb2: 687b ldr r3, [r7, #4]
8003bb4: 699b ldr r3, [r3, #24]
8003bb6: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
8003bb8: 68fb ldr r3, [r7, #12]
8003bba: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8003bbe: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
8003bc0: 68fb ldr r3, [r7, #12]
8003bc2: f423 7340 bic.w r3, r3, #768 ; 0x300
8003bc6: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8003bc8: 683b ldr r3, [r7, #0]
8003bca: 681b ldr r3, [r3, #0]
8003bcc: 021b lsls r3, r3, #8
8003bce: 68fa ldr r2, [r7, #12]
8003bd0: 4313 orrs r3, r2
8003bd2: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
8003bd4: 697b ldr r3, [r7, #20]
8003bd6: f023 0320 bic.w r3, r3, #32
8003bda: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
8003bdc: 683b ldr r3, [r7, #0]
8003bde: 689b ldr r3, [r3, #8]
8003be0: 011b lsls r3, r3, #4
8003be2: 697a ldr r2, [r7, #20]
8003be4: 4313 orrs r3, r2
8003be6: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
8003be8: 687b ldr r3, [r7, #4]
8003bea: 4a1d ldr r2, [pc, #116] ; (8003c60 <TIM_OC2_SetConfig+0xd0>)
8003bec: 4293 cmp r3, r2
8003bee: d10d bne.n 8003c0c <TIM_OC2_SetConfig+0x7c>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
8003bf0: 697b ldr r3, [r7, #20]
8003bf2: f023 0380 bic.w r3, r3, #128 ; 0x80
8003bf6: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 4U);
8003bf8: 683b ldr r3, [r7, #0]
8003bfa: 68db ldr r3, [r3, #12]
8003bfc: 011b lsls r3, r3, #4
8003bfe: 697a ldr r2, [r7, #20]
8003c00: 4313 orrs r3, r2
8003c02: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
8003c04: 697b ldr r3, [r7, #20]
8003c06: f023 0340 bic.w r3, r3, #64 ; 0x40
8003c0a: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8003c0c: 687b ldr r3, [r7, #4]
8003c0e: 4a14 ldr r2, [pc, #80] ; (8003c60 <TIM_OC2_SetConfig+0xd0>)
8003c10: 4293 cmp r3, r2
8003c12: d113 bne.n 8003c3c <TIM_OC2_SetConfig+0xac>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
8003c14: 693b ldr r3, [r7, #16]
8003c16: f423 6380 bic.w r3, r3, #1024 ; 0x400
8003c1a: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS2N;
8003c1c: 693b ldr r3, [r7, #16]
8003c1e: f423 6300 bic.w r3, r3, #2048 ; 0x800
8003c22: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 2U);
8003c24: 683b ldr r3, [r7, #0]
8003c26: 695b ldr r3, [r3, #20]
8003c28: 009b lsls r3, r3, #2
8003c2a: 693a ldr r2, [r7, #16]
8003c2c: 4313 orrs r3, r2
8003c2e: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
8003c30: 683b ldr r3, [r7, #0]
8003c32: 699b ldr r3, [r3, #24]
8003c34: 009b lsls r3, r3, #2
8003c36: 693a ldr r2, [r7, #16]
8003c38: 4313 orrs r3, r2
8003c3a: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8003c3c: 687b ldr r3, [r7, #4]
8003c3e: 693a ldr r2, [r7, #16]
8003c40: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8003c42: 687b ldr r3, [r7, #4]
8003c44: 68fa ldr r2, [r7, #12]
8003c46: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
8003c48: 683b ldr r3, [r7, #0]
8003c4a: 685a ldr r2, [r3, #4]
8003c4c: 687b ldr r3, [r7, #4]
8003c4e: 639a str r2, [r3, #56] ; 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8003c50: 687b ldr r3, [r7, #4]
8003c52: 697a ldr r2, [r7, #20]
8003c54: 621a str r2, [r3, #32]
}
8003c56: bf00 nop
8003c58: 371c adds r7, #28
8003c5a: 46bd mov sp, r7
8003c5c: bc80 pop {r7}
8003c5e: 4770 bx lr
8003c60: 40012c00 .word 0x40012c00
08003c64 <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
8003c64: b480 push {r7}
8003c66: b087 sub sp, #28
8003c68: af00 add r7, sp, #0
8003c6a: 6078 str r0, [r7, #4]
8003c6c: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
8003c6e: 687b ldr r3, [r7, #4]
8003c70: 6a1b ldr r3, [r3, #32]
8003c72: f423 7280 bic.w r2, r3, #256 ; 0x100
8003c76: 687b ldr r3, [r7, #4]
8003c78: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8003c7a: 687b ldr r3, [r7, #4]
8003c7c: 6a1b ldr r3, [r3, #32]
8003c7e: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8003c80: 687b ldr r3, [r7, #4]
8003c82: 685b ldr r3, [r3, #4]
8003c84: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8003c86: 687b ldr r3, [r7, #4]
8003c88: 69db ldr r3, [r3, #28]
8003c8a: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
8003c8c: 68fb ldr r3, [r7, #12]
8003c8e: f023 0370 bic.w r3, r3, #112 ; 0x70
8003c92: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
8003c94: 68fb ldr r3, [r7, #12]
8003c96: f023 0303 bic.w r3, r3, #3
8003c9a: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8003c9c: 683b ldr r3, [r7, #0]
8003c9e: 681b ldr r3, [r3, #0]
8003ca0: 68fa ldr r2, [r7, #12]
8003ca2: 4313 orrs r3, r2
8003ca4: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
8003ca6: 697b ldr r3, [r7, #20]
8003ca8: f423 7300 bic.w r3, r3, #512 ; 0x200
8003cac: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
8003cae: 683b ldr r3, [r7, #0]
8003cb0: 689b ldr r3, [r3, #8]
8003cb2: 021b lsls r3, r3, #8
8003cb4: 697a ldr r2, [r7, #20]
8003cb6: 4313 orrs r3, r2
8003cb8: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
8003cba: 687b ldr r3, [r7, #4]
8003cbc: 4a1d ldr r2, [pc, #116] ; (8003d34 <TIM_OC3_SetConfig+0xd0>)
8003cbe: 4293 cmp r3, r2
8003cc0: d10d bne.n 8003cde <TIM_OC3_SetConfig+0x7a>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
8003cc2: 697b ldr r3, [r7, #20]
8003cc4: f423 6300 bic.w r3, r3, #2048 ; 0x800
8003cc8: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
8003cca: 683b ldr r3, [r7, #0]
8003ccc: 68db ldr r3, [r3, #12]
8003cce: 021b lsls r3, r3, #8
8003cd0: 697a ldr r2, [r7, #20]
8003cd2: 4313 orrs r3, r2
8003cd4: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
8003cd6: 697b ldr r3, [r7, #20]
8003cd8: f423 6380 bic.w r3, r3, #1024 ; 0x400
8003cdc: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8003cde: 687b ldr r3, [r7, #4]
8003ce0: 4a14 ldr r2, [pc, #80] ; (8003d34 <TIM_OC3_SetConfig+0xd0>)
8003ce2: 4293 cmp r3, r2
8003ce4: d113 bne.n 8003d0e <TIM_OC3_SetConfig+0xaa>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
8003ce6: 693b ldr r3, [r7, #16]
8003ce8: f423 5380 bic.w r3, r3, #4096 ; 0x1000
8003cec: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS3N;
8003cee: 693b ldr r3, [r7, #16]
8003cf0: f423 5300 bic.w r3, r3, #8192 ; 0x2000
8003cf4: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
8003cf6: 683b ldr r3, [r7, #0]
8003cf8: 695b ldr r3, [r3, #20]
8003cfa: 011b lsls r3, r3, #4
8003cfc: 693a ldr r2, [r7, #16]
8003cfe: 4313 orrs r3, r2
8003d00: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
8003d02: 683b ldr r3, [r7, #0]
8003d04: 699b ldr r3, [r3, #24]
8003d06: 011b lsls r3, r3, #4
8003d08: 693a ldr r2, [r7, #16]
8003d0a: 4313 orrs r3, r2
8003d0c: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8003d0e: 687b ldr r3, [r7, #4]
8003d10: 693a ldr r2, [r7, #16]
8003d12: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8003d14: 687b ldr r3, [r7, #4]
8003d16: 68fa ldr r2, [r7, #12]
8003d18: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
8003d1a: 683b ldr r3, [r7, #0]
8003d1c: 685a ldr r2, [r3, #4]
8003d1e: 687b ldr r3, [r7, #4]
8003d20: 63da str r2, [r3, #60] ; 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8003d22: 687b ldr r3, [r7, #4]
8003d24: 697a ldr r2, [r7, #20]
8003d26: 621a str r2, [r3, #32]
}
8003d28: bf00 nop
8003d2a: 371c adds r7, #28
8003d2c: 46bd mov sp, r7
8003d2e: bc80 pop {r7}
8003d30: 4770 bx lr
8003d32: bf00 nop
8003d34: 40012c00 .word 0x40012c00
08003d38 <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
8003d38: b480 push {r7}
8003d3a: b087 sub sp, #28
8003d3c: af00 add r7, sp, #0
8003d3e: 6078 str r0, [r7, #4]
8003d40: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
8003d42: 687b ldr r3, [r7, #4]
8003d44: 6a1b ldr r3, [r3, #32]
8003d46: f423 5280 bic.w r2, r3, #4096 ; 0x1000
8003d4a: 687b ldr r3, [r7, #4]
8003d4c: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8003d4e: 687b ldr r3, [r7, #4]
8003d50: 6a1b ldr r3, [r3, #32]
8003d52: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8003d54: 687b ldr r3, [r7, #4]
8003d56: 685b ldr r3, [r3, #4]
8003d58: 617b str r3, [r7, #20]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8003d5a: 687b ldr r3, [r7, #4]
8003d5c: 69db ldr r3, [r3, #28]
8003d5e: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
8003d60: 68fb ldr r3, [r7, #12]
8003d62: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8003d66: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
8003d68: 68fb ldr r3, [r7, #12]
8003d6a: f423 7340 bic.w r3, r3, #768 ; 0x300
8003d6e: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8003d70: 683b ldr r3, [r7, #0]
8003d72: 681b ldr r3, [r3, #0]
8003d74: 021b lsls r3, r3, #8
8003d76: 68fa ldr r2, [r7, #12]
8003d78: 4313 orrs r3, r2
8003d7a: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
8003d7c: 693b ldr r3, [r7, #16]
8003d7e: f423 5300 bic.w r3, r3, #8192 ; 0x2000
8003d82: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
8003d84: 683b ldr r3, [r7, #0]
8003d86: 689b ldr r3, [r3, #8]
8003d88: 031b lsls r3, r3, #12
8003d8a: 693a ldr r2, [r7, #16]
8003d8c: 4313 orrs r3, r2
8003d8e: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
8003d90: 687b ldr r3, [r7, #4]
8003d92: 4a0f ldr r2, [pc, #60] ; (8003dd0 <TIM_OC4_SetConfig+0x98>)
8003d94: 4293 cmp r3, r2
8003d96: d109 bne.n 8003dac <TIM_OC4_SetConfig+0x74>
{
/* Check parameters */
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
8003d98: 697b ldr r3, [r7, #20]
8003d9a: f423 4380 bic.w r3, r3, #16384 ; 0x4000
8003d9e: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
8003da0: 683b ldr r3, [r7, #0]
8003da2: 695b ldr r3, [r3, #20]
8003da4: 019b lsls r3, r3, #6
8003da6: 697a ldr r2, [r7, #20]
8003da8: 4313 orrs r3, r2
8003daa: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8003dac: 687b ldr r3, [r7, #4]
8003dae: 697a ldr r2, [r7, #20]
8003db0: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8003db2: 687b ldr r3, [r7, #4]
8003db4: 68fa ldr r2, [r7, #12]
8003db6: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
8003db8: 683b ldr r3, [r7, #0]
8003dba: 685a ldr r2, [r3, #4]
8003dbc: 687b ldr r3, [r7, #4]
8003dbe: 641a str r2, [r3, #64] ; 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8003dc0: 687b ldr r3, [r7, #4]
8003dc2: 693a ldr r2, [r7, #16]
8003dc4: 621a str r2, [r3, #32]
}
8003dc6: bf00 nop
8003dc8: 371c adds r7, #28
8003dca: 46bd mov sp, r7
8003dcc: bc80 pop {r7}
8003dce: 4770 bx lr
8003dd0: 40012c00 .word 0x40012c00
08003dd4 <TIM_TI1_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8003dd4: b480 push {r7}
8003dd6: b087 sub sp, #28
8003dd8: af00 add r7, sp, #0
8003dda: 60f8 str r0, [r7, #12]
8003ddc: 60b9 str r1, [r7, #8]
8003dde: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
8003de0: 68fb ldr r3, [r7, #12]
8003de2: 6a1b ldr r3, [r3, #32]
8003de4: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC1E;
8003de6: 68fb ldr r3, [r7, #12]
8003de8: 6a1b ldr r3, [r3, #32]
8003dea: f023 0201 bic.w r2, r3, #1
8003dee: 68fb ldr r3, [r7, #12]
8003df0: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8003df2: 68fb ldr r3, [r7, #12]
8003df4: 699b ldr r3, [r3, #24]
8003df6: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
8003df8: 693b ldr r3, [r7, #16]
8003dfa: f023 03f0 bic.w r3, r3, #240 ; 0xf0
8003dfe: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 4U);
8003e00: 687b ldr r3, [r7, #4]
8003e02: 011b lsls r3, r3, #4
8003e04: 693a ldr r2, [r7, #16]
8003e06: 4313 orrs r3, r2
8003e08: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
8003e0a: 697b ldr r3, [r7, #20]
8003e0c: f023 030a bic.w r3, r3, #10
8003e10: 617b str r3, [r7, #20]
tmpccer |= TIM_ICPolarity;
8003e12: 697a ldr r2, [r7, #20]
8003e14: 68bb ldr r3, [r7, #8]
8003e16: 4313 orrs r3, r2
8003e18: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
8003e1a: 68fb ldr r3, [r7, #12]
8003e1c: 693a ldr r2, [r7, #16]
8003e1e: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8003e20: 68fb ldr r3, [r7, #12]
8003e22: 697a ldr r2, [r7, #20]
8003e24: 621a str r2, [r3, #32]
}
8003e26: bf00 nop
8003e28: 371c adds r7, #28
8003e2a: 46bd mov sp, r7
8003e2c: bc80 pop {r7}
8003e2e: 4770 bx lr
08003e30 <TIM_TI2_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8003e30: b480 push {r7}
8003e32: b087 sub sp, #28
8003e34: af00 add r7, sp, #0
8003e36: 60f8 str r0, [r7, #12]
8003e38: 60b9 str r1, [r7, #8]
8003e3a: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
8003e3c: 68fb ldr r3, [r7, #12]
8003e3e: 6a1b ldr r3, [r3, #32]
8003e40: f023 0210 bic.w r2, r3, #16
8003e44: 68fb ldr r3, [r7, #12]
8003e46: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8003e48: 68fb ldr r3, [r7, #12]
8003e4a: 699b ldr r3, [r3, #24]
8003e4c: 617b str r3, [r7, #20]
tmpccer = TIMx->CCER;
8003e4e: 68fb ldr r3, [r7, #12]
8003e50: 6a1b ldr r3, [r3, #32]
8003e52: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
8003e54: 697b ldr r3, [r7, #20]
8003e56: f423 4370 bic.w r3, r3, #61440 ; 0xf000
8003e5a: 617b str r3, [r7, #20]
tmpccmr1 |= (TIM_ICFilter << 12U);
8003e5c: 687b ldr r3, [r7, #4]
8003e5e: 031b lsls r3, r3, #12
8003e60: 697a ldr r2, [r7, #20]
8003e62: 4313 orrs r3, r2
8003e64: 617b str r3, [r7, #20]
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
8003e66: 693b ldr r3, [r7, #16]
8003e68: f023 03a0 bic.w r3, r3, #160 ; 0xa0
8003e6c: 613b str r3, [r7, #16]
tmpccer |= (TIM_ICPolarity << 4U);
8003e6e: 68bb ldr r3, [r7, #8]
8003e70: 011b lsls r3, r3, #4
8003e72: 693a ldr r2, [r7, #16]
8003e74: 4313 orrs r3, r2
8003e76: 613b str r3, [r7, #16]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
8003e78: 68fb ldr r3, [r7, #12]
8003e7a: 697a ldr r2, [r7, #20]
8003e7c: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8003e7e: 68fb ldr r3, [r7, #12]
8003e80: 693a ldr r2, [r7, #16]
8003e82: 621a str r2, [r3, #32]
}
8003e84: bf00 nop
8003e86: 371c adds r7, #28
8003e88: 46bd mov sp, r7
8003e8a: bc80 pop {r7}
8003e8c: 4770 bx lr
08003e8e <TIM_ITRx_SetConfig>:
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
* @arg TIM_TS_ETRF: External Trigger input
* @retval None
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
8003e8e: b480 push {r7}
8003e90: b085 sub sp, #20
8003e92: af00 add r7, sp, #0
8003e94: 6078 str r0, [r7, #4]
8003e96: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
8003e98: 687b ldr r3, [r7, #4]
8003e9a: 689b ldr r3, [r3, #8]
8003e9c: 60fb str r3, [r7, #12]
/* Reset the TS Bits */
tmpsmcr &= ~TIM_SMCR_TS;
8003e9e: 68fb ldr r3, [r7, #12]
8003ea0: f023 0370 bic.w r3, r3, #112 ; 0x70
8003ea4: 60fb str r3, [r7, #12]
/* Set the Input Trigger source and the slave mode*/
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
8003ea6: 683a ldr r2, [r7, #0]
8003ea8: 68fb ldr r3, [r7, #12]
8003eaa: 4313 orrs r3, r2
8003eac: f043 0307 orr.w r3, r3, #7
8003eb0: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8003eb2: 687b ldr r3, [r7, #4]
8003eb4: 68fa ldr r2, [r7, #12]
8003eb6: 609a str r2, [r3, #8]
}
8003eb8: bf00 nop
8003eba: 3714 adds r7, #20
8003ebc: 46bd mov sp, r7
8003ebe: bc80 pop {r7}
8003ec0: 4770 bx lr
08003ec2 <TIM_ETR_SetConfig>:
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
8003ec2: b480 push {r7}
8003ec4: b087 sub sp, #28
8003ec6: af00 add r7, sp, #0
8003ec8: 60f8 str r0, [r7, #12]
8003eca: 60b9 str r1, [r7, #8]
8003ecc: 607a str r2, [r7, #4]
8003ece: 603b str r3, [r7, #0]
uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
8003ed0: 68fb ldr r3, [r7, #12]
8003ed2: 689b ldr r3, [r3, #8]
8003ed4: 617b str r3, [r7, #20]
/* Reset the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8003ed6: 697b ldr r3, [r7, #20]
8003ed8: f423 437f bic.w r3, r3, #65280 ; 0xff00
8003edc: 617b str r3, [r7, #20]
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
8003ede: 683b ldr r3, [r7, #0]
8003ee0: 021a lsls r2, r3, #8
8003ee2: 687b ldr r3, [r7, #4]
8003ee4: 431a orrs r2, r3
8003ee6: 68bb ldr r3, [r7, #8]
8003ee8: 4313 orrs r3, r2
8003eea: 697a ldr r2, [r7, #20]
8003eec: 4313 orrs r3, r2
8003eee: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8003ef0: 68fb ldr r3, [r7, #12]
8003ef2: 697a ldr r2, [r7, #20]
8003ef4: 609a str r2, [r3, #8]
}
8003ef6: bf00 nop
8003ef8: 371c adds r7, #28
8003efa: 46bd mov sp, r7
8003efc: bc80 pop {r7}
8003efe: 4770 bx lr
08003f00 <TIM_CCxChannelCmd>:
* @param ChannelState specifies the TIM Channel CCxE bit new state.
* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
* @retval None
*/
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
{
8003f00: b480 push {r7}
8003f02: b087 sub sp, #28
8003f04: af00 add r7, sp, #0
8003f06: 60f8 str r0, [r7, #12]
8003f08: 60b9 str r1, [r7, #8]
8003f0a: 607a str r2, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
assert_param(IS_TIM_CHANNELS(Channel));
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
8003f0c: 68bb ldr r3, [r7, #8]
8003f0e: f003 031f and.w r3, r3, #31
8003f12: 2201 movs r2, #1
8003f14: fa02 f303 lsl.w r3, r2, r3
8003f18: 617b str r3, [r7, #20]
/* Reset the CCxE Bit */
TIMx->CCER &= ~tmp;
8003f1a: 68fb ldr r3, [r7, #12]
8003f1c: 6a1a ldr r2, [r3, #32]
8003f1e: 697b ldr r3, [r7, #20]
8003f20: 43db mvns r3, r3
8003f22: 401a ands r2, r3
8003f24: 68fb ldr r3, [r7, #12]
8003f26: 621a str r2, [r3, #32]
/* Set or reset the CCxE Bit */
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
8003f28: 68fb ldr r3, [r7, #12]
8003f2a: 6a1a ldr r2, [r3, #32]
8003f2c: 68bb ldr r3, [r7, #8]
8003f2e: f003 031f and.w r3, r3, #31
8003f32: 6879 ldr r1, [r7, #4]
8003f34: fa01 f303 lsl.w r3, r1, r3
8003f38: 431a orrs r2, r3
8003f3a: 68fb ldr r3, [r7, #12]
8003f3c: 621a str r2, [r3, #32]
}
8003f3e: bf00 nop
8003f40: 371c adds r7, #28
8003f42: 46bd mov sp, r7
8003f44: bc80 pop {r7}
8003f46: 4770 bx lr
08003f48 <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
TIM_MasterConfigTypeDef *sMasterConfig)
{
8003f48: b480 push {r7}
8003f4a: b085 sub sp, #20
8003f4c: af00 add r7, sp, #0
8003f4e: 6078 str r0, [r7, #4]
8003f50: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
8003f52: 687b ldr r3, [r7, #4]
8003f54: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8003f58: 2b01 cmp r3, #1
8003f5a: d101 bne.n 8003f60 <HAL_TIMEx_MasterConfigSynchronization+0x18>
8003f5c: 2302 movs r3, #2
8003f5e: e046 b.n 8003fee <HAL_TIMEx_MasterConfigSynchronization+0xa6>
8003f60: 687b ldr r3, [r7, #4]
8003f62: 2201 movs r2, #1
8003f64: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
8003f68: 687b ldr r3, [r7, #4]
8003f6a: 2202 movs r2, #2
8003f6c: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
8003f70: 687b ldr r3, [r7, #4]
8003f72: 681b ldr r3, [r3, #0]
8003f74: 685b ldr r3, [r3, #4]
8003f76: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
8003f78: 687b ldr r3, [r7, #4]
8003f7a: 681b ldr r3, [r3, #0]
8003f7c: 689b ldr r3, [r3, #8]
8003f7e: 60bb str r3, [r7, #8]
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
8003f80: 68fb ldr r3, [r7, #12]
8003f82: f023 0370 bic.w r3, r3, #112 ; 0x70
8003f86: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
8003f88: 683b ldr r3, [r7, #0]
8003f8a: 681b ldr r3, [r3, #0]
8003f8c: 68fa ldr r2, [r7, #12]
8003f8e: 4313 orrs r3, r2
8003f90: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
8003f92: 687b ldr r3, [r7, #4]
8003f94: 681b ldr r3, [r3, #0]
8003f96: 68fa ldr r2, [r7, #12]
8003f98: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8003f9a: 687b ldr r3, [r7, #4]
8003f9c: 681b ldr r3, [r3, #0]
8003f9e: 4a16 ldr r2, [pc, #88] ; (8003ff8 <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
8003fa0: 4293 cmp r3, r2
8003fa2: d00e beq.n 8003fc2 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
8003fa4: 687b ldr r3, [r7, #4]
8003fa6: 681b ldr r3, [r3, #0]
8003fa8: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8003fac: d009 beq.n 8003fc2 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
8003fae: 687b ldr r3, [r7, #4]
8003fb0: 681b ldr r3, [r3, #0]
8003fb2: 4a12 ldr r2, [pc, #72] ; (8003ffc <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
8003fb4: 4293 cmp r3, r2
8003fb6: d004 beq.n 8003fc2 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
8003fb8: 687b ldr r3, [r7, #4]
8003fba: 681b ldr r3, [r3, #0]
8003fbc: 4a10 ldr r2, [pc, #64] ; (8004000 <HAL_TIMEx_MasterConfigSynchronization+0xb8>)
8003fbe: 4293 cmp r3, r2
8003fc0: d10c bne.n 8003fdc <HAL_TIMEx_MasterConfigSynchronization+0x94>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
8003fc2: 68bb ldr r3, [r7, #8]
8003fc4: f023 0380 bic.w r3, r3, #128 ; 0x80
8003fc8: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
8003fca: 683b ldr r3, [r7, #0]
8003fcc: 685b ldr r3, [r3, #4]
8003fce: 68ba ldr r2, [r7, #8]
8003fd0: 4313 orrs r3, r2
8003fd2: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8003fd4: 687b ldr r3, [r7, #4]
8003fd6: 681b ldr r3, [r3, #0]
8003fd8: 68ba ldr r2, [r7, #8]
8003fda: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
8003fdc: 687b ldr r3, [r7, #4]
8003fde: 2201 movs r2, #1
8003fe0: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
8003fe4: 687b ldr r3, [r7, #4]
8003fe6: 2200 movs r2, #0
8003fe8: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
8003fec: 2300 movs r3, #0
}
8003fee: 4618 mov r0, r3
8003ff0: 3714 adds r7, #20
8003ff2: 46bd mov sp, r7
8003ff4: bc80 pop {r7}
8003ff6: 4770 bx lr
8003ff8: 40012c00 .word 0x40012c00
8003ffc: 40000400 .word 0x40000400
8004000: 40000800 .word 0x40000800
08004004 <HAL_TIMEx_CommutCallback>:
* @brief Hall commutation changed callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
8004004: b480 push {r7}
8004006: b083 sub sp, #12
8004008: af00 add r7, sp, #0
800400a: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_CommutCallback could be implemented in the user file
*/
}
800400c: bf00 nop
800400e: 370c adds r7, #12
8004010: 46bd mov sp, r7
8004012: bc80 pop {r7}
8004014: 4770 bx lr
08004016 <HAL_TIMEx_BreakCallback>:
* @brief Hall Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
8004016: b480 push {r7}
8004018: b083 sub sp, #12
800401a: af00 add r7, sp, #0
800401c: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
800401e: bf00 nop
8004020: 370c adds r7, #12
8004022: 46bd mov sp, r7
8004024: bc80 pop {r7}
8004026: 4770 bx lr
08004028 <HAL_UART_Init>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
8004028: b580 push {r7, lr}
800402a: b082 sub sp, #8
800402c: af00 add r7, sp, #0
800402e: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
8004030: 687b ldr r3, [r7, #4]
8004032: 2b00 cmp r3, #0
8004034: d101 bne.n 800403a <HAL_UART_Init+0x12>
{
return HAL_ERROR;
8004036: 2301 movs r3, #1
8004038: e03f b.n 80040ba <HAL_UART_Init+0x92>
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
#if defined(USART_CR1_OVER8)
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
#endif /* USART_CR1_OVER8 */
if (huart->gState == HAL_UART_STATE_RESET)
800403a: 687b ldr r3, [r7, #4]
800403c: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8004040: b2db uxtb r3, r3
8004042: 2b00 cmp r3, #0
8004044: d106 bne.n 8004054 <HAL_UART_Init+0x2c>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
8004046: 687b ldr r3, [r7, #4]
8004048: 2200 movs r2, #0
800404a: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
800404e: 6878 ldr r0, [r7, #4]
8004050: f7fd fa02 bl 8001458 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
8004054: 687b ldr r3, [r7, #4]
8004056: 2224 movs r2, #36 ; 0x24
8004058: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Disable the peripheral */
__HAL_UART_DISABLE(huart);
800405c: 687b ldr r3, [r7, #4]
800405e: 681b ldr r3, [r3, #0]
8004060: 68da ldr r2, [r3, #12]
8004062: 687b ldr r3, [r7, #4]
8004064: 681b ldr r3, [r3, #0]
8004066: f422 5200 bic.w r2, r2, #8192 ; 0x2000
800406a: 60da str r2, [r3, #12]
/* Set the UART Communication parameters */
UART_SetConfig(huart);
800406c: 6878 ldr r0, [r7, #4]
800406e: f000 fdb3 bl 8004bd8 <UART_SetConfig>
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
8004072: 687b ldr r3, [r7, #4]
8004074: 681b ldr r3, [r3, #0]
8004076: 691a ldr r2, [r3, #16]
8004078: 687b ldr r3, [r7, #4]
800407a: 681b ldr r3, [r3, #0]
800407c: f422 4290 bic.w r2, r2, #18432 ; 0x4800
8004080: 611a str r2, [r3, #16]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
8004082: 687b ldr r3, [r7, #4]
8004084: 681b ldr r3, [r3, #0]
8004086: 695a ldr r2, [r3, #20]
8004088: 687b ldr r3, [r7, #4]
800408a: 681b ldr r3, [r3, #0]
800408c: f022 022a bic.w r2, r2, #42 ; 0x2a
8004090: 615a str r2, [r3, #20]
/* Enable the peripheral */
__HAL_UART_ENABLE(huart);
8004092: 687b ldr r3, [r7, #4]
8004094: 681b ldr r3, [r3, #0]
8004096: 68da ldr r2, [r3, #12]
8004098: 687b ldr r3, [r7, #4]
800409a: 681b ldr r3, [r3, #0]
800409c: f442 5200 orr.w r2, r2, #8192 ; 0x2000
80040a0: 60da str r2, [r3, #12]
/* Initialize the UART state */
huart->ErrorCode = HAL_UART_ERROR_NONE;
80040a2: 687b ldr r3, [r7, #4]
80040a4: 2200 movs r2, #0
80040a6: 641a str r2, [r3, #64] ; 0x40
huart->gState = HAL_UART_STATE_READY;
80040a8: 687b ldr r3, [r7, #4]
80040aa: 2220 movs r2, #32
80040ac: f883 203d strb.w r2, [r3, #61] ; 0x3d
huart->RxState = HAL_UART_STATE_READY;
80040b0: 687b ldr r3, [r7, #4]
80040b2: 2220 movs r2, #32
80040b4: f883 203e strb.w r2, [r3, #62] ; 0x3e
return HAL_OK;
80040b8: 2300 movs r3, #0
}
80040ba: 4618 mov r0, r3
80040bc: 3708 adds r7, #8
80040be: 46bd mov sp, r7
80040c0: bd80 pop {r7, pc}
080040c2 <HAL_UART_Transmit>:
* @param Size Amount of data elements (u8 or u16) to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
80040c2: b580 push {r7, lr}
80040c4: b08a sub sp, #40 ; 0x28
80040c6: af02 add r7, sp, #8
80040c8: 60f8 str r0, [r7, #12]
80040ca: 60b9 str r1, [r7, #8]
80040cc: 603b str r3, [r7, #0]
80040ce: 4613 mov r3, r2
80040d0: 80fb strh r3, [r7, #6]
uint8_t *pdata8bits;
uint16_t *pdata16bits;
uint32_t tickstart = 0U;
80040d2: 2300 movs r3, #0
80040d4: 617b str r3, [r7, #20]
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
80040d6: 68fb ldr r3, [r7, #12]
80040d8: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
80040dc: b2db uxtb r3, r3
80040de: 2b20 cmp r3, #32
80040e0: d17c bne.n 80041dc <HAL_UART_Transmit+0x11a>
{
if ((pData == NULL) || (Size == 0U))
80040e2: 68bb ldr r3, [r7, #8]
80040e4: 2b00 cmp r3, #0
80040e6: d002 beq.n 80040ee <HAL_UART_Transmit+0x2c>
80040e8: 88fb ldrh r3, [r7, #6]
80040ea: 2b00 cmp r3, #0
80040ec: d101 bne.n 80040f2 <HAL_UART_Transmit+0x30>
{
return HAL_ERROR;
80040ee: 2301 movs r3, #1
80040f0: e075 b.n 80041de <HAL_UART_Transmit+0x11c>
}
/* Process Locked */
__HAL_LOCK(huart);
80040f2: 68fb ldr r3, [r7, #12]
80040f4: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
80040f8: 2b01 cmp r3, #1
80040fa: d101 bne.n 8004100 <HAL_UART_Transmit+0x3e>
80040fc: 2302 movs r3, #2
80040fe: e06e b.n 80041de <HAL_UART_Transmit+0x11c>
8004100: 68fb ldr r3, [r7, #12]
8004102: 2201 movs r2, #1
8004104: f883 203c strb.w r2, [r3, #60] ; 0x3c
huart->ErrorCode = HAL_UART_ERROR_NONE;
8004108: 68fb ldr r3, [r7, #12]
800410a: 2200 movs r2, #0
800410c: 641a str r2, [r3, #64] ; 0x40
huart->gState = HAL_UART_STATE_BUSY_TX;
800410e: 68fb ldr r3, [r7, #12]
8004110: 2221 movs r2, #33 ; 0x21
8004112: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
8004116: f7fd fbb7 bl 8001888 <HAL_GetTick>
800411a: 6178 str r0, [r7, #20]
huart->TxXferSize = Size;
800411c: 68fb ldr r3, [r7, #12]
800411e: 88fa ldrh r2, [r7, #6]
8004120: 849a strh r2, [r3, #36] ; 0x24
huart->TxXferCount = Size;
8004122: 68fb ldr r3, [r7, #12]
8004124: 88fa ldrh r2, [r7, #6]
8004126: 84da strh r2, [r3, #38] ; 0x26
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8004128: 68fb ldr r3, [r7, #12]
800412a: 689b ldr r3, [r3, #8]
800412c: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8004130: d108 bne.n 8004144 <HAL_UART_Transmit+0x82>
8004132: 68fb ldr r3, [r7, #12]
8004134: 691b ldr r3, [r3, #16]
8004136: 2b00 cmp r3, #0
8004138: d104 bne.n 8004144 <HAL_UART_Transmit+0x82>
{
pdata8bits = NULL;
800413a: 2300 movs r3, #0
800413c: 61fb str r3, [r7, #28]
pdata16bits = (uint16_t *) pData;
800413e: 68bb ldr r3, [r7, #8]
8004140: 61bb str r3, [r7, #24]
8004142: e003 b.n 800414c <HAL_UART_Transmit+0x8a>
}
else
{
pdata8bits = pData;
8004144: 68bb ldr r3, [r7, #8]
8004146: 61fb str r3, [r7, #28]
pdata16bits = NULL;
8004148: 2300 movs r3, #0
800414a: 61bb str r3, [r7, #24]
}
/* Process Unlocked */
__HAL_UNLOCK(huart);
800414c: 68fb ldr r3, [r7, #12]
800414e: 2200 movs r2, #0
8004150: f883 203c strb.w r2, [r3, #60] ; 0x3c
while (huart->TxXferCount > 0U)
8004154: e02a b.n 80041ac <HAL_UART_Transmit+0xea>
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
8004156: 683b ldr r3, [r7, #0]
8004158: 9300 str r3, [sp, #0]
800415a: 697b ldr r3, [r7, #20]
800415c: 2200 movs r2, #0
800415e: 2180 movs r1, #128 ; 0x80
8004160: 68f8 ldr r0, [r7, #12]
8004162: f000 fb71 bl 8004848 <UART_WaitOnFlagUntilTimeout>
8004166: 4603 mov r3, r0
8004168: 2b00 cmp r3, #0
800416a: d001 beq.n 8004170 <HAL_UART_Transmit+0xae>
{
return HAL_TIMEOUT;
800416c: 2303 movs r3, #3
800416e: e036 b.n 80041de <HAL_UART_Transmit+0x11c>
}
if (pdata8bits == NULL)
8004170: 69fb ldr r3, [r7, #28]
8004172: 2b00 cmp r3, #0
8004174: d10b bne.n 800418e <HAL_UART_Transmit+0xcc>
{
huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU);
8004176: 69bb ldr r3, [r7, #24]
8004178: 881b ldrh r3, [r3, #0]
800417a: 461a mov r2, r3
800417c: 68fb ldr r3, [r7, #12]
800417e: 681b ldr r3, [r3, #0]
8004180: f3c2 0208 ubfx r2, r2, #0, #9
8004184: 605a str r2, [r3, #4]
pdata16bits++;
8004186: 69bb ldr r3, [r7, #24]
8004188: 3302 adds r3, #2
800418a: 61bb str r3, [r7, #24]
800418c: e007 b.n 800419e <HAL_UART_Transmit+0xdc>
}
else
{
huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU);
800418e: 69fb ldr r3, [r7, #28]
8004190: 781a ldrb r2, [r3, #0]
8004192: 68fb ldr r3, [r7, #12]
8004194: 681b ldr r3, [r3, #0]
8004196: 605a str r2, [r3, #4]
pdata8bits++;
8004198: 69fb ldr r3, [r7, #28]
800419a: 3301 adds r3, #1
800419c: 61fb str r3, [r7, #28]
}
huart->TxXferCount--;
800419e: 68fb ldr r3, [r7, #12]
80041a0: 8cdb ldrh r3, [r3, #38] ; 0x26
80041a2: b29b uxth r3, r3
80041a4: 3b01 subs r3, #1
80041a6: b29a uxth r2, r3
80041a8: 68fb ldr r3, [r7, #12]
80041aa: 84da strh r2, [r3, #38] ; 0x26
while (huart->TxXferCount > 0U)
80041ac: 68fb ldr r3, [r7, #12]
80041ae: 8cdb ldrh r3, [r3, #38] ; 0x26
80041b0: b29b uxth r3, r3
80041b2: 2b00 cmp r3, #0
80041b4: d1cf bne.n 8004156 <HAL_UART_Transmit+0x94>
}
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
80041b6: 683b ldr r3, [r7, #0]
80041b8: 9300 str r3, [sp, #0]
80041ba: 697b ldr r3, [r7, #20]
80041bc: 2200 movs r2, #0
80041be: 2140 movs r1, #64 ; 0x40
80041c0: 68f8 ldr r0, [r7, #12]
80041c2: f000 fb41 bl 8004848 <UART_WaitOnFlagUntilTimeout>
80041c6: 4603 mov r3, r0
80041c8: 2b00 cmp r3, #0
80041ca: d001 beq.n 80041d0 <HAL_UART_Transmit+0x10e>
{
return HAL_TIMEOUT;
80041cc: 2303 movs r3, #3
80041ce: e006 b.n 80041de <HAL_UART_Transmit+0x11c>
}
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
80041d0: 68fb ldr r3, [r7, #12]
80041d2: 2220 movs r2, #32
80041d4: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
80041d8: 2300 movs r3, #0
80041da: e000 b.n 80041de <HAL_UART_Transmit+0x11c>
}
else
{
return HAL_BUSY;
80041dc: 2302 movs r3, #2
}
}
80041de: 4618 mov r0, r3
80041e0: 3720 adds r7, #32
80041e2: 46bd mov sp, r7
80041e4: bd80 pop {r7, pc}
...
080041e8 <HAL_UART_Transmit_DMA>:
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
80041e8: b580 push {r7, lr}
80041ea: b086 sub sp, #24
80041ec: af00 add r7, sp, #0
80041ee: 60f8 str r0, [r7, #12]
80041f0: 60b9 str r1, [r7, #8]
80041f2: 4613 mov r3, r2
80041f4: 80fb strh r3, [r7, #6]
uint32_t *tmp;
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
80041f6: 68fb ldr r3, [r7, #12]
80041f8: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
80041fc: b2db uxtb r3, r3
80041fe: 2b20 cmp r3, #32
8004200: d153 bne.n 80042aa <HAL_UART_Transmit_DMA+0xc2>
{
if ((pData == NULL) || (Size == 0U))
8004202: 68bb ldr r3, [r7, #8]
8004204: 2b00 cmp r3, #0
8004206: d002 beq.n 800420e <HAL_UART_Transmit_DMA+0x26>
8004208: 88fb ldrh r3, [r7, #6]
800420a: 2b00 cmp r3, #0
800420c: d101 bne.n 8004212 <HAL_UART_Transmit_DMA+0x2a>
{
return HAL_ERROR;
800420e: 2301 movs r3, #1
8004210: e04c b.n 80042ac <HAL_UART_Transmit_DMA+0xc4>
}
/* Process Locked */
__HAL_LOCK(huart);
8004212: 68fb ldr r3, [r7, #12]
8004214: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8004218: 2b01 cmp r3, #1
800421a: d101 bne.n 8004220 <HAL_UART_Transmit_DMA+0x38>
800421c: 2302 movs r3, #2
800421e: e045 b.n 80042ac <HAL_UART_Transmit_DMA+0xc4>
8004220: 68fb ldr r3, [r7, #12]
8004222: 2201 movs r2, #1
8004224: f883 203c strb.w r2, [r3, #60] ; 0x3c
huart->pTxBuffPtr = pData;
8004228: 68ba ldr r2, [r7, #8]
800422a: 68fb ldr r3, [r7, #12]
800422c: 621a str r2, [r3, #32]
huart->TxXferSize = Size;
800422e: 68fb ldr r3, [r7, #12]
8004230: 88fa ldrh r2, [r7, #6]
8004232: 849a strh r2, [r3, #36] ; 0x24
huart->TxXferCount = Size;
8004234: 68fb ldr r3, [r7, #12]
8004236: 88fa ldrh r2, [r7, #6]
8004238: 84da strh r2, [r3, #38] ; 0x26
huart->ErrorCode = HAL_UART_ERROR_NONE;
800423a: 68fb ldr r3, [r7, #12]
800423c: 2200 movs r2, #0
800423e: 641a str r2, [r3, #64] ; 0x40
huart->gState = HAL_UART_STATE_BUSY_TX;
8004240: 68fb ldr r3, [r7, #12]
8004242: 2221 movs r2, #33 ; 0x21
8004244: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Set the UART DMA transfer complete callback */
huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
8004248: 68fb ldr r3, [r7, #12]
800424a: 6b5b ldr r3, [r3, #52] ; 0x34
800424c: 4a19 ldr r2, [pc, #100] ; (80042b4 <HAL_UART_Transmit_DMA+0xcc>)
800424e: 629a str r2, [r3, #40] ; 0x28
/* Set the UART DMA Half transfer complete callback */
huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
8004250: 68fb ldr r3, [r7, #12]
8004252: 6b5b ldr r3, [r3, #52] ; 0x34
8004254: 4a18 ldr r2, [pc, #96] ; (80042b8 <HAL_UART_Transmit_DMA+0xd0>)
8004256: 62da str r2, [r3, #44] ; 0x2c
/* Set the DMA error callback */
huart->hdmatx->XferErrorCallback = UART_DMAError;
8004258: 68fb ldr r3, [r7, #12]
800425a: 6b5b ldr r3, [r3, #52] ; 0x34
800425c: 4a17 ldr r2, [pc, #92] ; (80042bc <HAL_UART_Transmit_DMA+0xd4>)
800425e: 631a str r2, [r3, #48] ; 0x30
/* Set the DMA abort callback */
huart->hdmatx->XferAbortCallback = NULL;
8004260: 68fb ldr r3, [r7, #12]
8004262: 6b5b ldr r3, [r3, #52] ; 0x34
8004264: 2200 movs r2, #0
8004266: 635a str r2, [r3, #52] ; 0x34
/* Enable the UART transmit DMA channel */
tmp = (uint32_t *)&pData;
8004268: f107 0308 add.w r3, r7, #8
800426c: 617b str r3, [r7, #20]
HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size);
800426e: 68fb ldr r3, [r7, #12]
8004270: 6b58 ldr r0, [r3, #52] ; 0x34
8004272: 697b ldr r3, [r7, #20]
8004274: 6819 ldr r1, [r3, #0]
8004276: 68fb ldr r3, [r7, #12]
8004278: 681b ldr r3, [r3, #0]
800427a: 3304 adds r3, #4
800427c: 461a mov r2, r3
800427e: 88fb ldrh r3, [r7, #6]
8004280: f7fd fc98 bl 8001bb4 <HAL_DMA_Start_IT>
/* Clear the TC flag in the SR register by writing 0 to it */
__HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
8004284: 68fb ldr r3, [r7, #12]
8004286: 681b ldr r3, [r3, #0]
8004288: f06f 0240 mvn.w r2, #64 ; 0x40
800428c: 601a str r2, [r3, #0]
/* Process Unlocked */
__HAL_UNLOCK(huart);
800428e: 68fb ldr r3, [r7, #12]
8004290: 2200 movs r2, #0
8004292: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the UART CR3 register */
SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
8004296: 68fb ldr r3, [r7, #12]
8004298: 681b ldr r3, [r3, #0]
800429a: 695a ldr r2, [r3, #20]
800429c: 68fb ldr r3, [r7, #12]
800429e: 681b ldr r3, [r3, #0]
80042a0: f042 0280 orr.w r2, r2, #128 ; 0x80
80042a4: 615a str r2, [r3, #20]
return HAL_OK;
80042a6: 2300 movs r3, #0
80042a8: e000 b.n 80042ac <HAL_UART_Transmit_DMA+0xc4>
}
else
{
return HAL_BUSY;
80042aa: 2302 movs r3, #2
}
}
80042ac: 4618 mov r0, r3
80042ae: 3718 adds r7, #24
80042b0: 46bd mov sp, r7
80042b2: bd80 pop {r7, pc}
80042b4: 08004747 .word 0x08004747
80042b8: 08004799 .word 0x08004799
80042bc: 080047b5 .word 0x080047b5
080042c0 <HAL_UART_AbortReceive_IT>:
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
{
80042c0: b580 push {r7, lr}
80042c2: b082 sub sp, #8
80042c4: af00 add r7, sp, #0
80042c6: 6078 str r0, [r7, #4]
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
80042c8: 687b ldr r3, [r7, #4]
80042ca: 681b ldr r3, [r3, #0]
80042cc: 68da ldr r2, [r3, #12]
80042ce: 687b ldr r3, [r7, #4]
80042d0: 681b ldr r3, [r3, #0]
80042d2: f422 7290 bic.w r2, r2, #288 ; 0x120
80042d6: 60da str r2, [r3, #12]
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
80042d8: 687b ldr r3, [r7, #4]
80042da: 681b ldr r3, [r3, #0]
80042dc: 695a ldr r2, [r3, #20]
80042de: 687b ldr r3, [r7, #4]
80042e0: 681b ldr r3, [r3, #0]
80042e2: f022 0201 bic.w r2, r2, #1
80042e6: 615a str r2, [r3, #20]
/* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
80042e8: 687b ldr r3, [r7, #4]
80042ea: 6b1b ldr r3, [r3, #48] ; 0x30
80042ec: 2b01 cmp r3, #1
80042ee: d107 bne.n 8004300 <HAL_UART_AbortReceive_IT+0x40>
{
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
80042f0: 687b ldr r3, [r7, #4]
80042f2: 681b ldr r3, [r3, #0]
80042f4: 68da ldr r2, [r3, #12]
80042f6: 687b ldr r3, [r7, #4]
80042f8: 681b ldr r3, [r3, #0]
80042fa: f022 0210 bic.w r2, r2, #16
80042fe: 60da str r2, [r3, #12]
}
/* Disable the UART DMA Rx request if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8004300: 687b ldr r3, [r7, #4]
8004302: 681b ldr r3, [r3, #0]
8004304: 695b ldr r3, [r3, #20]
8004306: f003 0340 and.w r3, r3, #64 ; 0x40
800430a: 2b00 cmp r3, #0
800430c: d02d beq.n 800436a <HAL_UART_AbortReceive_IT+0xaa>
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
800430e: 687b ldr r3, [r7, #4]
8004310: 681b ldr r3, [r3, #0]
8004312: 695a ldr r2, [r3, #20]
8004314: 687b ldr r3, [r7, #4]
8004316: 681b ldr r3, [r3, #0]
8004318: f022 0240 bic.w r2, r2, #64 ; 0x40
800431c: 615a str r2, [r3, #20]
/* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
if (huart->hdmarx != NULL)
800431e: 687b ldr r3, [r7, #4]
8004320: 6b9b ldr r3, [r3, #56] ; 0x38
8004322: 2b00 cmp r3, #0
8004324: d013 beq.n 800434e <HAL_UART_AbortReceive_IT+0x8e>
{
/* Set the UART DMA Abort callback :
will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
8004326: 687b ldr r3, [r7, #4]
8004328: 6b9b ldr r3, [r3, #56] ; 0x38
800432a: 4a19 ldr r2, [pc, #100] ; (8004390 <HAL_UART_AbortReceive_IT+0xd0>)
800432c: 635a str r2, [r3, #52] ; 0x34
/* Abort DMA RX */
if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
800432e: 687b ldr r3, [r7, #4]
8004330: 6b9b ldr r3, [r3, #56] ; 0x38
8004332: 4618 mov r0, r3
8004334: f7fd fcd8 bl 8001ce8 <HAL_DMA_Abort_IT>
8004338: 4603 mov r3, r0
800433a: 2b00 cmp r3, #0
800433c: d022 beq.n 8004384 <HAL_UART_AbortReceive_IT+0xc4>
{
/* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
huart->hdmarx->XferAbortCallback(huart->hdmarx);
800433e: 687b ldr r3, [r7, #4]
8004340: 6b9b ldr r3, [r3, #56] ; 0x38
8004342: 6b5b ldr r3, [r3, #52] ; 0x34
8004344: 687a ldr r2, [r7, #4]
8004346: 6b92 ldr r2, [r2, #56] ; 0x38
8004348: 4610 mov r0, r2
800434a: 4798 blx r3
800434c: e01a b.n 8004384 <HAL_UART_AbortReceive_IT+0xc4>
}
}
else
{
/* Reset Rx transfer counter */
huart->RxXferCount = 0x00U;
800434e: 687b ldr r3, [r7, #4]
8004350: 2200 movs r2, #0
8004352: 85da strh r2, [r3, #46] ; 0x2e
/* Restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8004354: 687b ldr r3, [r7, #4]
8004356: 2220 movs r2, #32
8004358: f883 203e strb.w r2, [r3, #62] ; 0x3e
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
800435c: 687b ldr r3, [r7, #4]
800435e: 2200 movs r2, #0
8004360: 631a str r2, [r3, #48] ; 0x30
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/* Call registered Abort Receive Complete Callback */
huart->AbortReceiveCpltCallback(huart);
#else
/* Call legacy weak Abort Receive Complete Callback */
HAL_UART_AbortReceiveCpltCallback(huart);
8004362: 6878 ldr r0, [r7, #4]
8004364: f000 f9db bl 800471e <HAL_UART_AbortReceiveCpltCallback>
8004368: e00c b.n 8004384 <HAL_UART_AbortReceive_IT+0xc4>
}
}
else
{
/* Reset Rx transfer counter */
huart->RxXferCount = 0x00U;
800436a: 687b ldr r3, [r7, #4]
800436c: 2200 movs r2, #0
800436e: 85da strh r2, [r3, #46] ; 0x2e
/* Restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8004370: 687b ldr r3, [r7, #4]
8004372: 2220 movs r2, #32
8004374: f883 203e strb.w r2, [r3, #62] ; 0x3e
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8004378: 687b ldr r3, [r7, #4]
800437a: 2200 movs r2, #0
800437c: 631a str r2, [r3, #48] ; 0x30
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/* Call registered Abort Receive Complete Callback */
huart->AbortReceiveCpltCallback(huart);
#else
/* Call legacy weak Abort Receive Complete Callback */
HAL_UART_AbortReceiveCpltCallback(huart);
800437e: 6878 ldr r0, [r7, #4]
8004380: f000 f9cd bl 800471e <HAL_UART_AbortReceiveCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
return HAL_OK;
8004384: 2300 movs r3, #0
}
8004386: 4618 mov r0, r3
8004388: 3708 adds r7, #8
800438a: 46bd mov sp, r7
800438c: bd80 pop {r7, pc}
800438e: bf00 nop
8004390: 08004987 .word 0x08004987
08004394 <HAL_UART_IRQHandler>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
{
8004394: b580 push {r7, lr}
8004396: b08a sub sp, #40 ; 0x28
8004398: af00 add r7, sp, #0
800439a: 6078 str r0, [r7, #4]
uint32_t isrflags = READ_REG(huart->Instance->SR);
800439c: 687b ldr r3, [r7, #4]
800439e: 681b ldr r3, [r3, #0]
80043a0: 681b ldr r3, [r3, #0]
80043a2: 627b str r3, [r7, #36] ; 0x24
uint32_t cr1its = READ_REG(huart->Instance->CR1);
80043a4: 687b ldr r3, [r7, #4]
80043a6: 681b ldr r3, [r3, #0]
80043a8: 68db ldr r3, [r3, #12]
80043aa: 623b str r3, [r7, #32]
uint32_t cr3its = READ_REG(huart->Instance->CR3);
80043ac: 687b ldr r3, [r7, #4]
80043ae: 681b ldr r3, [r3, #0]
80043b0: 695b ldr r3, [r3, #20]
80043b2: 61fb str r3, [r7, #28]
uint32_t errorflags = 0x00U;
80043b4: 2300 movs r3, #0
80043b6: 61bb str r3, [r7, #24]
uint32_t dmarequest = 0x00U;
80043b8: 2300 movs r3, #0
80043ba: 617b str r3, [r7, #20]
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
80043bc: 6a7b ldr r3, [r7, #36] ; 0x24
80043be: f003 030f and.w r3, r3, #15
80043c2: 61bb str r3, [r7, #24]
if (errorflags == RESET)
80043c4: 69bb ldr r3, [r7, #24]
80043c6: 2b00 cmp r3, #0
80043c8: d10d bne.n 80043e6 <HAL_UART_IRQHandler+0x52>
{
/* UART in mode Receiver -------------------------------------------------*/
if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
80043ca: 6a7b ldr r3, [r7, #36] ; 0x24
80043cc: f003 0320 and.w r3, r3, #32
80043d0: 2b00 cmp r3, #0
80043d2: d008 beq.n 80043e6 <HAL_UART_IRQHandler+0x52>
80043d4: 6a3b ldr r3, [r7, #32]
80043d6: f003 0320 and.w r3, r3, #32
80043da: 2b00 cmp r3, #0
80043dc: d003 beq.n 80043e6 <HAL_UART_IRQHandler+0x52>
{
UART_Receive_IT(huart);
80043de: 6878 ldr r0, [r7, #4]
80043e0: f000 fb50 bl 8004a84 <UART_Receive_IT>
return;
80043e4: e17b b.n 80046de <HAL_UART_IRQHandler+0x34a>
}
}
/* If some errors occur */
if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
80043e6: 69bb ldr r3, [r7, #24]
80043e8: 2b00 cmp r3, #0
80043ea: f000 80b1 beq.w 8004550 <HAL_UART_IRQHandler+0x1bc>
80043ee: 69fb ldr r3, [r7, #28]
80043f0: f003 0301 and.w r3, r3, #1
80043f4: 2b00 cmp r3, #0
80043f6: d105 bne.n 8004404 <HAL_UART_IRQHandler+0x70>
80043f8: 6a3b ldr r3, [r7, #32]
80043fa: f403 7390 and.w r3, r3, #288 ; 0x120
80043fe: 2b00 cmp r3, #0
8004400: f000 80a6 beq.w 8004550 <HAL_UART_IRQHandler+0x1bc>
{
/* UART parity error interrupt occurred ----------------------------------*/
if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
8004404: 6a7b ldr r3, [r7, #36] ; 0x24
8004406: f003 0301 and.w r3, r3, #1
800440a: 2b00 cmp r3, #0
800440c: d00a beq.n 8004424 <HAL_UART_IRQHandler+0x90>
800440e: 6a3b ldr r3, [r7, #32]
8004410: f403 7380 and.w r3, r3, #256 ; 0x100
8004414: 2b00 cmp r3, #0
8004416: d005 beq.n 8004424 <HAL_UART_IRQHandler+0x90>
{
huart->ErrorCode |= HAL_UART_ERROR_PE;
8004418: 687b ldr r3, [r7, #4]
800441a: 6c1b ldr r3, [r3, #64] ; 0x40
800441c: f043 0201 orr.w r2, r3, #1
8004420: 687b ldr r3, [r7, #4]
8004422: 641a str r2, [r3, #64] ; 0x40
}
/* UART noise error interrupt occurred -----------------------------------*/
if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
8004424: 6a7b ldr r3, [r7, #36] ; 0x24
8004426: f003 0304 and.w r3, r3, #4
800442a: 2b00 cmp r3, #0
800442c: d00a beq.n 8004444 <HAL_UART_IRQHandler+0xb0>
800442e: 69fb ldr r3, [r7, #28]
8004430: f003 0301 and.w r3, r3, #1
8004434: 2b00 cmp r3, #0
8004436: d005 beq.n 8004444 <HAL_UART_IRQHandler+0xb0>
{
huart->ErrorCode |= HAL_UART_ERROR_NE;
8004438: 687b ldr r3, [r7, #4]
800443a: 6c1b ldr r3, [r3, #64] ; 0x40
800443c: f043 0202 orr.w r2, r3, #2
8004440: 687b ldr r3, [r7, #4]
8004442: 641a str r2, [r3, #64] ; 0x40
}
/* UART frame error interrupt occurred -----------------------------------*/
if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
8004444: 6a7b ldr r3, [r7, #36] ; 0x24
8004446: f003 0302 and.w r3, r3, #2
800444a: 2b00 cmp r3, #0
800444c: d00a beq.n 8004464 <HAL_UART_IRQHandler+0xd0>
800444e: 69fb ldr r3, [r7, #28]
8004450: f003 0301 and.w r3, r3, #1
8004454: 2b00 cmp r3, #0
8004456: d005 beq.n 8004464 <HAL_UART_IRQHandler+0xd0>
{
huart->ErrorCode |= HAL_UART_ERROR_FE;
8004458: 687b ldr r3, [r7, #4]
800445a: 6c1b ldr r3, [r3, #64] ; 0x40
800445c: f043 0204 orr.w r2, r3, #4
8004460: 687b ldr r3, [r7, #4]
8004462: 641a str r2, [r3, #64] ; 0x40
}
/* UART Over-Run interrupt occurred --------------------------------------*/
if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
8004464: 6a7b ldr r3, [r7, #36] ; 0x24
8004466: f003 0308 and.w r3, r3, #8
800446a: 2b00 cmp r3, #0
800446c: d00f beq.n 800448e <HAL_UART_IRQHandler+0xfa>
800446e: 6a3b ldr r3, [r7, #32]
8004470: f003 0320 and.w r3, r3, #32
8004474: 2b00 cmp r3, #0
8004476: d104 bne.n 8004482 <HAL_UART_IRQHandler+0xee>
8004478: 69fb ldr r3, [r7, #28]
800447a: f003 0301 and.w r3, r3, #1
800447e: 2b00 cmp r3, #0
8004480: d005 beq.n 800448e <HAL_UART_IRQHandler+0xfa>
{
huart->ErrorCode |= HAL_UART_ERROR_ORE;
8004482: 687b ldr r3, [r7, #4]
8004484: 6c1b ldr r3, [r3, #64] ; 0x40
8004486: f043 0208 orr.w r2, r3, #8
800448a: 687b ldr r3, [r7, #4]
800448c: 641a str r2, [r3, #64] ; 0x40
}
/* Call UART Error Call back function if need be --------------------------*/
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
800448e: 687b ldr r3, [r7, #4]
8004490: 6c1b ldr r3, [r3, #64] ; 0x40
8004492: 2b00 cmp r3, #0
8004494: f000 811e beq.w 80046d4 <HAL_UART_IRQHandler+0x340>
{
/* UART in mode Receiver -----------------------------------------------*/
if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
8004498: 6a7b ldr r3, [r7, #36] ; 0x24
800449a: f003 0320 and.w r3, r3, #32
800449e: 2b00 cmp r3, #0
80044a0: d007 beq.n 80044b2 <HAL_UART_IRQHandler+0x11e>
80044a2: 6a3b ldr r3, [r7, #32]
80044a4: f003 0320 and.w r3, r3, #32
80044a8: 2b00 cmp r3, #0
80044aa: d002 beq.n 80044b2 <HAL_UART_IRQHandler+0x11e>
{
UART_Receive_IT(huart);
80044ac: 6878 ldr r0, [r7, #4]
80044ae: f000 fae9 bl 8004a84 <UART_Receive_IT>
}
/* If Overrun error occurs, or if any error occurs in DMA mode reception,
consider error as blocking */
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
80044b2: 687b ldr r3, [r7, #4]
80044b4: 681b ldr r3, [r3, #0]
80044b6: 695b ldr r3, [r3, #20]
80044b8: f003 0340 and.w r3, r3, #64 ; 0x40
80044bc: 2b00 cmp r3, #0
80044be: bf14 ite ne
80044c0: 2301 movne r3, #1
80044c2: 2300 moveq r3, #0
80044c4: b2db uxtb r3, r3
80044c6: 617b str r3, [r7, #20]
if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
80044c8: 687b ldr r3, [r7, #4]
80044ca: 6c1b ldr r3, [r3, #64] ; 0x40
80044cc: f003 0308 and.w r3, r3, #8
80044d0: 2b00 cmp r3, #0
80044d2: d102 bne.n 80044da <HAL_UART_IRQHandler+0x146>
80044d4: 697b ldr r3, [r7, #20]
80044d6: 2b00 cmp r3, #0
80044d8: d031 beq.n 800453e <HAL_UART_IRQHandler+0x1aa>
{
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
UART_EndRxTransfer(huart);
80044da: 6878 ldr r0, [r7, #4]
80044dc: f000 fa13 bl 8004906 <UART_EndRxTransfer>
/* Disable the UART DMA Rx request if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80044e0: 687b ldr r3, [r7, #4]
80044e2: 681b ldr r3, [r3, #0]
80044e4: 695b ldr r3, [r3, #20]
80044e6: f003 0340 and.w r3, r3, #64 ; 0x40
80044ea: 2b00 cmp r3, #0
80044ec: d023 beq.n 8004536 <HAL_UART_IRQHandler+0x1a2>
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
80044ee: 687b ldr r3, [r7, #4]
80044f0: 681b ldr r3, [r3, #0]
80044f2: 695a ldr r2, [r3, #20]
80044f4: 687b ldr r3, [r7, #4]
80044f6: 681b ldr r3, [r3, #0]
80044f8: f022 0240 bic.w r2, r2, #64 ; 0x40
80044fc: 615a str r2, [r3, #20]
/* Abort the UART DMA Rx channel */
if (huart->hdmarx != NULL)
80044fe: 687b ldr r3, [r7, #4]
8004500: 6b9b ldr r3, [r3, #56] ; 0x38
8004502: 2b00 cmp r3, #0
8004504: d013 beq.n 800452e <HAL_UART_IRQHandler+0x19a>
{
/* Set the UART DMA Abort callback :
will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
8004506: 687b ldr r3, [r7, #4]
8004508: 6b9b ldr r3, [r3, #56] ; 0x38
800450a: 4a76 ldr r2, [pc, #472] ; (80046e4 <HAL_UART_IRQHandler+0x350>)
800450c: 635a str r2, [r3, #52] ; 0x34
if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
800450e: 687b ldr r3, [r7, #4]
8004510: 6b9b ldr r3, [r3, #56] ; 0x38
8004512: 4618 mov r0, r3
8004514: f7fd fbe8 bl 8001ce8 <HAL_DMA_Abort_IT>
8004518: 4603 mov r3, r0
800451a: 2b00 cmp r3, #0
800451c: d016 beq.n 800454c <HAL_UART_IRQHandler+0x1b8>
{
/* Call Directly XferAbortCallback function in case of error */
huart->hdmarx->XferAbortCallback(huart->hdmarx);
800451e: 687b ldr r3, [r7, #4]
8004520: 6b9b ldr r3, [r3, #56] ; 0x38
8004522: 6b5b ldr r3, [r3, #52] ; 0x34
8004524: 687a ldr r2, [r7, #4]
8004526: 6b92 ldr r2, [r2, #56] ; 0x38
8004528: 4610 mov r0, r2
800452a: 4798 blx r3
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
800452c: e00e b.n 800454c <HAL_UART_IRQHandler+0x1b8>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
800452e: 6878 ldr r0, [r7, #4]
8004530: f000 f8ec bl 800470c <HAL_UART_ErrorCallback>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8004534: e00a b.n 800454c <HAL_UART_IRQHandler+0x1b8>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8004536: 6878 ldr r0, [r7, #4]
8004538: f000 f8e8 bl 800470c <HAL_UART_ErrorCallback>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
800453c: e006 b.n 800454c <HAL_UART_IRQHandler+0x1b8>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
800453e: 6878 ldr r0, [r7, #4]
8004540: f000 f8e4 bl 800470c <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8004544: 687b ldr r3, [r7, #4]
8004546: 2200 movs r2, #0
8004548: 641a str r2, [r3, #64] ; 0x40
}
}
return;
800454a: e0c3 b.n 80046d4 <HAL_UART_IRQHandler+0x340>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
800454c: bf00 nop
return;
800454e: e0c1 b.n 80046d4 <HAL_UART_IRQHandler+0x340>
} /* End if some error occurs */
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if ( (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8004550: 687b ldr r3, [r7, #4]
8004552: 6b1b ldr r3, [r3, #48] ; 0x30
8004554: 2b01 cmp r3, #1
8004556: f040 80a1 bne.w 800469c <HAL_UART_IRQHandler+0x308>
&&((isrflags & USART_SR_IDLE) != 0U)
800455a: 6a7b ldr r3, [r7, #36] ; 0x24
800455c: f003 0310 and.w r3, r3, #16
8004560: 2b00 cmp r3, #0
8004562: f000 809b beq.w 800469c <HAL_UART_IRQHandler+0x308>
&&((cr1its & USART_SR_IDLE) != 0U))
8004566: 6a3b ldr r3, [r7, #32]
8004568: f003 0310 and.w r3, r3, #16
800456c: 2b00 cmp r3, #0
800456e: f000 8095 beq.w 800469c <HAL_UART_IRQHandler+0x308>
{
__HAL_UART_CLEAR_IDLEFLAG(huart);
8004572: 2300 movs r3, #0
8004574: 60fb str r3, [r7, #12]
8004576: 687b ldr r3, [r7, #4]
8004578: 681b ldr r3, [r3, #0]
800457a: 681b ldr r3, [r3, #0]
800457c: 60fb str r3, [r7, #12]
800457e: 687b ldr r3, [r7, #4]
8004580: 681b ldr r3, [r3, #0]
8004582: 685b ldr r3, [r3, #4]
8004584: 60fb str r3, [r7, #12]
8004586: 68fb ldr r3, [r7, #12]
/* Check if DMA mode is enabled in UART */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8004588: 687b ldr r3, [r7, #4]
800458a: 681b ldr r3, [r3, #0]
800458c: 695b ldr r3, [r3, #20]
800458e: f003 0340 and.w r3, r3, #64 ; 0x40
8004592: 2b00 cmp r3, #0
8004594: d04e beq.n 8004634 <HAL_UART_IRQHandler+0x2a0>
{
/* DMA mode enabled */
/* Check received length : If all expected data are received, do nothing,
(DMA cplt callback will be called).
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
8004596: 687b ldr r3, [r7, #4]
8004598: 6b9b ldr r3, [r3, #56] ; 0x38
800459a: 681b ldr r3, [r3, #0]
800459c: 685b ldr r3, [r3, #4]
800459e: 823b strh r3, [r7, #16]
if ( (nb_remaining_rx_data > 0U)
80045a0: 8a3b ldrh r3, [r7, #16]
80045a2: 2b00 cmp r3, #0
80045a4: f000 8098 beq.w 80046d8 <HAL_UART_IRQHandler+0x344>
&&(nb_remaining_rx_data < huart->RxXferSize))
80045a8: 687b ldr r3, [r7, #4]
80045aa: 8d9b ldrh r3, [r3, #44] ; 0x2c
80045ac: 8a3a ldrh r2, [r7, #16]
80045ae: 429a cmp r2, r3
80045b0: f080 8092 bcs.w 80046d8 <HAL_UART_IRQHandler+0x344>
{
/* Reception is not complete */
huart->RxXferCount = nb_remaining_rx_data;
80045b4: 687b ldr r3, [r7, #4]
80045b6: 8a3a ldrh r2, [r7, #16]
80045b8: 85da strh r2, [r3, #46] ; 0x2e
/* In Normal mode, end DMA xfer and HAL UART Rx process*/
if (huart->hdmarx->Init.Mode != DMA_CIRCULAR)
80045ba: 687b ldr r3, [r7, #4]
80045bc: 6b9b ldr r3, [r3, #56] ; 0x38
80045be: 699b ldr r3, [r3, #24]
80045c0: 2b20 cmp r3, #32
80045c2: d02b beq.n 800461c <HAL_UART_IRQHandler+0x288>
{
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
80045c4: 687b ldr r3, [r7, #4]
80045c6: 681b ldr r3, [r3, #0]
80045c8: 68da ldr r2, [r3, #12]
80045ca: 687b ldr r3, [r7, #4]
80045cc: 681b ldr r3, [r3, #0]
80045ce: f422 7280 bic.w r2, r2, #256 ; 0x100
80045d2: 60da str r2, [r3, #12]
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
80045d4: 687b ldr r3, [r7, #4]
80045d6: 681b ldr r3, [r3, #0]
80045d8: 695a ldr r2, [r3, #20]
80045da: 687b ldr r3, [r7, #4]
80045dc: 681b ldr r3, [r3, #0]
80045de: f022 0201 bic.w r2, r2, #1
80045e2: 615a str r2, [r3, #20]
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
in the UART CR3 register */
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
80045e4: 687b ldr r3, [r7, #4]
80045e6: 681b ldr r3, [r3, #0]
80045e8: 695a ldr r2, [r3, #20]
80045ea: 687b ldr r3, [r7, #4]
80045ec: 681b ldr r3, [r3, #0]
80045ee: f022 0240 bic.w r2, r2, #64 ; 0x40
80045f2: 615a str r2, [r3, #20]
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
80045f4: 687b ldr r3, [r7, #4]
80045f6: 2220 movs r2, #32
80045f8: f883 203e strb.w r2, [r3, #62] ; 0x3e
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
80045fc: 687b ldr r3, [r7, #4]
80045fe: 2200 movs r2, #0
8004600: 631a str r2, [r3, #48] ; 0x30
CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8004602: 687b ldr r3, [r7, #4]
8004604: 681b ldr r3, [r3, #0]
8004606: 68da ldr r2, [r3, #12]
8004608: 687b ldr r3, [r7, #4]
800460a: 681b ldr r3, [r3, #0]
800460c: f022 0210 bic.w r2, r2, #16
8004610: 60da str r2, [r3, #12]
/* Last bytes received, so no need as the abort is immediate */
(void)HAL_DMA_Abort(huart->hdmarx);
8004612: 687b ldr r3, [r7, #4]
8004614: 6b9b ldr r3, [r3, #56] ; 0x38
8004616: 4618 mov r0, r3
8004618: f7fd fb2b bl 8001c72 <HAL_DMA_Abort>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
800461c: 687b ldr r3, [r7, #4]
800461e: 8d9a ldrh r2, [r3, #44] ; 0x2c
8004620: 687b ldr r3, [r7, #4]
8004622: 8ddb ldrh r3, [r3, #46] ; 0x2e
8004624: b29b uxth r3, r3
8004626: 1ad3 subs r3, r2, r3
8004628: b29b uxth r3, r3
800462a: 4619 mov r1, r3
800462c: 6878 ldr r0, [r7, #4]
800462e: f000 f87f bl 8004730 <HAL_UARTEx_RxEventCallback>
#endif
}
return;
8004632: e051 b.n 80046d8 <HAL_UART_IRQHandler+0x344>
else
{
/* DMA mode not enabled */
/* Check received length : If all expected data are received, do nothing.
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
8004634: 687b ldr r3, [r7, #4]
8004636: 8d9a ldrh r2, [r3, #44] ; 0x2c
8004638: 687b ldr r3, [r7, #4]
800463a: 8ddb ldrh r3, [r3, #46] ; 0x2e
800463c: b29b uxth r3, r3
800463e: 1ad3 subs r3, r2, r3
8004640: 827b strh r3, [r7, #18]
if ( (huart->RxXferCount > 0U)
8004642: 687b ldr r3, [r7, #4]
8004644: 8ddb ldrh r3, [r3, #46] ; 0x2e
8004646: b29b uxth r3, r3
8004648: 2b00 cmp r3, #0
800464a: d047 beq.n 80046dc <HAL_UART_IRQHandler+0x348>
&&(nb_rx_data > 0U) )
800464c: 8a7b ldrh r3, [r7, #18]
800464e: 2b00 cmp r3, #0
8004650: d044 beq.n 80046dc <HAL_UART_IRQHandler+0x348>
{
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
8004652: 687b ldr r3, [r7, #4]
8004654: 681b ldr r3, [r3, #0]
8004656: 68da ldr r2, [r3, #12]
8004658: 687b ldr r3, [r7, #4]
800465a: 681b ldr r3, [r3, #0]
800465c: f422 7290 bic.w r2, r2, #288 ; 0x120
8004660: 60da str r2, [r3, #12]
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8004662: 687b ldr r3, [r7, #4]
8004664: 681b ldr r3, [r3, #0]
8004666: 695a ldr r2, [r3, #20]
8004668: 687b ldr r3, [r7, #4]
800466a: 681b ldr r3, [r3, #0]
800466c: f022 0201 bic.w r2, r2, #1
8004670: 615a str r2, [r3, #20]
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8004672: 687b ldr r3, [r7, #4]
8004674: 2220 movs r2, #32
8004676: f883 203e strb.w r2, [r3, #62] ; 0x3e
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
800467a: 687b ldr r3, [r7, #4]
800467c: 2200 movs r2, #0
800467e: 631a str r2, [r3, #48] ; 0x30
CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8004680: 687b ldr r3, [r7, #4]
8004682: 681b ldr r3, [r3, #0]
8004684: 68da ldr r2, [r3, #12]
8004686: 687b ldr r3, [r7, #4]
8004688: 681b ldr r3, [r3, #0]
800468a: f022 0210 bic.w r2, r2, #16
800468e: 60da str r2, [r3, #12]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxEventCallback(huart, nb_rx_data);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
8004690: 8a7b ldrh r3, [r7, #18]
8004692: 4619 mov r1, r3
8004694: 6878 ldr r0, [r7, #4]
8004696: f000 f84b bl 8004730 <HAL_UARTEx_RxEventCallback>
#endif
}
return;
800469a: e01f b.n 80046dc <HAL_UART_IRQHandler+0x348>
}
}
/* UART in mode Transmitter ------------------------------------------------*/
if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
800469c: 6a7b ldr r3, [r7, #36] ; 0x24
800469e: f003 0380 and.w r3, r3, #128 ; 0x80
80046a2: 2b00 cmp r3, #0
80046a4: d008 beq.n 80046b8 <HAL_UART_IRQHandler+0x324>
80046a6: 6a3b ldr r3, [r7, #32]
80046a8: f003 0380 and.w r3, r3, #128 ; 0x80
80046ac: 2b00 cmp r3, #0
80046ae: d003 beq.n 80046b8 <HAL_UART_IRQHandler+0x324>
{
UART_Transmit_IT(huart);
80046b0: 6878 ldr r0, [r7, #4]
80046b2: f000 f980 bl 80049b6 <UART_Transmit_IT>
return;
80046b6: e012 b.n 80046de <HAL_UART_IRQHandler+0x34a>
}
/* UART in mode Transmitter end --------------------------------------------*/
if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
80046b8: 6a7b ldr r3, [r7, #36] ; 0x24
80046ba: f003 0340 and.w r3, r3, #64 ; 0x40
80046be: 2b00 cmp r3, #0
80046c0: d00d beq.n 80046de <HAL_UART_IRQHandler+0x34a>
80046c2: 6a3b ldr r3, [r7, #32]
80046c4: f003 0340 and.w r3, r3, #64 ; 0x40
80046c8: 2b00 cmp r3, #0
80046ca: d008 beq.n 80046de <HAL_UART_IRQHandler+0x34a>
{
UART_EndTransmit_IT(huart);
80046cc: 6878 ldr r0, [r7, #4]
80046ce: f000 f9c1 bl 8004a54 <UART_EndTransmit_IT>
return;
80046d2: e004 b.n 80046de <HAL_UART_IRQHandler+0x34a>
return;
80046d4: bf00 nop
80046d6: e002 b.n 80046de <HAL_UART_IRQHandler+0x34a>
return;
80046d8: bf00 nop
80046da: e000 b.n 80046de <HAL_UART_IRQHandler+0x34a>
return;
80046dc: bf00 nop
}
}
80046de: 3728 adds r7, #40 ; 0x28
80046e0: 46bd mov sp, r7
80046e2: bd80 pop {r7, pc}
80046e4: 0800495f .word 0x0800495f
080046e8 <HAL_UART_TxHalfCpltCallback>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
{
80046e8: b480 push {r7}
80046ea: b083 sub sp, #12
80046ec: af00 add r7, sp, #0
80046ee: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_UART_TxHalfCpltCallback could be implemented in the user file
*/
}
80046f0: bf00 nop
80046f2: 370c adds r7, #12
80046f4: 46bd mov sp, r7
80046f6: bc80 pop {r7}
80046f8: 4770 bx lr
080046fa <HAL_UART_RxCpltCallback>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
{
80046fa: b480 push {r7}
80046fc: b083 sub sp, #12
80046fe: af00 add r7, sp, #0
8004700: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_UART_RxCpltCallback could be implemented in the user file
*/
}
8004702: bf00 nop
8004704: 370c adds r7, #12
8004706: 46bd mov sp, r7
8004708: bc80 pop {r7}
800470a: 4770 bx lr
0800470c <HAL_UART_ErrorCallback>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
800470c: b480 push {r7}
800470e: b083 sub sp, #12
8004710: af00 add r7, sp, #0
8004712: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_UART_ErrorCallback could be implemented in the user file
*/
}
8004714: bf00 nop
8004716: 370c adds r7, #12
8004718: 46bd mov sp, r7
800471a: bc80 pop {r7}
800471c: 4770 bx lr
0800471e <HAL_UART_AbortReceiveCpltCallback>:
* @brief UART Abort Receive Complete callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)
{
800471e: b480 push {r7}
8004720: b083 sub sp, #12
8004722: af00 add r7, sp, #0
8004724: 6078 str r0, [r7, #4]
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
*/
}
8004726: bf00 nop
8004728: 370c adds r7, #12
800472a: 46bd mov sp, r7
800472c: bc80 pop {r7}
800472e: 4770 bx lr
08004730 <HAL_UARTEx_RxEventCallback>:
* @param Size Number of data available in application reception buffer (indicates a position in
* reception buffer until which, data are available)
* @retval None
*/
__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
{
8004730: b480 push {r7}
8004732: b083 sub sp, #12
8004734: af00 add r7, sp, #0
8004736: 6078 str r0, [r7, #4]
8004738: 460b mov r3, r1
800473a: 807b strh r3, [r7, #2]
UNUSED(Size);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_RxEventCallback can be implemented in the user file.
*/
}
800473c: bf00 nop
800473e: 370c adds r7, #12
8004740: 46bd mov sp, r7
8004742: bc80 pop {r7}
8004744: 4770 bx lr
08004746 <UART_DMATransmitCplt>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
8004746: b580 push {r7, lr}
8004748: b084 sub sp, #16
800474a: af00 add r7, sp, #0
800474c: 6078 str r0, [r7, #4]
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
800474e: 687b ldr r3, [r7, #4]
8004750: 6a5b ldr r3, [r3, #36] ; 0x24
8004752: 60fb str r3, [r7, #12]
/* DMA Normal mode*/
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
8004754: 687b ldr r3, [r7, #4]
8004756: 681b ldr r3, [r3, #0]
8004758: 681b ldr r3, [r3, #0]
800475a: f003 0320 and.w r3, r3, #32
800475e: 2b00 cmp r3, #0
8004760: d113 bne.n 800478a <UART_DMATransmitCplt+0x44>
{
huart->TxXferCount = 0x00U;
8004762: 68fb ldr r3, [r7, #12]
8004764: 2200 movs r2, #0
8004766: 84da strh r2, [r3, #38] ; 0x26
/* Disable the DMA transfer for transmit request by setting the DMAT bit
in the UART CR3 register */
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
8004768: 68fb ldr r3, [r7, #12]
800476a: 681b ldr r3, [r3, #0]
800476c: 695a ldr r2, [r3, #20]
800476e: 68fb ldr r3, [r7, #12]
8004770: 681b ldr r3, [r3, #0]
8004772: f022 0280 bic.w r2, r2, #128 ; 0x80
8004776: 615a str r2, [r3, #20]
/* Enable the UART Transmit Complete Interrupt */
SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
8004778: 68fb ldr r3, [r7, #12]
800477a: 681b ldr r3, [r3, #0]
800477c: 68da ldr r2, [r3, #12]
800477e: 68fb ldr r3, [r7, #12]
8004780: 681b ldr r3, [r3, #0]
8004782: f042 0240 orr.w r2, r2, #64 ; 0x40
8004786: 60da str r2, [r3, #12]
#else
/*Call legacy weak Tx complete callback*/
HAL_UART_TxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
}
8004788: e002 b.n 8004790 <UART_DMATransmitCplt+0x4a>
HAL_UART_TxCpltCallback(huart);
800478a: 68f8 ldr r0, [r7, #12]
800478c: f7fc f858 bl 8000840 <HAL_UART_TxCpltCallback>
}
8004790: bf00 nop
8004792: 3710 adds r7, #16
8004794: 46bd mov sp, r7
8004796: bd80 pop {r7, pc}
08004798 <UART_DMATxHalfCplt>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
{
8004798: b580 push {r7, lr}
800479a: b084 sub sp, #16
800479c: af00 add r7, sp, #0
800479e: 6078 str r0, [r7, #4]
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
80047a0: 687b ldr r3, [r7, #4]
80047a2: 6a5b ldr r3, [r3, #36] ; 0x24
80047a4: 60fb str r3, [r7, #12]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Tx complete callback*/
huart->TxHalfCpltCallback(huart);
#else
/*Call legacy weak Tx complete callback*/
HAL_UART_TxHalfCpltCallback(huart);
80047a6: 68f8 ldr r0, [r7, #12]
80047a8: f7ff ff9e bl 80046e8 <HAL_UART_TxHalfCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
80047ac: bf00 nop
80047ae: 3710 adds r7, #16
80047b0: 46bd mov sp, r7
80047b2: bd80 pop {r7, pc}
080047b4 <UART_DMAError>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void UART_DMAError(DMA_HandleTypeDef *hdma)
{
80047b4: b580 push {r7, lr}
80047b6: b084 sub sp, #16
80047b8: af00 add r7, sp, #0
80047ba: 6078 str r0, [r7, #4]
uint32_t dmarequest = 0x00U;
80047bc: 2300 movs r3, #0
80047be: 60fb str r3, [r7, #12]
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
80047c0: 687b ldr r3, [r7, #4]
80047c2: 6a5b ldr r3, [r3, #36] ; 0x24
80047c4: 60bb str r3, [r7, #8]
/* Stop UART DMA Tx request if ongoing */
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
80047c6: 68bb ldr r3, [r7, #8]
80047c8: 681b ldr r3, [r3, #0]
80047ca: 695b ldr r3, [r3, #20]
80047cc: f003 0380 and.w r3, r3, #128 ; 0x80
80047d0: 2b00 cmp r3, #0
80047d2: bf14 ite ne
80047d4: 2301 movne r3, #1
80047d6: 2300 moveq r3, #0
80047d8: b2db uxtb r3, r3
80047da: 60fb str r3, [r7, #12]
if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
80047dc: 68bb ldr r3, [r7, #8]
80047de: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
80047e2: b2db uxtb r3, r3
80047e4: 2b21 cmp r3, #33 ; 0x21
80047e6: d108 bne.n 80047fa <UART_DMAError+0x46>
80047e8: 68fb ldr r3, [r7, #12]
80047ea: 2b00 cmp r3, #0
80047ec: d005 beq.n 80047fa <UART_DMAError+0x46>
{
huart->TxXferCount = 0x00U;
80047ee: 68bb ldr r3, [r7, #8]
80047f0: 2200 movs r2, #0
80047f2: 84da strh r2, [r3, #38] ; 0x26
UART_EndTxTransfer(huart);
80047f4: 68b8 ldr r0, [r7, #8]
80047f6: f000 f871 bl 80048dc <UART_EndTxTransfer>
}
/* Stop UART DMA Rx request if ongoing */
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
80047fa: 68bb ldr r3, [r7, #8]
80047fc: 681b ldr r3, [r3, #0]
80047fe: 695b ldr r3, [r3, #20]
8004800: f003 0340 and.w r3, r3, #64 ; 0x40
8004804: 2b00 cmp r3, #0
8004806: bf14 ite ne
8004808: 2301 movne r3, #1
800480a: 2300 moveq r3, #0
800480c: b2db uxtb r3, r3
800480e: 60fb str r3, [r7, #12]
if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
8004810: 68bb ldr r3, [r7, #8]
8004812: f893 303e ldrb.w r3, [r3, #62] ; 0x3e
8004816: b2db uxtb r3, r3
8004818: 2b22 cmp r3, #34 ; 0x22
800481a: d108 bne.n 800482e <UART_DMAError+0x7a>
800481c: 68fb ldr r3, [r7, #12]
800481e: 2b00 cmp r3, #0
8004820: d005 beq.n 800482e <UART_DMAError+0x7a>
{
huart->RxXferCount = 0x00U;
8004822: 68bb ldr r3, [r7, #8]
8004824: 2200 movs r2, #0
8004826: 85da strh r2, [r3, #46] ; 0x2e
UART_EndRxTransfer(huart);
8004828: 68b8 ldr r0, [r7, #8]
800482a: f000 f86c bl 8004906 <UART_EndRxTransfer>
}
huart->ErrorCode |= HAL_UART_ERROR_DMA;
800482e: 68bb ldr r3, [r7, #8]
8004830: 6c1b ldr r3, [r3, #64] ; 0x40
8004832: f043 0210 orr.w r2, r3, #16
8004836: 68bb ldr r3, [r7, #8]
8004838: 641a str r2, [r3, #64] ; 0x40
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
800483a: 68b8 ldr r0, [r7, #8]
800483c: f7ff ff66 bl 800470c <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
8004840: bf00 nop
8004842: 3710 adds r7, #16
8004844: 46bd mov sp, r7
8004846: bd80 pop {r7, pc}
08004848 <UART_WaitOnFlagUntilTimeout>:
* @param Tickstart Tick start value
* @param Timeout Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
{
8004848: b580 push {r7, lr}
800484a: b084 sub sp, #16
800484c: af00 add r7, sp, #0
800484e: 60f8 str r0, [r7, #12]
8004850: 60b9 str r1, [r7, #8]
8004852: 603b str r3, [r7, #0]
8004854: 4613 mov r3, r2
8004856: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8004858: e02c b.n 80048b4 <UART_WaitOnFlagUntilTimeout+0x6c>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
800485a: 69bb ldr r3, [r7, #24]
800485c: f1b3 3fff cmp.w r3, #4294967295
8004860: d028 beq.n 80048b4 <UART_WaitOnFlagUntilTimeout+0x6c>
{
if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
8004862: 69bb ldr r3, [r7, #24]
8004864: 2b00 cmp r3, #0
8004866: d007 beq.n 8004878 <UART_WaitOnFlagUntilTimeout+0x30>
8004868: f7fd f80e bl 8001888 <HAL_GetTick>
800486c: 4602 mov r2, r0
800486e: 683b ldr r3, [r7, #0]
8004870: 1ad3 subs r3, r2, r3
8004872: 69ba ldr r2, [r7, #24]
8004874: 429a cmp r2, r3
8004876: d21d bcs.n 80048b4 <UART_WaitOnFlagUntilTimeout+0x6c>
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
8004878: 68fb ldr r3, [r7, #12]
800487a: 681b ldr r3, [r3, #0]
800487c: 68da ldr r2, [r3, #12]
800487e: 68fb ldr r3, [r7, #12]
8004880: 681b ldr r3, [r3, #0]
8004882: f422 72d0 bic.w r2, r2, #416 ; 0x1a0
8004886: 60da str r2, [r3, #12]
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8004888: 68fb ldr r3, [r7, #12]
800488a: 681b ldr r3, [r3, #0]
800488c: 695a ldr r2, [r3, #20]
800488e: 68fb ldr r3, [r7, #12]
8004890: 681b ldr r3, [r3, #0]
8004892: f022 0201 bic.w r2, r2, #1
8004896: 615a str r2, [r3, #20]
huart->gState = HAL_UART_STATE_READY;
8004898: 68fb ldr r3, [r7, #12]
800489a: 2220 movs r2, #32
800489c: f883 203d strb.w r2, [r3, #61] ; 0x3d
huart->RxState = HAL_UART_STATE_READY;
80048a0: 68fb ldr r3, [r7, #12]
80048a2: 2220 movs r2, #32
80048a4: f883 203e strb.w r2, [r3, #62] ; 0x3e
/* Process Unlocked */
__HAL_UNLOCK(huart);
80048a8: 68fb ldr r3, [r7, #12]
80048aa: 2200 movs r2, #0
80048ac: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_TIMEOUT;
80048b0: 2303 movs r3, #3
80048b2: e00f b.n 80048d4 <UART_WaitOnFlagUntilTimeout+0x8c>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
80048b4: 68fb ldr r3, [r7, #12]
80048b6: 681b ldr r3, [r3, #0]
80048b8: 681a ldr r2, [r3, #0]
80048ba: 68bb ldr r3, [r7, #8]
80048bc: 4013 ands r3, r2
80048be: 68ba ldr r2, [r7, #8]
80048c0: 429a cmp r2, r3
80048c2: bf0c ite eq
80048c4: 2301 moveq r3, #1
80048c6: 2300 movne r3, #0
80048c8: b2db uxtb r3, r3
80048ca: 461a mov r2, r3
80048cc: 79fb ldrb r3, [r7, #7]
80048ce: 429a cmp r2, r3
80048d0: d0c3 beq.n 800485a <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
return HAL_OK;
80048d2: 2300 movs r3, #0
}
80048d4: 4618 mov r0, r3
80048d6: 3710 adds r7, #16
80048d8: 46bd mov sp, r7
80048da: bd80 pop {r7, pc}
080048dc <UART_EndTxTransfer>:
* @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
{
80048dc: b480 push {r7}
80048de: b083 sub sp, #12
80048e0: af00 add r7, sp, #0
80048e2: 6078 str r0, [r7, #4]
/* Disable TXEIE and TCIE interrupts */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
80048e4: 687b ldr r3, [r7, #4]
80048e6: 681b ldr r3, [r3, #0]
80048e8: 68da ldr r2, [r3, #12]
80048ea: 687b ldr r3, [r7, #4]
80048ec: 681b ldr r3, [r3, #0]
80048ee: f022 02c0 bic.w r2, r2, #192 ; 0xc0
80048f2: 60da str r2, [r3, #12]
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
80048f4: 687b ldr r3, [r7, #4]
80048f6: 2220 movs r2, #32
80048f8: f883 203d strb.w r2, [r3, #61] ; 0x3d
}
80048fc: bf00 nop
80048fe: 370c adds r7, #12
8004900: 46bd mov sp, r7
8004902: bc80 pop {r7}
8004904: 4770 bx lr
08004906 <UART_EndRxTransfer>:
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
8004906: b480 push {r7}
8004908: b083 sub sp, #12
800490a: af00 add r7, sp, #0
800490c: 6078 str r0, [r7, #4]
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
800490e: 687b ldr r3, [r7, #4]
8004910: 681b ldr r3, [r3, #0]
8004912: 68da ldr r2, [r3, #12]
8004914: 687b ldr r3, [r7, #4]
8004916: 681b ldr r3, [r3, #0]
8004918: f422 7290 bic.w r2, r2, #288 ; 0x120
800491c: 60da str r2, [r3, #12]
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
800491e: 687b ldr r3, [r7, #4]
8004920: 681b ldr r3, [r3, #0]
8004922: 695a ldr r2, [r3, #20]
8004924: 687b ldr r3, [r7, #4]
8004926: 681b ldr r3, [r3, #0]
8004928: f022 0201 bic.w r2, r2, #1
800492c: 615a str r2, [r3, #20]
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
800492e: 687b ldr r3, [r7, #4]
8004930: 6b1b ldr r3, [r3, #48] ; 0x30
8004932: 2b01 cmp r3, #1
8004934: d107 bne.n 8004946 <UART_EndRxTransfer+0x40>
{
CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8004936: 687b ldr r3, [r7, #4]
8004938: 681b ldr r3, [r3, #0]
800493a: 68da ldr r2, [r3, #12]
800493c: 687b ldr r3, [r7, #4]
800493e: 681b ldr r3, [r3, #0]
8004940: f022 0210 bic.w r2, r2, #16
8004944: 60da str r2, [r3, #12]
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8004946: 687b ldr r3, [r7, #4]
8004948: 2220 movs r2, #32
800494a: f883 203e strb.w r2, [r3, #62] ; 0x3e
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
800494e: 687b ldr r3, [r7, #4]
8004950: 2200 movs r2, #0
8004952: 631a str r2, [r3, #48] ; 0x30
}
8004954: bf00 nop
8004956: 370c adds r7, #12
8004958: 46bd mov sp, r7
800495a: bc80 pop {r7}
800495c: 4770 bx lr
0800495e <UART_DMAAbortOnError>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
800495e: b580 push {r7, lr}
8004960: b084 sub sp, #16
8004962: af00 add r7, sp, #0
8004964: 6078 str r0, [r7, #4]
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
8004966: 687b ldr r3, [r7, #4]
8004968: 6a5b ldr r3, [r3, #36] ; 0x24
800496a: 60fb str r3, [r7, #12]
huart->RxXferCount = 0x00U;
800496c: 68fb ldr r3, [r7, #12]
800496e: 2200 movs r2, #0
8004970: 85da strh r2, [r3, #46] ; 0x2e
huart->TxXferCount = 0x00U;
8004972: 68fb ldr r3, [r7, #12]
8004974: 2200 movs r2, #0
8004976: 84da strh r2, [r3, #38] ; 0x26
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8004978: 68f8 ldr r0, [r7, #12]
800497a: f7ff fec7 bl 800470c <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
800497e: bf00 nop
8004980: 3710 adds r7, #16
8004982: 46bd mov sp, r7
8004984: bd80 pop {r7, pc}
08004986 <UART_DMARxOnlyAbortCallback>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
{
8004986: b580 push {r7, lr}
8004988: b084 sub sp, #16
800498a: af00 add r7, sp, #0
800498c: 6078 str r0, [r7, #4]
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
800498e: 687b ldr r3, [r7, #4]
8004990: 6a5b ldr r3, [r3, #36] ; 0x24
8004992: 60fb str r3, [r7, #12]
huart->RxXferCount = 0x00U;
8004994: 68fb ldr r3, [r7, #12]
8004996: 2200 movs r2, #0
8004998: 85da strh r2, [r3, #46] ; 0x2e
/* Restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
800499a: 68fb ldr r3, [r7, #12]
800499c: 2220 movs r2, #32
800499e: f883 203e strb.w r2, [r3, #62] ; 0x3e
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
80049a2: 68fb ldr r3, [r7, #12]
80049a4: 2200 movs r2, #0
80049a6: 631a str r2, [r3, #48] ; 0x30
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/* Call registered Abort Receive Complete Callback */
huart->AbortReceiveCpltCallback(huart);
#else
/* Call legacy weak Abort Receive Complete Callback */
HAL_UART_AbortReceiveCpltCallback(huart);
80049a8: 68f8 ldr r0, [r7, #12]
80049aa: f7ff feb8 bl 800471e <HAL_UART_AbortReceiveCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
80049ae: bf00 nop
80049b0: 3710 adds r7, #16
80049b2: 46bd mov sp, r7
80049b4: bd80 pop {r7, pc}
080049b6 <UART_Transmit_IT>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
{
80049b6: b480 push {r7}
80049b8: b085 sub sp, #20
80049ba: af00 add r7, sp, #0
80049bc: 6078 str r0, [r7, #4]
uint16_t *tmp;
/* Check that a Tx process is ongoing */
if (huart->gState == HAL_UART_STATE_BUSY_TX)
80049be: 687b ldr r3, [r7, #4]
80049c0: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
80049c4: b2db uxtb r3, r3
80049c6: 2b21 cmp r3, #33 ; 0x21
80049c8: d13e bne.n 8004a48 <UART_Transmit_IT+0x92>
{
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
80049ca: 687b ldr r3, [r7, #4]
80049cc: 689b ldr r3, [r3, #8]
80049ce: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
80049d2: d114 bne.n 80049fe <UART_Transmit_IT+0x48>
80049d4: 687b ldr r3, [r7, #4]
80049d6: 691b ldr r3, [r3, #16]
80049d8: 2b00 cmp r3, #0
80049da: d110 bne.n 80049fe <UART_Transmit_IT+0x48>
{
tmp = (uint16_t *) huart->pTxBuffPtr;
80049dc: 687b ldr r3, [r7, #4]
80049de: 6a1b ldr r3, [r3, #32]
80049e0: 60fb str r3, [r7, #12]
huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
80049e2: 68fb ldr r3, [r7, #12]
80049e4: 881b ldrh r3, [r3, #0]
80049e6: 461a mov r2, r3
80049e8: 687b ldr r3, [r7, #4]
80049ea: 681b ldr r3, [r3, #0]
80049ec: f3c2 0208 ubfx r2, r2, #0, #9
80049f0: 605a str r2, [r3, #4]
huart->pTxBuffPtr += 2U;
80049f2: 687b ldr r3, [r7, #4]
80049f4: 6a1b ldr r3, [r3, #32]
80049f6: 1c9a adds r2, r3, #2
80049f8: 687b ldr r3, [r7, #4]
80049fa: 621a str r2, [r3, #32]
80049fc: e008 b.n 8004a10 <UART_Transmit_IT+0x5a>
}
else
{
huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
80049fe: 687b ldr r3, [r7, #4]
8004a00: 6a1b ldr r3, [r3, #32]
8004a02: 1c59 adds r1, r3, #1
8004a04: 687a ldr r2, [r7, #4]
8004a06: 6211 str r1, [r2, #32]
8004a08: 781a ldrb r2, [r3, #0]
8004a0a: 687b ldr r3, [r7, #4]
8004a0c: 681b ldr r3, [r3, #0]
8004a0e: 605a str r2, [r3, #4]
}
if (--huart->TxXferCount == 0U)
8004a10: 687b ldr r3, [r7, #4]
8004a12: 8cdb ldrh r3, [r3, #38] ; 0x26
8004a14: b29b uxth r3, r3
8004a16: 3b01 subs r3, #1
8004a18: b29b uxth r3, r3
8004a1a: 687a ldr r2, [r7, #4]
8004a1c: 4619 mov r1, r3
8004a1e: 84d1 strh r1, [r2, #38] ; 0x26
8004a20: 2b00 cmp r3, #0
8004a22: d10f bne.n 8004a44 <UART_Transmit_IT+0x8e>
{
/* Disable the UART Transmit Complete Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
8004a24: 687b ldr r3, [r7, #4]
8004a26: 681b ldr r3, [r3, #0]
8004a28: 68da ldr r2, [r3, #12]
8004a2a: 687b ldr r3, [r7, #4]
8004a2c: 681b ldr r3, [r3, #0]
8004a2e: f022 0280 bic.w r2, r2, #128 ; 0x80
8004a32: 60da str r2, [r3, #12]
/* Enable the UART Transmit Complete Interrupt */
__HAL_UART_ENABLE_IT(huart, UART_IT_TC);
8004a34: 687b ldr r3, [r7, #4]
8004a36: 681b ldr r3, [r3, #0]
8004a38: 68da ldr r2, [r3, #12]
8004a3a: 687b ldr r3, [r7, #4]
8004a3c: 681b ldr r3, [r3, #0]
8004a3e: f042 0240 orr.w r2, r2, #64 ; 0x40
8004a42: 60da str r2, [r3, #12]
}
return HAL_OK;
8004a44: 2300 movs r3, #0
8004a46: e000 b.n 8004a4a <UART_Transmit_IT+0x94>
}
else
{
return HAL_BUSY;
8004a48: 2302 movs r3, #2
}
}
8004a4a: 4618 mov r0, r3
8004a4c: 3714 adds r7, #20
8004a4e: 46bd mov sp, r7
8004a50: bc80 pop {r7}
8004a52: 4770 bx lr
08004a54 <UART_EndTransmit_IT>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
{
8004a54: b580 push {r7, lr}
8004a56: b082 sub sp, #8
8004a58: af00 add r7, sp, #0
8004a5a: 6078 str r0, [r7, #4]
/* Disable the UART Transmit Complete Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_TC);
8004a5c: 687b ldr r3, [r7, #4]
8004a5e: 681b ldr r3, [r3, #0]
8004a60: 68da ldr r2, [r3, #12]
8004a62: 687b ldr r3, [r7, #4]
8004a64: 681b ldr r3, [r3, #0]
8004a66: f022 0240 bic.w r2, r2, #64 ; 0x40
8004a6a: 60da str r2, [r3, #12]
/* Tx process is ended, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
8004a6c: 687b ldr r3, [r7, #4]
8004a6e: 2220 movs r2, #32
8004a70: f883 203d strb.w r2, [r3, #61] ; 0x3d
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Tx complete callback*/
huart->TxCpltCallback(huart);
#else
/*Call legacy weak Tx complete callback*/
HAL_UART_TxCpltCallback(huart);
8004a74: 6878 ldr r0, [r7, #4]
8004a76: f7fb fee3 bl 8000840 <HAL_UART_TxCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
return HAL_OK;
8004a7a: 2300 movs r3, #0
}
8004a7c: 4618 mov r0, r3
8004a7e: 3708 adds r7, #8
8004a80: 46bd mov sp, r7
8004a82: bd80 pop {r7, pc}
08004a84 <UART_Receive_IT>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
{
8004a84: b580 push {r7, lr}
8004a86: b086 sub sp, #24
8004a88: af00 add r7, sp, #0
8004a8a: 6078 str r0, [r7, #4]
uint8_t *pdata8bits;
uint16_t *pdata16bits;
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
8004a8c: 687b ldr r3, [r7, #4]
8004a8e: f893 303e ldrb.w r3, [r3, #62] ; 0x3e
8004a92: b2db uxtb r3, r3
8004a94: 2b22 cmp r3, #34 ; 0x22
8004a96: f040 8099 bne.w 8004bcc <UART_Receive_IT+0x148>
{
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8004a9a: 687b ldr r3, [r7, #4]
8004a9c: 689b ldr r3, [r3, #8]
8004a9e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8004aa2: d117 bne.n 8004ad4 <UART_Receive_IT+0x50>
8004aa4: 687b ldr r3, [r7, #4]
8004aa6: 691b ldr r3, [r3, #16]
8004aa8: 2b00 cmp r3, #0
8004aaa: d113 bne.n 8004ad4 <UART_Receive_IT+0x50>
{
pdata8bits = NULL;
8004aac: 2300 movs r3, #0
8004aae: 617b str r3, [r7, #20]
pdata16bits = (uint16_t *) huart->pRxBuffPtr;
8004ab0: 687b ldr r3, [r7, #4]
8004ab2: 6a9b ldr r3, [r3, #40] ; 0x28
8004ab4: 613b str r3, [r7, #16]
*pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
8004ab6: 687b ldr r3, [r7, #4]
8004ab8: 681b ldr r3, [r3, #0]
8004aba: 685b ldr r3, [r3, #4]
8004abc: b29b uxth r3, r3
8004abe: f3c3 0308 ubfx r3, r3, #0, #9
8004ac2: b29a uxth r2, r3
8004ac4: 693b ldr r3, [r7, #16]
8004ac6: 801a strh r2, [r3, #0]
huart->pRxBuffPtr += 2U;
8004ac8: 687b ldr r3, [r7, #4]
8004aca: 6a9b ldr r3, [r3, #40] ; 0x28
8004acc: 1c9a adds r2, r3, #2
8004ace: 687b ldr r3, [r7, #4]
8004ad0: 629a str r2, [r3, #40] ; 0x28
8004ad2: e026 b.n 8004b22 <UART_Receive_IT+0x9e>
}
else
{
pdata8bits = (uint8_t *) huart->pRxBuffPtr;
8004ad4: 687b ldr r3, [r7, #4]
8004ad6: 6a9b ldr r3, [r3, #40] ; 0x28
8004ad8: 617b str r3, [r7, #20]
pdata16bits = NULL;
8004ada: 2300 movs r3, #0
8004adc: 613b str r3, [r7, #16]
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
8004ade: 687b ldr r3, [r7, #4]
8004ae0: 689b ldr r3, [r3, #8]
8004ae2: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8004ae6: d007 beq.n 8004af8 <UART_Receive_IT+0x74>
8004ae8: 687b ldr r3, [r7, #4]
8004aea: 689b ldr r3, [r3, #8]
8004aec: 2b00 cmp r3, #0
8004aee: d10a bne.n 8004b06 <UART_Receive_IT+0x82>
8004af0: 687b ldr r3, [r7, #4]
8004af2: 691b ldr r3, [r3, #16]
8004af4: 2b00 cmp r3, #0
8004af6: d106 bne.n 8004b06 <UART_Receive_IT+0x82>
{
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
8004af8: 687b ldr r3, [r7, #4]
8004afa: 681b ldr r3, [r3, #0]
8004afc: 685b ldr r3, [r3, #4]
8004afe: b2da uxtb r2, r3
8004b00: 697b ldr r3, [r7, #20]
8004b02: 701a strb r2, [r3, #0]
8004b04: e008 b.n 8004b18 <UART_Receive_IT+0x94>
}
else
{
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
8004b06: 687b ldr r3, [r7, #4]
8004b08: 681b ldr r3, [r3, #0]
8004b0a: 685b ldr r3, [r3, #4]
8004b0c: b2db uxtb r3, r3
8004b0e: f003 037f and.w r3, r3, #127 ; 0x7f
8004b12: b2da uxtb r2, r3
8004b14: 697b ldr r3, [r7, #20]
8004b16: 701a strb r2, [r3, #0]
}
huart->pRxBuffPtr += 1U;
8004b18: 687b ldr r3, [r7, #4]
8004b1a: 6a9b ldr r3, [r3, #40] ; 0x28
8004b1c: 1c5a adds r2, r3, #1
8004b1e: 687b ldr r3, [r7, #4]
8004b20: 629a str r2, [r3, #40] ; 0x28
}
if (--huart->RxXferCount == 0U)
8004b22: 687b ldr r3, [r7, #4]
8004b24: 8ddb ldrh r3, [r3, #46] ; 0x2e
8004b26: b29b uxth r3, r3
8004b28: 3b01 subs r3, #1
8004b2a: b29b uxth r3, r3
8004b2c: 687a ldr r2, [r7, #4]
8004b2e: 4619 mov r1, r3
8004b30: 85d1 strh r1, [r2, #46] ; 0x2e
8004b32: 2b00 cmp r3, #0
8004b34: d148 bne.n 8004bc8 <UART_Receive_IT+0x144>
{
/* Disable the UART Data Register not empty Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
8004b36: 687b ldr r3, [r7, #4]
8004b38: 681b ldr r3, [r3, #0]
8004b3a: 68da ldr r2, [r3, #12]
8004b3c: 687b ldr r3, [r7, #4]
8004b3e: 681b ldr r3, [r3, #0]
8004b40: f022 0220 bic.w r2, r2, #32
8004b44: 60da str r2, [r3, #12]
/* Disable the UART Parity Error Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_PE);
8004b46: 687b ldr r3, [r7, #4]
8004b48: 681b ldr r3, [r3, #0]
8004b4a: 68da ldr r2, [r3, #12]
8004b4c: 687b ldr r3, [r7, #4]
8004b4e: 681b ldr r3, [r3, #0]
8004b50: f422 7280 bic.w r2, r2, #256 ; 0x100
8004b54: 60da str r2, [r3, #12]
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
8004b56: 687b ldr r3, [r7, #4]
8004b58: 681b ldr r3, [r3, #0]
8004b5a: 695a ldr r2, [r3, #20]
8004b5c: 687b ldr r3, [r7, #4]
8004b5e: 681b ldr r3, [r3, #0]
8004b60: f022 0201 bic.w r2, r2, #1
8004b64: 615a str r2, [r3, #20]
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8004b66: 687b ldr r3, [r7, #4]
8004b68: 2220 movs r2, #32
8004b6a: f883 203e strb.w r2, [r3, #62] ; 0x3e
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8004b6e: 687b ldr r3, [r7, #4]
8004b70: 6b1b ldr r3, [r3, #48] ; 0x30
8004b72: 2b01 cmp r3, #1
8004b74: d123 bne.n 8004bbe <UART_Receive_IT+0x13a>
{
/* Set reception type to Standard */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8004b76: 687b ldr r3, [r7, #4]
8004b78: 2200 movs r2, #0
8004b7a: 631a str r2, [r3, #48] ; 0x30
/* Disable IDLE interrupt */
CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8004b7c: 687b ldr r3, [r7, #4]
8004b7e: 681b ldr r3, [r3, #0]
8004b80: 68da ldr r2, [r3, #12]
8004b82: 687b ldr r3, [r7, #4]
8004b84: 681b ldr r3, [r3, #0]
8004b86: f022 0210 bic.w r2, r2, #16
8004b8a: 60da str r2, [r3, #12]
/* Check if IDLE flag is set */
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
8004b8c: 687b ldr r3, [r7, #4]
8004b8e: 681b ldr r3, [r3, #0]
8004b90: 681b ldr r3, [r3, #0]
8004b92: f003 0310 and.w r3, r3, #16
8004b96: 2b10 cmp r3, #16
8004b98: d10a bne.n 8004bb0 <UART_Receive_IT+0x12c>
{
/* Clear IDLE flag in ISR */
__HAL_UART_CLEAR_IDLEFLAG(huart);
8004b9a: 2300 movs r3, #0
8004b9c: 60fb str r3, [r7, #12]
8004b9e: 687b ldr r3, [r7, #4]
8004ba0: 681b ldr r3, [r3, #0]
8004ba2: 681b ldr r3, [r3, #0]
8004ba4: 60fb str r3, [r7, #12]
8004ba6: 687b ldr r3, [r7, #4]
8004ba8: 681b ldr r3, [r3, #0]
8004baa: 685b ldr r3, [r3, #4]
8004bac: 60fb str r3, [r7, #12]
8004bae: 68fb ldr r3, [r7, #12]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
8004bb0: 687b ldr r3, [r7, #4]
8004bb2: 8d9b ldrh r3, [r3, #44] ; 0x2c
8004bb4: 4619 mov r1, r3
8004bb6: 6878 ldr r0, [r7, #4]
8004bb8: f7ff fdba bl 8004730 <HAL_UARTEx_RxEventCallback>
8004bbc: e002 b.n 8004bc4 <UART_Receive_IT+0x140>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxCpltCallback(huart);
#else
/*Call legacy weak Rx complete callback*/
HAL_UART_RxCpltCallback(huart);
8004bbe: 6878 ldr r0, [r7, #4]
8004bc0: f7ff fd9b bl 80046fa <HAL_UART_RxCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
return HAL_OK;
8004bc4: 2300 movs r3, #0
8004bc6: e002 b.n 8004bce <UART_Receive_IT+0x14a>
}
return HAL_OK;
8004bc8: 2300 movs r3, #0
8004bca: e000 b.n 8004bce <UART_Receive_IT+0x14a>
}
else
{
return HAL_BUSY;
8004bcc: 2302 movs r3, #2
}
}
8004bce: 4618 mov r0, r3
8004bd0: 3718 adds r7, #24
8004bd2: 46bd mov sp, r7
8004bd4: bd80 pop {r7, pc}
...
08004bd8 <UART_SetConfig>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
8004bd8: b580 push {r7, lr}
8004bda: b084 sub sp, #16
8004bdc: af00 add r7, sp, #0
8004bde: 6078 str r0, [r7, #4]
assert_param(IS_UART_MODE(huart->Init.Mode));
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits
according to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8004be0: 687b ldr r3, [r7, #4]
8004be2: 681b ldr r3, [r3, #0]
8004be4: 691b ldr r3, [r3, #16]
8004be6: f423 5140 bic.w r1, r3, #12288 ; 0x3000
8004bea: 687b ldr r3, [r7, #4]
8004bec: 68da ldr r2, [r3, #12]
8004bee: 687b ldr r3, [r7, #4]
8004bf0: 681b ldr r3, [r3, #0]
8004bf2: 430a orrs r2, r1
8004bf4: 611a str r2, [r3, #16]
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
MODIFY_REG(huart->Instance->CR1,
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
tmpreg);
#else
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
8004bf6: 687b ldr r3, [r7, #4]
8004bf8: 689a ldr r2, [r3, #8]
8004bfa: 687b ldr r3, [r7, #4]
8004bfc: 691b ldr r3, [r3, #16]
8004bfe: 431a orrs r2, r3
8004c00: 687b ldr r3, [r7, #4]
8004c02: 695b ldr r3, [r3, #20]
8004c04: 4313 orrs r3, r2
8004c06: 60bb str r3, [r7, #8]
MODIFY_REG(huart->Instance->CR1,
8004c08: 687b ldr r3, [r7, #4]
8004c0a: 681b ldr r3, [r3, #0]
8004c0c: 68db ldr r3, [r3, #12]
8004c0e: f423 53b0 bic.w r3, r3, #5632 ; 0x1600
8004c12: f023 030c bic.w r3, r3, #12
8004c16: 687a ldr r2, [r7, #4]
8004c18: 6812 ldr r2, [r2, #0]
8004c1a: 68b9 ldr r1, [r7, #8]
8004c1c: 430b orrs r3, r1
8004c1e: 60d3 str r3, [r2, #12]
tmpreg);
#endif /* USART_CR1_OVER8 */
/*-------------------------- USART CR3 Configuration -----------------------*/
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
8004c20: 687b ldr r3, [r7, #4]
8004c22: 681b ldr r3, [r3, #0]
8004c24: 695b ldr r3, [r3, #20]
8004c26: f423 7140 bic.w r1, r3, #768 ; 0x300
8004c2a: 687b ldr r3, [r7, #4]
8004c2c: 699a ldr r2, [r3, #24]
8004c2e: 687b ldr r3, [r7, #4]
8004c30: 681b ldr r3, [r3, #0]
8004c32: 430a orrs r2, r1
8004c34: 615a str r2, [r3, #20]
if(huart->Instance == USART1)
8004c36: 687b ldr r3, [r7, #4]
8004c38: 681b ldr r3, [r3, #0]
8004c3a: 4a2c ldr r2, [pc, #176] ; (8004cec <UART_SetConfig+0x114>)
8004c3c: 4293 cmp r3, r2
8004c3e: d103 bne.n 8004c48 <UART_SetConfig+0x70>
{
pclk = HAL_RCC_GetPCLK2Freq();
8004c40: f7fe f88c bl 8002d5c <HAL_RCC_GetPCLK2Freq>
8004c44: 60f8 str r0, [r7, #12]
8004c46: e002 b.n 8004c4e <UART_SetConfig+0x76>
}
else
{
pclk = HAL_RCC_GetPCLK1Freq();
8004c48: f7fe f874 bl 8002d34 <HAL_RCC_GetPCLK1Freq>
8004c4c: 60f8 str r0, [r7, #12]
else
{
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
}
#else
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
8004c4e: 68fa ldr r2, [r7, #12]
8004c50: 4613 mov r3, r2
8004c52: 009b lsls r3, r3, #2
8004c54: 4413 add r3, r2
8004c56: 009a lsls r2, r3, #2
8004c58: 441a add r2, r3
8004c5a: 687b ldr r3, [r7, #4]
8004c5c: 685b ldr r3, [r3, #4]
8004c5e: 009b lsls r3, r3, #2
8004c60: fbb2 f3f3 udiv r3, r2, r3
8004c64: 4a22 ldr r2, [pc, #136] ; (8004cf0 <UART_SetConfig+0x118>)
8004c66: fba2 2303 umull r2, r3, r2, r3
8004c6a: 095b lsrs r3, r3, #5
8004c6c: 0119 lsls r1, r3, #4
8004c6e: 68fa ldr r2, [r7, #12]
8004c70: 4613 mov r3, r2
8004c72: 009b lsls r3, r3, #2
8004c74: 4413 add r3, r2
8004c76: 009a lsls r2, r3, #2
8004c78: 441a add r2, r3
8004c7a: 687b ldr r3, [r7, #4]
8004c7c: 685b ldr r3, [r3, #4]
8004c7e: 009b lsls r3, r3, #2
8004c80: fbb2 f2f3 udiv r2, r2, r3
8004c84: 4b1a ldr r3, [pc, #104] ; (8004cf0 <UART_SetConfig+0x118>)
8004c86: fba3 0302 umull r0, r3, r3, r2
8004c8a: 095b lsrs r3, r3, #5
8004c8c: 2064 movs r0, #100 ; 0x64
8004c8e: fb00 f303 mul.w r3, r0, r3
8004c92: 1ad3 subs r3, r2, r3
8004c94: 011b lsls r3, r3, #4
8004c96: 3332 adds r3, #50 ; 0x32
8004c98: 4a15 ldr r2, [pc, #84] ; (8004cf0 <UART_SetConfig+0x118>)
8004c9a: fba2 2303 umull r2, r3, r2, r3
8004c9e: 095b lsrs r3, r3, #5
8004ca0: f003 03f0 and.w r3, r3, #240 ; 0xf0
8004ca4: 4419 add r1, r3
8004ca6: 68fa ldr r2, [r7, #12]
8004ca8: 4613 mov r3, r2
8004caa: 009b lsls r3, r3, #2
8004cac: 4413 add r3, r2
8004cae: 009a lsls r2, r3, #2
8004cb0: 441a add r2, r3
8004cb2: 687b ldr r3, [r7, #4]
8004cb4: 685b ldr r3, [r3, #4]
8004cb6: 009b lsls r3, r3, #2
8004cb8: fbb2 f2f3 udiv r2, r2, r3
8004cbc: 4b0c ldr r3, [pc, #48] ; (8004cf0 <UART_SetConfig+0x118>)
8004cbe: fba3 0302 umull r0, r3, r3, r2
8004cc2: 095b lsrs r3, r3, #5
8004cc4: 2064 movs r0, #100 ; 0x64
8004cc6: fb00 f303 mul.w r3, r0, r3
8004cca: 1ad3 subs r3, r2, r3
8004ccc: 011b lsls r3, r3, #4
8004cce: 3332 adds r3, #50 ; 0x32
8004cd0: 4a07 ldr r2, [pc, #28] ; (8004cf0 <UART_SetConfig+0x118>)
8004cd2: fba2 2303 umull r2, r3, r2, r3
8004cd6: 095b lsrs r3, r3, #5
8004cd8: f003 020f and.w r2, r3, #15
8004cdc: 687b ldr r3, [r7, #4]
8004cde: 681b ldr r3, [r3, #0]
8004ce0: 440a add r2, r1
8004ce2: 609a str r2, [r3, #8]
#endif /* USART_CR1_OVER8 */
}
8004ce4: bf00 nop
8004ce6: 3710 adds r7, #16
8004ce8: 46bd mov sp, r7
8004cea: bd80 pop {r7, pc}
8004cec: 40013800 .word 0x40013800
8004cf0: 51eb851f .word 0x51eb851f
08004cf4 <USB_CoreInit>:
* @param cfg pointer to a USB_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
{
8004cf4: b084 sub sp, #16
8004cf6: b480 push {r7}
8004cf8: b083 sub sp, #12
8004cfa: af00 add r7, sp, #0
8004cfc: 6078 str r0, [r7, #4]
8004cfe: f107 0014 add.w r0, r7, #20
8004d02: e880 000e stmia.w r0, {r1, r2, r3}
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
8004d06: 2300 movs r3, #0
}
8004d08: 4618 mov r0, r3
8004d0a: 370c adds r7, #12
8004d0c: 46bd mov sp, r7
8004d0e: bc80 pop {r7}
8004d10: b004 add sp, #16
8004d12: 4770 bx lr
08004d14 <USB_DisableGlobalInt>:
* Disable the controller's Global Int in the AHB Config reg
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx)
{
8004d14: b480 push {r7}
8004d16: b085 sub sp, #20
8004d18: af00 add r7, sp, #0
8004d1a: 6078 str r0, [r7, #4]
uint32_t winterruptmask;
/* Set winterruptmask variable */
winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
8004d1c: f44f 433f mov.w r3, #48896 ; 0xbf00
8004d20: 60fb str r3, [r7, #12]
USB_CNTR_SUSPM | USB_CNTR_ERRM |
USB_CNTR_SOFM | USB_CNTR_ESOFM |
USB_CNTR_RESETM;
/* Clear interrupt mask */
USBx->CNTR &= (uint16_t)(~winterruptmask);
8004d22: 687b ldr r3, [r7, #4]
8004d24: f8b3 3040 ldrh.w r3, [r3, #64] ; 0x40
8004d28: b29a uxth r2, r3
8004d2a: 68fb ldr r3, [r7, #12]
8004d2c: b29b uxth r3, r3
8004d2e: 43db mvns r3, r3
8004d30: b29b uxth r3, r3
8004d32: 4013 ands r3, r2
8004d34: b29a uxth r2, r3
8004d36: 687b ldr r3, [r7, #4]
8004d38: f8a3 2040 strh.w r2, [r3, #64] ; 0x40
return HAL_OK;
8004d3c: 2300 movs r3, #0
}
8004d3e: 4618 mov r0, r3
8004d40: 3714 adds r7, #20
8004d42: 46bd mov sp, r7
8004d44: bc80 pop {r7}
8004d46: 4770 bx lr
08004d48 <USB_SetCurrentMode>:
* This parameter can be one of the these values:
* @arg USB_DEVICE_MODE Peripheral mode
* @retval HAL status
*/
HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode)
{
8004d48: b480 push {r7}
8004d4a: b083 sub sp, #12
8004d4c: af00 add r7, sp, #0
8004d4e: 6078 str r0, [r7, #4]
8004d50: 460b mov r3, r1
8004d52: 70fb strb r3, [r7, #3]
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
8004d54: 2300 movs r3, #0
}
8004d56: 4618 mov r0, r3
8004d58: 370c adds r7, #12
8004d5a: 46bd mov sp, r7
8004d5c: bc80 pop {r7}
8004d5e: 4770 bx lr
08004d60 <USB_DevInit>:
* @param cfg pointer to a USB_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
{
8004d60: b084 sub sp, #16
8004d62: b480 push {r7}
8004d64: b083 sub sp, #12
8004d66: af00 add r7, sp, #0
8004d68: 6078 str r0, [r7, #4]
8004d6a: f107 0014 add.w r0, r7, #20
8004d6e: e880 000e stmia.w r0, {r1, r2, r3}
/* Prevent unused argument(s) compilation warning */
UNUSED(cfg);
/* Init Device */
/* CNTR_FRES = 1 */
USBx->CNTR = (uint16_t)USB_CNTR_FRES;
8004d72: 687b ldr r3, [r7, #4]
8004d74: 2201 movs r2, #1
8004d76: f8a3 2040 strh.w r2, [r3, #64] ; 0x40
/* CNTR_FRES = 0 */
USBx->CNTR = 0U;
8004d7a: 687b ldr r3, [r7, #4]
8004d7c: 2200 movs r2, #0
8004d7e: f8a3 2040 strh.w r2, [r3, #64] ; 0x40
/* Clear pending interrupts */
USBx->ISTR = 0U;
8004d82: 687b ldr r3, [r7, #4]
8004d84: 2200 movs r2, #0
8004d86: f8a3 2044 strh.w r2, [r3, #68] ; 0x44
/*Set Btable Address*/
USBx->BTABLE = BTABLE_ADDRESS;
8004d8a: 687b ldr r3, [r7, #4]
8004d8c: 2200 movs r2, #0
8004d8e: f8a3 2050 strh.w r2, [r3, #80] ; 0x50
return HAL_OK;
8004d92: 2300 movs r3, #0
}
8004d94: 4618 mov r0, r3
8004d96: 370c adds r7, #12
8004d98: 46bd mov sp, r7
8004d9a: bc80 pop {r7}
8004d9c: b004 add sp, #16
8004d9e: 4770 bx lr
08004da0 <USB_DevDisconnect>:
* @brief USB_DevDisconnect Disconnect the USB device by disabling the pull-up/pull-down
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx)
{
8004da0: b480 push {r7}
8004da2: b083 sub sp, #12
8004da4: af00 add r7, sp, #0
8004da6: 6078 str r0, [r7, #4]
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
8004da8: 2300 movs r3, #0
}
8004daa: 4618 mov r0, r3
8004dac: 370c adds r7, #12
8004dae: 46bd mov sp, r7
8004db0: bc80 pop {r7}
8004db2: 4770 bx lr
08004db4 <_ZdlPvj>:
8004db4: f000 b813 b.w 8004dde <_ZdlPv>
08004db8 <_Znwj>:
8004db8: 2801 cmp r0, #1
8004dba: bf38 it cc
8004dbc: 2001 movcc r0, #1
8004dbe: b510 push {r4, lr}
8004dc0: 4604 mov r4, r0
8004dc2: 4620 mov r0, r4
8004dc4: f000 f848 bl 8004e58 <malloc>
8004dc8: b930 cbnz r0, 8004dd8 <_Znwj+0x20>
8004dca: f000 f80b bl 8004de4 <_ZSt15get_new_handlerv>
8004dce: b908 cbnz r0, 8004dd4 <_Znwj+0x1c>
8004dd0: f000 f810 bl 8004df4 <abort>
8004dd4: 4780 blx r0
8004dd6: e7f4 b.n 8004dc2 <_Znwj+0xa>
8004dd8: bd10 pop {r4, pc}
08004dda <_Znaj>:
8004dda: f7ff bfed b.w 8004db8 <_Znwj>
08004dde <_ZdlPv>:
8004dde: f000 b843 b.w 8004e68 <free>
...
08004de4 <_ZSt15get_new_handlerv>:
8004de4: 4b02 ldr r3, [pc, #8] ; (8004df0 <_ZSt15get_new_handlerv+0xc>)
8004de6: 6818 ldr r0, [r3, #0]
8004de8: f3bf 8f5b dmb ish
8004dec: 4770 bx lr
8004dee: bf00 nop
8004df0: 20000890 .word 0x20000890
08004df4 <abort>:
8004df4: 2006 movs r0, #6
8004df6: b508 push {r3, lr}
8004df8: f000 f968 bl 80050cc <raise>
8004dfc: 2001 movs r0, #1
8004dfe: f7fc fc7e bl 80016fe <_exit>
...
08004e04 <__errno>:
8004e04: 4b01 ldr r3, [pc, #4] ; (8004e0c <__errno+0x8>)
8004e06: 6818 ldr r0, [r3, #0]
8004e08: 4770 bx lr
8004e0a: bf00 nop
8004e0c: 2000000c .word 0x2000000c
08004e10 <__libc_init_array>:
8004e10: b570 push {r4, r5, r6, lr}
8004e12: 2600 movs r6, #0
8004e14: 4d0c ldr r5, [pc, #48] ; (8004e48 <__libc_init_array+0x38>)
8004e16: 4c0d ldr r4, [pc, #52] ; (8004e4c <__libc_init_array+0x3c>)
8004e18: 1b64 subs r4, r4, r5
8004e1a: 10a4 asrs r4, r4, #2
8004e1c: 42a6 cmp r6, r4
8004e1e: d109 bne.n 8004e34 <__libc_init_array+0x24>
8004e20: f000 fcf0 bl 8005804 <_init>
8004e24: 2600 movs r6, #0
8004e26: 4d0a ldr r5, [pc, #40] ; (8004e50 <__libc_init_array+0x40>)
8004e28: 4c0a ldr r4, [pc, #40] ; (8004e54 <__libc_init_array+0x44>)
8004e2a: 1b64 subs r4, r4, r5
8004e2c: 10a4 asrs r4, r4, #2
8004e2e: 42a6 cmp r6, r4
8004e30: d105 bne.n 8004e3e <__libc_init_array+0x2e>
8004e32: bd70 pop {r4, r5, r6, pc}
8004e34: f855 3b04 ldr.w r3, [r5], #4
8004e38: 4798 blx r3
8004e3a: 3601 adds r6, #1
8004e3c: e7ee b.n 8004e1c <__libc_init_array+0xc>
8004e3e: f855 3b04 ldr.w r3, [r5], #4
8004e42: 4798 blx r3
8004e44: 3601 adds r6, #1
8004e46: e7f2 b.n 8004e2e <__libc_init_array+0x1e>
8004e48: 08005a7c .word 0x08005a7c
8004e4c: 08005a7c .word 0x08005a7c
8004e50: 08005a7c .word 0x08005a7c
8004e54: 08005a84 .word 0x08005a84
08004e58 <malloc>:
8004e58: 4b02 ldr r3, [pc, #8] ; (8004e64 <malloc+0xc>)
8004e5a: 4601 mov r1, r0
8004e5c: 6818 ldr r0, [r3, #0]
8004e5e: f000 b889 b.w 8004f74 <_malloc_r>
8004e62: bf00 nop
8004e64: 2000000c .word 0x2000000c
08004e68 <free>:
8004e68: 4b02 ldr r3, [pc, #8] ; (8004e74 <free+0xc>)
8004e6a: 4601 mov r1, r0
8004e6c: 6818 ldr r0, [r3, #0]
8004e6e: f000 b819 b.w 8004ea4 <_free_r>
8004e72: bf00 nop
8004e74: 2000000c .word 0x2000000c
08004e78 <memcpy>:
8004e78: 440a add r2, r1
8004e7a: 4291 cmp r1, r2
8004e7c: f100 33ff add.w r3, r0, #4294967295
8004e80: d100 bne.n 8004e84 <memcpy+0xc>
8004e82: 4770 bx lr
8004e84: b510 push {r4, lr}
8004e86: f811 4b01 ldrb.w r4, [r1], #1
8004e8a: 4291 cmp r1, r2
8004e8c: f803 4f01 strb.w r4, [r3, #1]!
8004e90: d1f9 bne.n 8004e86 <memcpy+0xe>
8004e92: bd10 pop {r4, pc}
08004e94 <memset>:
8004e94: 4603 mov r3, r0
8004e96: 4402 add r2, r0
8004e98: 4293 cmp r3, r2
8004e9a: d100 bne.n 8004e9e <memset+0xa>
8004e9c: 4770 bx lr
8004e9e: f803 1b01 strb.w r1, [r3], #1
8004ea2: e7f9 b.n 8004e98 <memset+0x4>
08004ea4 <_free_r>:
8004ea4: b538 push {r3, r4, r5, lr}
8004ea6: 4605 mov r5, r0
8004ea8: 2900 cmp r1, #0
8004eaa: d040 beq.n 8004f2e <_free_r+0x8a>
8004eac: f851 3c04 ldr.w r3, [r1, #-4]
8004eb0: 1f0c subs r4, r1, #4
8004eb2: 2b00 cmp r3, #0
8004eb4: bfb8 it lt
8004eb6: 18e4 addlt r4, r4, r3
8004eb8: f000 f944 bl 8005144 <__malloc_lock>
8004ebc: 4a1c ldr r2, [pc, #112] ; (8004f30 <_free_r+0x8c>)
8004ebe: 6813 ldr r3, [r2, #0]
8004ec0: b933 cbnz r3, 8004ed0 <_free_r+0x2c>
8004ec2: 6063 str r3, [r4, #4]
8004ec4: 6014 str r4, [r2, #0]
8004ec6: 4628 mov r0, r5
8004ec8: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
8004ecc: f000 b940 b.w 8005150 <__malloc_unlock>
8004ed0: 42a3 cmp r3, r4
8004ed2: d908 bls.n 8004ee6 <_free_r+0x42>
8004ed4: 6820 ldr r0, [r4, #0]
8004ed6: 1821 adds r1, r4, r0
8004ed8: 428b cmp r3, r1
8004eda: bf01 itttt eq
8004edc: 6819 ldreq r1, [r3, #0]
8004ede: 685b ldreq r3, [r3, #4]
8004ee0: 1809 addeq r1, r1, r0
8004ee2: 6021 streq r1, [r4, #0]
8004ee4: e7ed b.n 8004ec2 <_free_r+0x1e>
8004ee6: 461a mov r2, r3
8004ee8: 685b ldr r3, [r3, #4]
8004eea: b10b cbz r3, 8004ef0 <_free_r+0x4c>
8004eec: 42a3 cmp r3, r4
8004eee: d9fa bls.n 8004ee6 <_free_r+0x42>
8004ef0: 6811 ldr r1, [r2, #0]
8004ef2: 1850 adds r0, r2, r1
8004ef4: 42a0 cmp r0, r4
8004ef6: d10b bne.n 8004f10 <_free_r+0x6c>
8004ef8: 6820 ldr r0, [r4, #0]
8004efa: 4401 add r1, r0
8004efc: 1850 adds r0, r2, r1
8004efe: 4283 cmp r3, r0
8004f00: 6011 str r1, [r2, #0]
8004f02: d1e0 bne.n 8004ec6 <_free_r+0x22>
8004f04: 6818 ldr r0, [r3, #0]
8004f06: 685b ldr r3, [r3, #4]
8004f08: 4401 add r1, r0
8004f0a: 6011 str r1, [r2, #0]
8004f0c: 6053 str r3, [r2, #4]
8004f0e: e7da b.n 8004ec6 <_free_r+0x22>
8004f10: d902 bls.n 8004f18 <_free_r+0x74>
8004f12: 230c movs r3, #12
8004f14: 602b str r3, [r5, #0]
8004f16: e7d6 b.n 8004ec6 <_free_r+0x22>
8004f18: 6820 ldr r0, [r4, #0]
8004f1a: 1821 adds r1, r4, r0
8004f1c: 428b cmp r3, r1
8004f1e: bf01 itttt eq
8004f20: 6819 ldreq r1, [r3, #0]
8004f22: 685b ldreq r3, [r3, #4]
8004f24: 1809 addeq r1, r1, r0
8004f26: 6021 streq r1, [r4, #0]
8004f28: 6063 str r3, [r4, #4]
8004f2a: 6054 str r4, [r2, #4]
8004f2c: e7cb b.n 8004ec6 <_free_r+0x22>
8004f2e: bd38 pop {r3, r4, r5, pc}
8004f30: 20000894 .word 0x20000894
08004f34 <sbrk_aligned>:
8004f34: b570 push {r4, r5, r6, lr}
8004f36: 4e0e ldr r6, [pc, #56] ; (8004f70 <sbrk_aligned+0x3c>)
8004f38: 460c mov r4, r1
8004f3a: 6831 ldr r1, [r6, #0]
8004f3c: 4605 mov r5, r0
8004f3e: b911 cbnz r1, 8004f46 <sbrk_aligned+0x12>
8004f40: f000 f88c bl 800505c <_sbrk_r>
8004f44: 6030 str r0, [r6, #0]
8004f46: 4621 mov r1, r4
8004f48: 4628 mov r0, r5
8004f4a: f000 f887 bl 800505c <_sbrk_r>
8004f4e: 1c43 adds r3, r0, #1
8004f50: d00a beq.n 8004f68 <sbrk_aligned+0x34>
8004f52: 1cc4 adds r4, r0, #3
8004f54: f024 0403 bic.w r4, r4, #3
8004f58: 42a0 cmp r0, r4
8004f5a: d007 beq.n 8004f6c <sbrk_aligned+0x38>
8004f5c: 1a21 subs r1, r4, r0
8004f5e: 4628 mov r0, r5
8004f60: f000 f87c bl 800505c <_sbrk_r>
8004f64: 3001 adds r0, #1
8004f66: d101 bne.n 8004f6c <sbrk_aligned+0x38>
8004f68: f04f 34ff mov.w r4, #4294967295
8004f6c: 4620 mov r0, r4
8004f6e: bd70 pop {r4, r5, r6, pc}
8004f70: 20000898 .word 0x20000898
08004f74 <_malloc_r>:
8004f74: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
8004f78: 1ccd adds r5, r1, #3
8004f7a: f025 0503 bic.w r5, r5, #3
8004f7e: 3508 adds r5, #8
8004f80: 2d0c cmp r5, #12
8004f82: bf38 it cc
8004f84: 250c movcc r5, #12
8004f86: 2d00 cmp r5, #0
8004f88: 4607 mov r7, r0
8004f8a: db01 blt.n 8004f90 <_malloc_r+0x1c>
8004f8c: 42a9 cmp r1, r5
8004f8e: d905 bls.n 8004f9c <_malloc_r+0x28>
8004f90: 230c movs r3, #12
8004f92: 2600 movs r6, #0
8004f94: 603b str r3, [r7, #0]
8004f96: 4630 mov r0, r6
8004f98: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
8004f9c: 4e2e ldr r6, [pc, #184] ; (8005058 <_malloc_r+0xe4>)
8004f9e: f000 f8d1 bl 8005144 <__malloc_lock>
8004fa2: 6833 ldr r3, [r6, #0]
8004fa4: 461c mov r4, r3
8004fa6: bb34 cbnz r4, 8004ff6 <_malloc_r+0x82>
8004fa8: 4629 mov r1, r5
8004faa: 4638 mov r0, r7
8004fac: f7ff ffc2 bl 8004f34 <sbrk_aligned>
8004fb0: 1c43 adds r3, r0, #1
8004fb2: 4604 mov r4, r0
8004fb4: d14d bne.n 8005052 <_malloc_r+0xde>
8004fb6: 6834 ldr r4, [r6, #0]
8004fb8: 4626 mov r6, r4
8004fba: 2e00 cmp r6, #0
8004fbc: d140 bne.n 8005040 <_malloc_r+0xcc>
8004fbe: 6823 ldr r3, [r4, #0]
8004fc0: 4631 mov r1, r6
8004fc2: 4638 mov r0, r7
8004fc4: eb04 0803 add.w r8, r4, r3
8004fc8: f000 f848 bl 800505c <_sbrk_r>
8004fcc: 4580 cmp r8, r0
8004fce: d13a bne.n 8005046 <_malloc_r+0xd2>
8004fd0: 6821 ldr r1, [r4, #0]
8004fd2: 3503 adds r5, #3
8004fd4: 1a6d subs r5, r5, r1
8004fd6: f025 0503 bic.w r5, r5, #3
8004fda: 3508 adds r5, #8
8004fdc: 2d0c cmp r5, #12
8004fde: bf38 it cc
8004fe0: 250c movcc r5, #12
8004fe2: 4638 mov r0, r7
8004fe4: 4629 mov r1, r5
8004fe6: f7ff ffa5 bl 8004f34 <sbrk_aligned>
8004fea: 3001 adds r0, #1
8004fec: d02b beq.n 8005046 <_malloc_r+0xd2>
8004fee: 6823 ldr r3, [r4, #0]
8004ff0: 442b add r3, r5
8004ff2: 6023 str r3, [r4, #0]
8004ff4: e00e b.n 8005014 <_malloc_r+0xa0>
8004ff6: 6822 ldr r2, [r4, #0]
8004ff8: 1b52 subs r2, r2, r5
8004ffa: d41e bmi.n 800503a <_malloc_r+0xc6>
8004ffc: 2a0b cmp r2, #11
8004ffe: d916 bls.n 800502e <_malloc_r+0xba>
8005000: 1961 adds r1, r4, r5
8005002: 42a3 cmp r3, r4
8005004: 6025 str r5, [r4, #0]
8005006: bf18 it ne
8005008: 6059 strne r1, [r3, #4]
800500a: 6863 ldr r3, [r4, #4]
800500c: bf08 it eq
800500e: 6031 streq r1, [r6, #0]
8005010: 5162 str r2, [r4, r5]
8005012: 604b str r3, [r1, #4]
8005014: 4638 mov r0, r7
8005016: f104 060b add.w r6, r4, #11
800501a: f000 f899 bl 8005150 <__malloc_unlock>
800501e: f026 0607 bic.w r6, r6, #7
8005022: 1d23 adds r3, r4, #4
8005024: 1af2 subs r2, r6, r3
8005026: d0b6 beq.n 8004f96 <_malloc_r+0x22>
8005028: 1b9b subs r3, r3, r6
800502a: 50a3 str r3, [r4, r2]
800502c: e7b3 b.n 8004f96 <_malloc_r+0x22>
800502e: 6862 ldr r2, [r4, #4]
8005030: 42a3 cmp r3, r4
8005032: bf0c ite eq
8005034: 6032 streq r2, [r6, #0]
8005036: 605a strne r2, [r3, #4]
8005038: e7ec b.n 8005014 <_malloc_r+0xa0>
800503a: 4623 mov r3, r4
800503c: 6864 ldr r4, [r4, #4]
800503e: e7b2 b.n 8004fa6 <_malloc_r+0x32>
8005040: 4634 mov r4, r6
8005042: 6876 ldr r6, [r6, #4]
8005044: e7b9 b.n 8004fba <_malloc_r+0x46>
8005046: 230c movs r3, #12
8005048: 4638 mov r0, r7
800504a: 603b str r3, [r7, #0]
800504c: f000 f880 bl 8005150 <__malloc_unlock>
8005050: e7a1 b.n 8004f96 <_malloc_r+0x22>
8005052: 6025 str r5, [r4, #0]
8005054: e7de b.n 8005014 <_malloc_r+0xa0>
8005056: bf00 nop
8005058: 20000894 .word 0x20000894
0800505c <_sbrk_r>:
800505c: b538 push {r3, r4, r5, lr}
800505e: 2300 movs r3, #0
8005060: 4d05 ldr r5, [pc, #20] ; (8005078 <_sbrk_r+0x1c>)
8005062: 4604 mov r4, r0
8005064: 4608 mov r0, r1
8005066: 602b str r3, [r5, #0]
8005068: f7fc fb54 bl 8001714 <_sbrk>
800506c: 1c43 adds r3, r0, #1
800506e: d102 bne.n 8005076 <_sbrk_r+0x1a>
8005070: 682b ldr r3, [r5, #0]
8005072: b103 cbz r3, 8005076 <_sbrk_r+0x1a>
8005074: 6023 str r3, [r4, #0]
8005076: bd38 pop {r3, r4, r5, pc}
8005078: 2000089c .word 0x2000089c
0800507c <_raise_r>:
800507c: 291f cmp r1, #31
800507e: b538 push {r3, r4, r5, lr}
8005080: 4604 mov r4, r0
8005082: 460d mov r5, r1
8005084: d904 bls.n 8005090 <_raise_r+0x14>
8005086: 2316 movs r3, #22
8005088: 6003 str r3, [r0, #0]
800508a: f04f 30ff mov.w r0, #4294967295
800508e: bd38 pop {r3, r4, r5, pc}
8005090: 6c42 ldr r2, [r0, #68] ; 0x44
8005092: b112 cbz r2, 800509a <_raise_r+0x1e>
8005094: f852 3021 ldr.w r3, [r2, r1, lsl #2]
8005098: b94b cbnz r3, 80050ae <_raise_r+0x32>
800509a: 4620 mov r0, r4
800509c: f000 f830 bl 8005100 <_getpid_r>
80050a0: 462a mov r2, r5
80050a2: 4601 mov r1, r0
80050a4: 4620 mov r0, r4
80050a6: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
80050aa: f000 b817 b.w 80050dc <_kill_r>
80050ae: 2b01 cmp r3, #1
80050b0: d00a beq.n 80050c8 <_raise_r+0x4c>
80050b2: 1c59 adds r1, r3, #1
80050b4: d103 bne.n 80050be <_raise_r+0x42>
80050b6: 2316 movs r3, #22
80050b8: 6003 str r3, [r0, #0]
80050ba: 2001 movs r0, #1
80050bc: e7e7 b.n 800508e <_raise_r+0x12>
80050be: 2400 movs r4, #0
80050c0: 4628 mov r0, r5
80050c2: f842 4025 str.w r4, [r2, r5, lsl #2]
80050c6: 4798 blx r3
80050c8: 2000 movs r0, #0
80050ca: e7e0 b.n 800508e <_raise_r+0x12>
080050cc <raise>:
80050cc: 4b02 ldr r3, [pc, #8] ; (80050d8 <raise+0xc>)
80050ce: 4601 mov r1, r0
80050d0: 6818 ldr r0, [r3, #0]
80050d2: f7ff bfd3 b.w 800507c <_raise_r>
80050d6: bf00 nop
80050d8: 2000000c .word 0x2000000c
080050dc <_kill_r>:
80050dc: b538 push {r3, r4, r5, lr}
80050de: 2300 movs r3, #0
80050e0: 4d06 ldr r5, [pc, #24] ; (80050fc <_kill_r+0x20>)
80050e2: 4604 mov r4, r0
80050e4: 4608 mov r0, r1
80050e6: 4611 mov r1, r2
80050e8: 602b str r3, [r5, #0]
80050ea: f7fc faf8 bl 80016de <_kill>
80050ee: 1c43 adds r3, r0, #1
80050f0: d102 bne.n 80050f8 <_kill_r+0x1c>
80050f2: 682b ldr r3, [r5, #0]
80050f4: b103 cbz r3, 80050f8 <_kill_r+0x1c>
80050f6: 6023 str r3, [r4, #0]
80050f8: bd38 pop {r3, r4, r5, pc}
80050fa: bf00 nop
80050fc: 2000089c .word 0x2000089c
08005100 <_getpid_r>:
8005100: f7fc bae6 b.w 80016d0 <_getpid>
08005104 <siprintf>:
8005104: b40e push {r1, r2, r3}
8005106: f06f 4100 mvn.w r1, #2147483648 ; 0x80000000
800510a: b500 push {lr}
800510c: b09c sub sp, #112 ; 0x70
800510e: ab1d add r3, sp, #116 ; 0x74
8005110: 9002 str r0, [sp, #8]
8005112: 9006 str r0, [sp, #24]
8005114: 9107 str r1, [sp, #28]
8005116: 9104 str r1, [sp, #16]
8005118: 4808 ldr r0, [pc, #32] ; (800513c <siprintf+0x38>)
800511a: 4909 ldr r1, [pc, #36] ; (8005140 <siprintf+0x3c>)
800511c: f853 2b04 ldr.w r2, [r3], #4
8005120: 9105 str r1, [sp, #20]
8005122: 6800 ldr r0, [r0, #0]
8005124: a902 add r1, sp, #8
8005126: 9301 str r3, [sp, #4]
8005128: f000 f874 bl 8005214 <_svfiprintf_r>
800512c: 2200 movs r2, #0
800512e: 9b02 ldr r3, [sp, #8]
8005130: 701a strb r2, [r3, #0]
8005132: b01c add sp, #112 ; 0x70
8005134: f85d eb04 ldr.w lr, [sp], #4
8005138: b003 add sp, #12
800513a: 4770 bx lr
800513c: 2000000c .word 0x2000000c
8005140: ffff0208 .word 0xffff0208
08005144 <__malloc_lock>:
8005144: 4801 ldr r0, [pc, #4] ; (800514c <__malloc_lock+0x8>)
8005146: f000 bafb b.w 8005740 <__retarget_lock_acquire_recursive>
800514a: bf00 nop
800514c: 200008a0 .word 0x200008a0
08005150 <__malloc_unlock>:
8005150: 4801 ldr r0, [pc, #4] ; (8005158 <__malloc_unlock+0x8>)
8005152: f000 baf6 b.w 8005742 <__retarget_lock_release_recursive>
8005156: bf00 nop
8005158: 200008a0 .word 0x200008a0
0800515c <__ssputs_r>:
800515c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
8005160: 688e ldr r6, [r1, #8]
8005162: 4682 mov sl, r0
8005164: 429e cmp r6, r3
8005166: 460c mov r4, r1
8005168: 4690 mov r8, r2
800516a: 461f mov r7, r3
800516c: d838 bhi.n 80051e0 <__ssputs_r+0x84>
800516e: 898a ldrh r2, [r1, #12]
8005170: f412 6f90 tst.w r2, #1152 ; 0x480
8005174: d032 beq.n 80051dc <__ssputs_r+0x80>
8005176: 6825 ldr r5, [r4, #0]
8005178: 6909 ldr r1, [r1, #16]
800517a: 3301 adds r3, #1
800517c: eba5 0901 sub.w r9, r5, r1
8005180: 6965 ldr r5, [r4, #20]
8005182: 444b add r3, r9
8005184: eb05 0545 add.w r5, r5, r5, lsl #1
8005188: eb05 75d5 add.w r5, r5, r5, lsr #31
800518c: 106d asrs r5, r5, #1
800518e: 429d cmp r5, r3
8005190: bf38 it cc
8005192: 461d movcc r5, r3
8005194: 0553 lsls r3, r2, #21
8005196: d531 bpl.n 80051fc <__ssputs_r+0xa0>
8005198: 4629 mov r1, r5
800519a: f7ff feeb bl 8004f74 <_malloc_r>
800519e: 4606 mov r6, r0
80051a0: b950 cbnz r0, 80051b8 <__ssputs_r+0x5c>
80051a2: 230c movs r3, #12
80051a4: f04f 30ff mov.w r0, #4294967295
80051a8: f8ca 3000 str.w r3, [sl]
80051ac: 89a3 ldrh r3, [r4, #12]
80051ae: f043 0340 orr.w r3, r3, #64 ; 0x40
80051b2: 81a3 strh r3, [r4, #12]
80051b4: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80051b8: 464a mov r2, r9
80051ba: 6921 ldr r1, [r4, #16]
80051bc: f7ff fe5c bl 8004e78 <memcpy>
80051c0: 89a3 ldrh r3, [r4, #12]
80051c2: f423 6390 bic.w r3, r3, #1152 ; 0x480
80051c6: f043 0380 orr.w r3, r3, #128 ; 0x80
80051ca: 81a3 strh r3, [r4, #12]
80051cc: 6126 str r6, [r4, #16]
80051ce: 444e add r6, r9
80051d0: 6026 str r6, [r4, #0]
80051d2: 463e mov r6, r7
80051d4: 6165 str r5, [r4, #20]
80051d6: eba5 0509 sub.w r5, r5, r9
80051da: 60a5 str r5, [r4, #8]
80051dc: 42be cmp r6, r7
80051de: d900 bls.n 80051e2 <__ssputs_r+0x86>
80051e0: 463e mov r6, r7
80051e2: 4632 mov r2, r6
80051e4: 4641 mov r1, r8
80051e6: 6820 ldr r0, [r4, #0]
80051e8: f000 faba bl 8005760 <memmove>
80051ec: 68a3 ldr r3, [r4, #8]
80051ee: 2000 movs r0, #0
80051f0: 1b9b subs r3, r3, r6
80051f2: 60a3 str r3, [r4, #8]
80051f4: 6823 ldr r3, [r4, #0]
80051f6: 4433 add r3, r6
80051f8: 6023 str r3, [r4, #0]
80051fa: e7db b.n 80051b4 <__ssputs_r+0x58>
80051fc: 462a mov r2, r5
80051fe: f000 fac9 bl 8005794 <_realloc_r>
8005202: 4606 mov r6, r0
8005204: 2800 cmp r0, #0
8005206: d1e1 bne.n 80051cc <__ssputs_r+0x70>
8005208: 4650 mov r0, sl
800520a: 6921 ldr r1, [r4, #16]
800520c: f7ff fe4a bl 8004ea4 <_free_r>
8005210: e7c7 b.n 80051a2 <__ssputs_r+0x46>
...
08005214 <_svfiprintf_r>:
8005214: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
8005218: 4698 mov r8, r3
800521a: 898b ldrh r3, [r1, #12]
800521c: 4607 mov r7, r0
800521e: 061b lsls r3, r3, #24
8005220: 460d mov r5, r1
8005222: 4614 mov r4, r2
8005224: b09d sub sp, #116 ; 0x74
8005226: d50e bpl.n 8005246 <_svfiprintf_r+0x32>
8005228: 690b ldr r3, [r1, #16]
800522a: b963 cbnz r3, 8005246 <_svfiprintf_r+0x32>
800522c: 2140 movs r1, #64 ; 0x40
800522e: f7ff fea1 bl 8004f74 <_malloc_r>
8005232: 6028 str r0, [r5, #0]
8005234: 6128 str r0, [r5, #16]
8005236: b920 cbnz r0, 8005242 <_svfiprintf_r+0x2e>
8005238: 230c movs r3, #12
800523a: 603b str r3, [r7, #0]
800523c: f04f 30ff mov.w r0, #4294967295
8005240: e0d1 b.n 80053e6 <_svfiprintf_r+0x1d2>
8005242: 2340 movs r3, #64 ; 0x40
8005244: 616b str r3, [r5, #20]
8005246: 2300 movs r3, #0
8005248: 9309 str r3, [sp, #36] ; 0x24
800524a: 2320 movs r3, #32
800524c: f88d 3029 strb.w r3, [sp, #41] ; 0x29
8005250: 2330 movs r3, #48 ; 0x30
8005252: f04f 0901 mov.w r9, #1
8005256: f8cd 800c str.w r8, [sp, #12]
800525a: f8df 81a4 ldr.w r8, [pc, #420] ; 8005400 <_svfiprintf_r+0x1ec>
800525e: f88d 302a strb.w r3, [sp, #42] ; 0x2a
8005262: 4623 mov r3, r4
8005264: 469a mov sl, r3
8005266: f813 2b01 ldrb.w r2, [r3], #1
800526a: b10a cbz r2, 8005270 <_svfiprintf_r+0x5c>
800526c: 2a25 cmp r2, #37 ; 0x25
800526e: d1f9 bne.n 8005264 <_svfiprintf_r+0x50>
8005270: ebba 0b04 subs.w fp, sl, r4
8005274: d00b beq.n 800528e <_svfiprintf_r+0x7a>
8005276: 465b mov r3, fp
8005278: 4622 mov r2, r4
800527a: 4629 mov r1, r5
800527c: 4638 mov r0, r7
800527e: f7ff ff6d bl 800515c <__ssputs_r>
8005282: 3001 adds r0, #1
8005284: f000 80aa beq.w 80053dc <_svfiprintf_r+0x1c8>
8005288: 9a09 ldr r2, [sp, #36] ; 0x24
800528a: 445a add r2, fp
800528c: 9209 str r2, [sp, #36] ; 0x24
800528e: f89a 3000 ldrb.w r3, [sl]
8005292: 2b00 cmp r3, #0
8005294: f000 80a2 beq.w 80053dc <_svfiprintf_r+0x1c8>
8005298: 2300 movs r3, #0
800529a: f04f 32ff mov.w r2, #4294967295
800529e: e9cd 2305 strd r2, r3, [sp, #20]
80052a2: f10a 0a01 add.w sl, sl, #1
80052a6: 9304 str r3, [sp, #16]
80052a8: 9307 str r3, [sp, #28]
80052aa: f88d 3053 strb.w r3, [sp, #83] ; 0x53
80052ae: 931a str r3, [sp, #104] ; 0x68
80052b0: 4654 mov r4, sl
80052b2: 2205 movs r2, #5
80052b4: f814 1b01 ldrb.w r1, [r4], #1
80052b8: 4851 ldr r0, [pc, #324] ; (8005400 <_svfiprintf_r+0x1ec>)
80052ba: f000 fa43 bl 8005744 <memchr>
80052be: 9a04 ldr r2, [sp, #16]
80052c0: b9d8 cbnz r0, 80052fa <_svfiprintf_r+0xe6>
80052c2: 06d0 lsls r0, r2, #27
80052c4: bf44 itt mi
80052c6: 2320 movmi r3, #32
80052c8: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53
80052cc: 0711 lsls r1, r2, #28
80052ce: bf44 itt mi
80052d0: 232b movmi r3, #43 ; 0x2b
80052d2: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53
80052d6: f89a 3000 ldrb.w r3, [sl]
80052da: 2b2a cmp r3, #42 ; 0x2a
80052dc: d015 beq.n 800530a <_svfiprintf_r+0xf6>
80052de: 4654 mov r4, sl
80052e0: 2000 movs r0, #0
80052e2: f04f 0c0a mov.w ip, #10
80052e6: 9a07 ldr r2, [sp, #28]
80052e8: 4621 mov r1, r4
80052ea: f811 3b01 ldrb.w r3, [r1], #1
80052ee: 3b30 subs r3, #48 ; 0x30
80052f0: 2b09 cmp r3, #9
80052f2: d94e bls.n 8005392 <_svfiprintf_r+0x17e>
80052f4: b1b0 cbz r0, 8005324 <_svfiprintf_r+0x110>
80052f6: 9207 str r2, [sp, #28]
80052f8: e014 b.n 8005324 <_svfiprintf_r+0x110>
80052fa: eba0 0308 sub.w r3, r0, r8
80052fe: fa09 f303 lsl.w r3, r9, r3
8005302: 4313 orrs r3, r2
8005304: 46a2 mov sl, r4
8005306: 9304 str r3, [sp, #16]
8005308: e7d2 b.n 80052b0 <_svfiprintf_r+0x9c>
800530a: 9b03 ldr r3, [sp, #12]
800530c: 1d19 adds r1, r3, #4
800530e: 681b ldr r3, [r3, #0]
8005310: 9103 str r1, [sp, #12]
8005312: 2b00 cmp r3, #0
8005314: bfbb ittet lt
8005316: 425b neglt r3, r3
8005318: f042 0202 orrlt.w r2, r2, #2
800531c: 9307 strge r3, [sp, #28]
800531e: 9307 strlt r3, [sp, #28]
8005320: bfb8 it lt
8005322: 9204 strlt r2, [sp, #16]
8005324: 7823 ldrb r3, [r4, #0]
8005326: 2b2e cmp r3, #46 ; 0x2e
8005328: d10c bne.n 8005344 <_svfiprintf_r+0x130>
800532a: 7863 ldrb r3, [r4, #1]
800532c: 2b2a cmp r3, #42 ; 0x2a
800532e: d135 bne.n 800539c <_svfiprintf_r+0x188>
8005330: 9b03 ldr r3, [sp, #12]
8005332: 3402 adds r4, #2
8005334: 1d1a adds r2, r3, #4
8005336: 681b ldr r3, [r3, #0]
8005338: 9203 str r2, [sp, #12]
800533a: 2b00 cmp r3, #0
800533c: bfb8 it lt
800533e: f04f 33ff movlt.w r3, #4294967295
8005342: 9305 str r3, [sp, #20]
8005344: f8df a0bc ldr.w sl, [pc, #188] ; 8005404 <_svfiprintf_r+0x1f0>
8005348: 2203 movs r2, #3
800534a: 4650 mov r0, sl
800534c: 7821 ldrb r1, [r4, #0]
800534e: f000 f9f9 bl 8005744 <memchr>
8005352: b140 cbz r0, 8005366 <_svfiprintf_r+0x152>
8005354: 2340 movs r3, #64 ; 0x40
8005356: eba0 000a sub.w r0, r0, sl
800535a: fa03 f000 lsl.w r0, r3, r0
800535e: 9b04 ldr r3, [sp, #16]
8005360: 3401 adds r4, #1
8005362: 4303 orrs r3, r0
8005364: 9304 str r3, [sp, #16]
8005366: f814 1b01 ldrb.w r1, [r4], #1
800536a: 2206 movs r2, #6
800536c: 4826 ldr r0, [pc, #152] ; (8005408 <_svfiprintf_r+0x1f4>)
800536e: f88d 1028 strb.w r1, [sp, #40] ; 0x28
8005372: f000 f9e7 bl 8005744 <memchr>
8005376: 2800 cmp r0, #0
8005378: d038 beq.n 80053ec <_svfiprintf_r+0x1d8>
800537a: 4b24 ldr r3, [pc, #144] ; (800540c <_svfiprintf_r+0x1f8>)
800537c: bb1b cbnz r3, 80053c6 <_svfiprintf_r+0x1b2>
800537e: 9b03 ldr r3, [sp, #12]
8005380: 3307 adds r3, #7
8005382: f023 0307 bic.w r3, r3, #7
8005386: 3308 adds r3, #8
8005388: 9303 str r3, [sp, #12]
800538a: 9b09 ldr r3, [sp, #36] ; 0x24
800538c: 4433 add r3, r6
800538e: 9309 str r3, [sp, #36] ; 0x24
8005390: e767 b.n 8005262 <_svfiprintf_r+0x4e>
8005392: 460c mov r4, r1
8005394: 2001 movs r0, #1
8005396: fb0c 3202 mla r2, ip, r2, r3
800539a: e7a5 b.n 80052e8 <_svfiprintf_r+0xd4>
800539c: 2300 movs r3, #0
800539e: f04f 0c0a mov.w ip, #10
80053a2: 4619 mov r1, r3
80053a4: 3401 adds r4, #1
80053a6: 9305 str r3, [sp, #20]
80053a8: 4620 mov r0, r4
80053aa: f810 2b01 ldrb.w r2, [r0], #1
80053ae: 3a30 subs r2, #48 ; 0x30
80053b0: 2a09 cmp r2, #9
80053b2: d903 bls.n 80053bc <_svfiprintf_r+0x1a8>
80053b4: 2b00 cmp r3, #0
80053b6: d0c5 beq.n 8005344 <_svfiprintf_r+0x130>
80053b8: 9105 str r1, [sp, #20]
80053ba: e7c3 b.n 8005344 <_svfiprintf_r+0x130>
80053bc: 4604 mov r4, r0
80053be: 2301 movs r3, #1
80053c0: fb0c 2101 mla r1, ip, r1, r2
80053c4: e7f0 b.n 80053a8 <_svfiprintf_r+0x194>
80053c6: ab03 add r3, sp, #12
80053c8: 9300 str r3, [sp, #0]
80053ca: 462a mov r2, r5
80053cc: 4638 mov r0, r7
80053ce: 4b10 ldr r3, [pc, #64] ; (8005410 <_svfiprintf_r+0x1fc>)
80053d0: a904 add r1, sp, #16
80053d2: f3af 8000 nop.w
80053d6: 1c42 adds r2, r0, #1
80053d8: 4606 mov r6, r0
80053da: d1d6 bne.n 800538a <_svfiprintf_r+0x176>
80053dc: 89ab ldrh r3, [r5, #12]
80053de: 065b lsls r3, r3, #25
80053e0: f53f af2c bmi.w 800523c <_svfiprintf_r+0x28>
80053e4: 9809 ldr r0, [sp, #36] ; 0x24
80053e6: b01d add sp, #116 ; 0x74
80053e8: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
80053ec: ab03 add r3, sp, #12
80053ee: 9300 str r3, [sp, #0]
80053f0: 462a mov r2, r5
80053f2: 4638 mov r0, r7
80053f4: 4b06 ldr r3, [pc, #24] ; (8005410 <_svfiprintf_r+0x1fc>)
80053f6: a904 add r1, sp, #16
80053f8: f000 f87c bl 80054f4 <_printf_i>
80053fc: e7eb b.n 80053d6 <_svfiprintf_r+0x1c2>
80053fe: bf00 nop
8005400: 08005a48 .word 0x08005a48
8005404: 08005a4e .word 0x08005a4e
8005408: 08005a52 .word 0x08005a52
800540c: 00000000 .word 0x00000000
8005410: 0800515d .word 0x0800515d
08005414 <_printf_common>:
8005414: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
8005418: 4616 mov r6, r2
800541a: 4699 mov r9, r3
800541c: 688a ldr r2, [r1, #8]
800541e: 690b ldr r3, [r1, #16]
8005420: 4607 mov r7, r0
8005422: 4293 cmp r3, r2
8005424: bfb8 it lt
8005426: 4613 movlt r3, r2
8005428: 6033 str r3, [r6, #0]
800542a: f891 2043 ldrb.w r2, [r1, #67] ; 0x43
800542e: 460c mov r4, r1
8005430: f8dd 8020 ldr.w r8, [sp, #32]
8005434: b10a cbz r2, 800543a <_printf_common+0x26>
8005436: 3301 adds r3, #1
8005438: 6033 str r3, [r6, #0]
800543a: 6823 ldr r3, [r4, #0]
800543c: 0699 lsls r1, r3, #26
800543e: bf42 ittt mi
8005440: 6833 ldrmi r3, [r6, #0]
8005442: 3302 addmi r3, #2
8005444: 6033 strmi r3, [r6, #0]
8005446: 6825 ldr r5, [r4, #0]
8005448: f015 0506 ands.w r5, r5, #6
800544c: d106 bne.n 800545c <_printf_common+0x48>
800544e: f104 0a19 add.w sl, r4, #25
8005452: 68e3 ldr r3, [r4, #12]
8005454: 6832 ldr r2, [r6, #0]
8005456: 1a9b subs r3, r3, r2
8005458: 42ab cmp r3, r5
800545a: dc28 bgt.n 80054ae <_printf_common+0x9a>
800545c: f894 2043 ldrb.w r2, [r4, #67] ; 0x43
8005460: 1e13 subs r3, r2, #0
8005462: 6822 ldr r2, [r4, #0]
8005464: bf18 it ne
8005466: 2301 movne r3, #1
8005468: 0692 lsls r2, r2, #26
800546a: d42d bmi.n 80054c8 <_printf_common+0xb4>
800546c: 4649 mov r1, r9
800546e: 4638 mov r0, r7
8005470: f104 0243 add.w r2, r4, #67 ; 0x43
8005474: 47c0 blx r8
8005476: 3001 adds r0, #1
8005478: d020 beq.n 80054bc <_printf_common+0xa8>
800547a: 6823 ldr r3, [r4, #0]
800547c: 68e5 ldr r5, [r4, #12]
800547e: f003 0306 and.w r3, r3, #6
8005482: 2b04 cmp r3, #4
8005484: bf18 it ne
8005486: 2500 movne r5, #0
8005488: 6832 ldr r2, [r6, #0]
800548a: f04f 0600 mov.w r6, #0
800548e: 68a3 ldr r3, [r4, #8]
8005490: bf08 it eq
8005492: 1aad subeq r5, r5, r2
8005494: 6922 ldr r2, [r4, #16]
8005496: bf08 it eq
8005498: ea25 75e5 biceq.w r5, r5, r5, asr #31
800549c: 4293 cmp r3, r2
800549e: bfc4 itt gt
80054a0: 1a9b subgt r3, r3, r2
80054a2: 18ed addgt r5, r5, r3
80054a4: 341a adds r4, #26
80054a6: 42b5 cmp r5, r6
80054a8: d11a bne.n 80054e0 <_printf_common+0xcc>
80054aa: 2000 movs r0, #0
80054ac: e008 b.n 80054c0 <_printf_common+0xac>
80054ae: 2301 movs r3, #1
80054b0: 4652 mov r2, sl
80054b2: 4649 mov r1, r9
80054b4: 4638 mov r0, r7
80054b6: 47c0 blx r8
80054b8: 3001 adds r0, #1
80054ba: d103 bne.n 80054c4 <_printf_common+0xb0>
80054bc: f04f 30ff mov.w r0, #4294967295
80054c0: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80054c4: 3501 adds r5, #1
80054c6: e7c4 b.n 8005452 <_printf_common+0x3e>
80054c8: 2030 movs r0, #48 ; 0x30
80054ca: 18e1 adds r1, r4, r3
80054cc: f881 0043 strb.w r0, [r1, #67] ; 0x43
80054d0: 1c5a adds r2, r3, #1
80054d2: f894 1045 ldrb.w r1, [r4, #69] ; 0x45
80054d6: 4422 add r2, r4
80054d8: 3302 adds r3, #2
80054da: f882 1043 strb.w r1, [r2, #67] ; 0x43
80054de: e7c5 b.n 800546c <_printf_common+0x58>
80054e0: 2301 movs r3, #1
80054e2: 4622 mov r2, r4
80054e4: 4649 mov r1, r9
80054e6: 4638 mov r0, r7
80054e8: 47c0 blx r8
80054ea: 3001 adds r0, #1
80054ec: d0e6 beq.n 80054bc <_printf_common+0xa8>
80054ee: 3601 adds r6, #1
80054f0: e7d9 b.n 80054a6 <_printf_common+0x92>
...
080054f4 <_printf_i>:
80054f4: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
80054f8: 7e0f ldrb r7, [r1, #24]
80054fa: 4691 mov r9, r2
80054fc: 2f78 cmp r7, #120 ; 0x78
80054fe: 4680 mov r8, r0
8005500: 460c mov r4, r1
8005502: 469a mov sl, r3
8005504: 9d0c ldr r5, [sp, #48] ; 0x30
8005506: f101 0243 add.w r2, r1, #67 ; 0x43
800550a: d807 bhi.n 800551c <_printf_i+0x28>
800550c: 2f62 cmp r7, #98 ; 0x62
800550e: d80a bhi.n 8005526 <_printf_i+0x32>
8005510: 2f00 cmp r7, #0
8005512: f000 80d9 beq.w 80056c8 <_printf_i+0x1d4>
8005516: 2f58 cmp r7, #88 ; 0x58
8005518: f000 80a4 beq.w 8005664 <_printf_i+0x170>
800551c: f104 0542 add.w r5, r4, #66 ; 0x42
8005520: f884 7042 strb.w r7, [r4, #66] ; 0x42
8005524: e03a b.n 800559c <_printf_i+0xa8>
8005526: f1a7 0363 sub.w r3, r7, #99 ; 0x63
800552a: 2b15 cmp r3, #21
800552c: d8f6 bhi.n 800551c <_printf_i+0x28>
800552e: a101 add r1, pc, #4 ; (adr r1, 8005534 <_printf_i+0x40>)
8005530: f851 f023 ldr.w pc, [r1, r3, lsl #2]
8005534: 0800558d .word 0x0800558d
8005538: 080055a1 .word 0x080055a1
800553c: 0800551d .word 0x0800551d
8005540: 0800551d .word 0x0800551d
8005544: 0800551d .word 0x0800551d
8005548: 0800551d .word 0x0800551d
800554c: 080055a1 .word 0x080055a1
8005550: 0800551d .word 0x0800551d
8005554: 0800551d .word 0x0800551d
8005558: 0800551d .word 0x0800551d
800555c: 0800551d .word 0x0800551d
8005560: 080056af .word 0x080056af
8005564: 080055d1 .word 0x080055d1
8005568: 08005691 .word 0x08005691
800556c: 0800551d .word 0x0800551d
8005570: 0800551d .word 0x0800551d
8005574: 080056d1 .word 0x080056d1
8005578: 0800551d .word 0x0800551d
800557c: 080055d1 .word 0x080055d1
8005580: 0800551d .word 0x0800551d
8005584: 0800551d .word 0x0800551d
8005588: 08005699 .word 0x08005699
800558c: 682b ldr r3, [r5, #0]
800558e: 1d1a adds r2, r3, #4
8005590: 681b ldr r3, [r3, #0]
8005592: 602a str r2, [r5, #0]
8005594: f104 0542 add.w r5, r4, #66 ; 0x42
8005598: f884 3042 strb.w r3, [r4, #66] ; 0x42
800559c: 2301 movs r3, #1
800559e: e0a4 b.n 80056ea <_printf_i+0x1f6>
80055a0: 6820 ldr r0, [r4, #0]
80055a2: 6829 ldr r1, [r5, #0]
80055a4: 0606 lsls r6, r0, #24
80055a6: f101 0304 add.w r3, r1, #4
80055aa: d50a bpl.n 80055c2 <_printf_i+0xce>
80055ac: 680e ldr r6, [r1, #0]
80055ae: 602b str r3, [r5, #0]
80055b0: 2e00 cmp r6, #0
80055b2: da03 bge.n 80055bc <_printf_i+0xc8>
80055b4: 232d movs r3, #45 ; 0x2d
80055b6: 4276 negs r6, r6
80055b8: f884 3043 strb.w r3, [r4, #67] ; 0x43
80055bc: 230a movs r3, #10
80055be: 485e ldr r0, [pc, #376] ; (8005738 <_printf_i+0x244>)
80055c0: e019 b.n 80055f6 <_printf_i+0x102>
80055c2: 680e ldr r6, [r1, #0]
80055c4: f010 0f40 tst.w r0, #64 ; 0x40
80055c8: 602b str r3, [r5, #0]
80055ca: bf18 it ne
80055cc: b236 sxthne r6, r6
80055ce: e7ef b.n 80055b0 <_printf_i+0xbc>
80055d0: 682b ldr r3, [r5, #0]
80055d2: 6820 ldr r0, [r4, #0]
80055d4: 1d19 adds r1, r3, #4
80055d6: 6029 str r1, [r5, #0]
80055d8: 0601 lsls r1, r0, #24
80055da: d501 bpl.n 80055e0 <_printf_i+0xec>
80055dc: 681e ldr r6, [r3, #0]
80055de: e002 b.n 80055e6 <_printf_i+0xf2>
80055e0: 0646 lsls r6, r0, #25
80055e2: d5fb bpl.n 80055dc <_printf_i+0xe8>
80055e4: 881e ldrh r6, [r3, #0]
80055e6: 2f6f cmp r7, #111 ; 0x6f
80055e8: bf0c ite eq
80055ea: 2308 moveq r3, #8
80055ec: 230a movne r3, #10
80055ee: 4852 ldr r0, [pc, #328] ; (8005738 <_printf_i+0x244>)
80055f0: 2100 movs r1, #0
80055f2: f884 1043 strb.w r1, [r4, #67] ; 0x43
80055f6: 6865 ldr r5, [r4, #4]
80055f8: 2d00 cmp r5, #0
80055fa: bfa8 it ge
80055fc: 6821 ldrge r1, [r4, #0]
80055fe: 60a5 str r5, [r4, #8]
8005600: bfa4 itt ge
8005602: f021 0104 bicge.w r1, r1, #4
8005606: 6021 strge r1, [r4, #0]
8005608: b90e cbnz r6, 800560e <_printf_i+0x11a>
800560a: 2d00 cmp r5, #0
800560c: d04d beq.n 80056aa <_printf_i+0x1b6>
800560e: 4615 mov r5, r2
8005610: fbb6 f1f3 udiv r1, r6, r3
8005614: fb03 6711 mls r7, r3, r1, r6
8005618: 5dc7 ldrb r7, [r0, r7]
800561a: f805 7d01 strb.w r7, [r5, #-1]!
800561e: 4637 mov r7, r6
8005620: 42bb cmp r3, r7
8005622: 460e mov r6, r1
8005624: d9f4 bls.n 8005610 <_printf_i+0x11c>
8005626: 2b08 cmp r3, #8
8005628: d10b bne.n 8005642 <_printf_i+0x14e>
800562a: 6823 ldr r3, [r4, #0]
800562c: 07de lsls r6, r3, #31
800562e: d508 bpl.n 8005642 <_printf_i+0x14e>
8005630: 6923 ldr r3, [r4, #16]
8005632: 6861 ldr r1, [r4, #4]
8005634: 4299 cmp r1, r3
8005636: bfde ittt le
8005638: 2330 movle r3, #48 ; 0x30
800563a: f805 3c01 strble.w r3, [r5, #-1]
800563e: f105 35ff addle.w r5, r5, #4294967295
8005642: 1b52 subs r2, r2, r5
8005644: 6122 str r2, [r4, #16]
8005646: 464b mov r3, r9
8005648: 4621 mov r1, r4
800564a: 4640 mov r0, r8
800564c: f8cd a000 str.w sl, [sp]
8005650: aa03 add r2, sp, #12
8005652: f7ff fedf bl 8005414 <_printf_common>
8005656: 3001 adds r0, #1
8005658: d14c bne.n 80056f4 <_printf_i+0x200>
800565a: f04f 30ff mov.w r0, #4294967295
800565e: b004 add sp, #16
8005660: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8005664: 4834 ldr r0, [pc, #208] ; (8005738 <_printf_i+0x244>)
8005666: f881 7045 strb.w r7, [r1, #69] ; 0x45
800566a: 6829 ldr r1, [r5, #0]
800566c: 6823 ldr r3, [r4, #0]
800566e: f851 6b04 ldr.w r6, [r1], #4
8005672: 6029 str r1, [r5, #0]
8005674: 061d lsls r5, r3, #24
8005676: d514 bpl.n 80056a2 <_printf_i+0x1ae>
8005678: 07df lsls r7, r3, #31
800567a: bf44 itt mi
800567c: f043 0320 orrmi.w r3, r3, #32
8005680: 6023 strmi r3, [r4, #0]
8005682: b91e cbnz r6, 800568c <_printf_i+0x198>
8005684: 6823 ldr r3, [r4, #0]
8005686: f023 0320 bic.w r3, r3, #32
800568a: 6023 str r3, [r4, #0]
800568c: 2310 movs r3, #16
800568e: e7af b.n 80055f0 <_printf_i+0xfc>
8005690: 6823 ldr r3, [r4, #0]
8005692: f043 0320 orr.w r3, r3, #32
8005696: 6023 str r3, [r4, #0]
8005698: 2378 movs r3, #120 ; 0x78
800569a: 4828 ldr r0, [pc, #160] ; (800573c <_printf_i+0x248>)
800569c: f884 3045 strb.w r3, [r4, #69] ; 0x45
80056a0: e7e3 b.n 800566a <_printf_i+0x176>
80056a2: 0659 lsls r1, r3, #25
80056a4: bf48 it mi
80056a6: b2b6 uxthmi r6, r6
80056a8: e7e6 b.n 8005678 <_printf_i+0x184>
80056aa: 4615 mov r5, r2
80056ac: e7bb b.n 8005626 <_printf_i+0x132>
80056ae: 682b ldr r3, [r5, #0]
80056b0: 6826 ldr r6, [r4, #0]
80056b2: 1d18 adds r0, r3, #4
80056b4: 6961 ldr r1, [r4, #20]
80056b6: 6028 str r0, [r5, #0]
80056b8: 0635 lsls r5, r6, #24
80056ba: 681b ldr r3, [r3, #0]
80056bc: d501 bpl.n 80056c2 <_printf_i+0x1ce>
80056be: 6019 str r1, [r3, #0]
80056c0: e002 b.n 80056c8 <_printf_i+0x1d4>
80056c2: 0670 lsls r0, r6, #25
80056c4: d5fb bpl.n 80056be <_printf_i+0x1ca>
80056c6: 8019 strh r1, [r3, #0]
80056c8: 2300 movs r3, #0
80056ca: 4615 mov r5, r2
80056cc: 6123 str r3, [r4, #16]
80056ce: e7ba b.n 8005646 <_printf_i+0x152>
80056d0: 682b ldr r3, [r5, #0]
80056d2: 2100 movs r1, #0
80056d4: 1d1a adds r2, r3, #4
80056d6: 602a str r2, [r5, #0]
80056d8: 681d ldr r5, [r3, #0]
80056da: 6862 ldr r2, [r4, #4]
80056dc: 4628 mov r0, r5
80056de: f000 f831 bl 8005744 <memchr>
80056e2: b108 cbz r0, 80056e8 <_printf_i+0x1f4>
80056e4: 1b40 subs r0, r0, r5
80056e6: 6060 str r0, [r4, #4]
80056e8: 6863 ldr r3, [r4, #4]
80056ea: 6123 str r3, [r4, #16]
80056ec: 2300 movs r3, #0
80056ee: f884 3043 strb.w r3, [r4, #67] ; 0x43
80056f2: e7a8 b.n 8005646 <_printf_i+0x152>
80056f4: 462a mov r2, r5
80056f6: 4649 mov r1, r9
80056f8: 4640 mov r0, r8
80056fa: 6923 ldr r3, [r4, #16]
80056fc: 47d0 blx sl
80056fe: 3001 adds r0, #1
8005700: d0ab beq.n 800565a <_printf_i+0x166>
8005702: 6823 ldr r3, [r4, #0]
8005704: 079b lsls r3, r3, #30
8005706: d413 bmi.n 8005730 <_printf_i+0x23c>
8005708: 68e0 ldr r0, [r4, #12]
800570a: 9b03 ldr r3, [sp, #12]
800570c: 4298 cmp r0, r3
800570e: bfb8 it lt
8005710: 4618 movlt r0, r3
8005712: e7a4 b.n 800565e <_printf_i+0x16a>
8005714: 2301 movs r3, #1
8005716: 4632 mov r2, r6
8005718: 4649 mov r1, r9
800571a: 4640 mov r0, r8
800571c: 47d0 blx sl
800571e: 3001 adds r0, #1
8005720: d09b beq.n 800565a <_printf_i+0x166>
8005722: 3501 adds r5, #1
8005724: 68e3 ldr r3, [r4, #12]
8005726: 9903 ldr r1, [sp, #12]
8005728: 1a5b subs r3, r3, r1
800572a: 42ab cmp r3, r5
800572c: dcf2 bgt.n 8005714 <_printf_i+0x220>
800572e: e7eb b.n 8005708 <_printf_i+0x214>
8005730: 2500 movs r5, #0
8005732: f104 0619 add.w r6, r4, #25
8005736: e7f5 b.n 8005724 <_printf_i+0x230>
8005738: 08005a59 .word 0x08005a59
800573c: 08005a6a .word 0x08005a6a
08005740 <__retarget_lock_acquire_recursive>:
8005740: 4770 bx lr
08005742 <__retarget_lock_release_recursive>:
8005742: 4770 bx lr
08005744 <memchr>:
8005744: 4603 mov r3, r0
8005746: b510 push {r4, lr}
8005748: b2c9 uxtb r1, r1
800574a: 4402 add r2, r0
800574c: 4293 cmp r3, r2
800574e: 4618 mov r0, r3
8005750: d101 bne.n 8005756 <memchr+0x12>
8005752: 2000 movs r0, #0
8005754: e003 b.n 800575e <memchr+0x1a>
8005756: 7804 ldrb r4, [r0, #0]
8005758: 3301 adds r3, #1
800575a: 428c cmp r4, r1
800575c: d1f6 bne.n 800574c <memchr+0x8>
800575e: bd10 pop {r4, pc}
08005760 <memmove>:
8005760: 4288 cmp r0, r1
8005762: b510 push {r4, lr}
8005764: eb01 0402 add.w r4, r1, r2
8005768: d902 bls.n 8005770 <memmove+0x10>
800576a: 4284 cmp r4, r0
800576c: 4623 mov r3, r4
800576e: d807 bhi.n 8005780 <memmove+0x20>
8005770: 1e43 subs r3, r0, #1
8005772: 42a1 cmp r1, r4
8005774: d008 beq.n 8005788 <memmove+0x28>
8005776: f811 2b01 ldrb.w r2, [r1], #1
800577a: f803 2f01 strb.w r2, [r3, #1]!
800577e: e7f8 b.n 8005772 <memmove+0x12>
8005780: 4601 mov r1, r0
8005782: 4402 add r2, r0
8005784: 428a cmp r2, r1
8005786: d100 bne.n 800578a <memmove+0x2a>
8005788: bd10 pop {r4, pc}
800578a: f813 4d01 ldrb.w r4, [r3, #-1]!
800578e: f802 4d01 strb.w r4, [r2, #-1]!
8005792: e7f7 b.n 8005784 <memmove+0x24>
08005794 <_realloc_r>:
8005794: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
8005798: 4680 mov r8, r0
800579a: 4614 mov r4, r2
800579c: 460e mov r6, r1
800579e: b921 cbnz r1, 80057aa <_realloc_r+0x16>
80057a0: 4611 mov r1, r2
80057a2: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
80057a6: f7ff bbe5 b.w 8004f74 <_malloc_r>
80057aa: b92a cbnz r2, 80057b8 <_realloc_r+0x24>
80057ac: f7ff fb7a bl 8004ea4 <_free_r>
80057b0: 4625 mov r5, r4
80057b2: 4628 mov r0, r5
80057b4: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
80057b8: f000 f81b bl 80057f2 <_malloc_usable_size_r>
80057bc: 4284 cmp r4, r0
80057be: 4607 mov r7, r0
80057c0: d802 bhi.n 80057c8 <_realloc_r+0x34>
80057c2: ebb4 0f50 cmp.w r4, r0, lsr #1
80057c6: d812 bhi.n 80057ee <_realloc_r+0x5a>
80057c8: 4621 mov r1, r4
80057ca: 4640 mov r0, r8
80057cc: f7ff fbd2 bl 8004f74 <_malloc_r>
80057d0: 4605 mov r5, r0
80057d2: 2800 cmp r0, #0
80057d4: d0ed beq.n 80057b2 <_realloc_r+0x1e>
80057d6: 42bc cmp r4, r7
80057d8: 4622 mov r2, r4
80057da: 4631 mov r1, r6
80057dc: bf28 it cs
80057de: 463a movcs r2, r7
80057e0: f7ff fb4a bl 8004e78 <memcpy>
80057e4: 4631 mov r1, r6
80057e6: 4640 mov r0, r8
80057e8: f7ff fb5c bl 8004ea4 <_free_r>
80057ec: e7e1 b.n 80057b2 <_realloc_r+0x1e>
80057ee: 4635 mov r5, r6
80057f0: e7df b.n 80057b2 <_realloc_r+0x1e>
080057f2 <_malloc_usable_size_r>:
80057f2: f851 3c04 ldr.w r3, [r1, #-4]
80057f6: 1f18 subs r0, r3, #4
80057f8: 2b00 cmp r3, #0
80057fa: bfbc itt lt
80057fc: 580b ldrlt r3, [r1, r0]
80057fe: 18c0 addlt r0, r0, r3
8005800: 4770 bx lr
...
08005804 <_init>:
8005804: b5f8 push {r3, r4, r5, r6, r7, lr}
8005806: bf00 nop
8005808: bcf8 pop {r3, r4, r5, r6, r7}
800580a: bc08 pop {r3}
800580c: 469e mov lr, r3
800580e: 4770 bx lr
08005810 <_fini>:
8005810: b5f8 push {r3, r4, r5, r6, r7, lr}
8005812: bf00 nop
8005814: bcf8 pop {r3, r4, r5, r6, r7}
8005816: bc08 pop {r3}
8005818: 469e mov lr, r3
800581a: 4770 bx lr
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