14 lines
301 B
Plaintext
14 lines
301 B
Plaintext
Release 14.7 - par P.20131013 (nt64)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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Thu Jun 23 00:39:11 2022
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All signals are completely routed.
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WARNING:ParHelpers:361 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC
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warnings.
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CLK_IBUF
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