340 lines
14 KiB
Plaintext
340 lines
14 KiB
Plaintext
Release 14.7 - xst P.20131013 (nt64)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.11 secs
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--> Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.11 secs
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--> Reading design: main.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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9.1) Device utilization summary
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9.2) Partition Resource Summary
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9.3) TIMING REPORT
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "main.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "main"
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Output Format : NGC
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Target Device : xc3s400-4-ft256
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---- Source Options
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Top Module Name : main
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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Safe Implementation : No
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FSM Style : LUT
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RAM Extraction : Yes
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RAM Style : Auto
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ROM Extraction : Yes
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Mux Style : Auto
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Decoder Extraction : YES
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Priority Encoder Extraction : Yes
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Shift Register Extraction : YES
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Logical Shifter Extraction : YES
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XOR Collapsing : YES
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ROM Style : Auto
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Mux Extraction : Yes
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Resource Sharing : YES
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Asynchronous To Synchronous : NO
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Multiplier Style : Auto
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Automatic Register Balancing : No
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---- Target Options
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Add IO Buffers : YES
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Global Maximum Fanout : 500
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Add Generic Clock Buffer(BUFG) : 8
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Register Duplication : YES
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Slice Packing : YES
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Optimize Instantiated Primitives : NO
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Use Clock Enable : Yes
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Use Synchronous Set : Yes
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Use Synchronous Reset : Yes
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Pack IO Registers into IOBs : Auto
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Keep Hierarchy : No
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Netlist Hierarchy : As_Optimized
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RTL Output : Yes
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Global Optimization : AllClockNets
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Read Cores : YES
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Write Timing Constraints : NO
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Cross Clock Analysis : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : Maintain
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Slice Utilization Ratio : 100
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BRAM Utilization Ratio : 100
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Verilog 2001 : YES
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Auto BRAM Packing : NO
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Slice Utilization Ratio Delta : 5
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling vhdl file "C:/Users/Gabriel/Xilinx/Nexys/ULA_P379.vhd" in Library work.
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Entity <ula_p379> compiled.
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Entity <ula_p379> (Architecture <behavioral>) compiled.
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Compiling vhdl file "C:/Users/Gabriel/Xilinx/Nexys/main.vhd" in Library work.
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Architecture behavioral of Entity main is up to date.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for entity <main> in library <work> (architecture <behavioral>).
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Analyzing hierarchy for entity <ULA_P379> in library <work> (architecture <behavioral>).
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing Entity <main> in library <work> (Architecture <behavioral>).
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WARNING:Xst:753 - "C:/Users/Gabriel/Xilinx/Nexys/main.vhd" line 60: Unconnected output port 'CARRY' of component 'ULA_P379'.
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Entity <main> analyzed. Unit <main> generated.
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Analyzing Entity <ULA_P379> in library <work> (Architecture <behavioral>).
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WARNING:Xst:819 - "C:/Users/Gabriel/Xilinx/Nexys/ULA_P379.vhd" line 49: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
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<ULA1>, <ULA2>
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WARNING:Xst:819 - "C:/Users/Gabriel/Xilinx/Nexys/ULA_P379.vhd" line 63: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
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<OUTPUT_ALL>
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Entity <ULA_P379> analyzed. Unit <ULA_P379> generated.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Performing bidirectional port resolution...
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Synthesizing Unit <ULA_P379>.
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Related source file is "C:/Users/Gabriel/Xilinx/Nexys/ULA_P379.vhd".
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WARNING:Xst:1305 - Output <CARRY> is never assigned. Tied to value 0.
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Found 4-bit tristate buffer for signal <OUTPUT_ALL>.
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Found 4-bit addsub for signal <OUTPUT_ALL$share0000>.
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Found 4-bit xor2 for signal <OUTPUT_ALL$xor0000> created at line 57.
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Summary:
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inferred 1 Adder/Subtractor(s).
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inferred 4 Tristate(s).
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Unit <ULA_P379> synthesized.
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Synthesizing Unit <main>.
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Related source file is "C:/Users/Gabriel/Xilinx/Nexys/main.vhd".
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WARNING:Xst:646 - Signal <clk745ms> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal <clk1490ms> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal <clk100k> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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Found 4-bit tristate buffer for signal <LEDS<3:0>>.
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Found 16-bit down counter for signal <cont100k>.
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Found 32-bit up counter for signal <contaux>.
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Summary:
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inferred 2 Counter(s).
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inferred 4 Tristate(s).
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Unit <main> synthesized.
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INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
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=========================================================================
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HDL Synthesis Report
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Macro Statistics
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# Adders/Subtractors : 1
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4-bit addsub : 1
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# Counters : 1
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16-bit down counter : 1
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# Tristates : 5
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1-bit tristate buffer : 4
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4-bit tristate buffer : 1
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# Xors : 1
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4-bit xor2 : 1
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=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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=========================================================================
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=========================================================================
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Advanced HDL Synthesis Report
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Macro Statistics
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# Adders/Subtractors : 1
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4-bit addsub : 1
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# Xors : 1
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4-bit xor2 : 1
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=========================================================================
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=========================================================================
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* Low Level Synthesis *
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=========================================================================
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Optimizing unit <main> ...
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Mapping all equations...
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Building and optimizing final netlist ...
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Found area constraint ratio of 100 (+ 5) on block main, actual ratio is 0.
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Final Macro Processing ...
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=========================================================================
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Final Register Report
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Found no macro
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=========================================================================
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=========================================================================
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* Partition Report *
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=========================================================================
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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=========================================================================
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* Final Report *
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=========================================================================
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Final Results
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RTL Top Level Output File Name : main.ngr
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Top Level Output File Name : main
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Output Format : NGC
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Optimization Goal : Speed
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Keep Hierarchy : No
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Design Statistics
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# IOs : 21
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Cell Usage :
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# BELS : 34
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# GND : 1
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# LUT3 : 2
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# LUT4 : 27
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# MUXF5 : 4
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# IO Buffers : 20
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# IBUF : 12
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# OBUF : 4
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# OBUFT : 4
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=========================================================================
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Device utilization summary:
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---------------------------
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Selected Device : 3s400ft256-4
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Number of Slices: 16 out of 3584 0%
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Number of 4 input LUTs: 29 out of 7168 0%
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Number of IOs: 21
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Number of bonded IOBs: 20 out of 173 11%
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---------------------------
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Partition Resource Summary:
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---------------------------
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No Partitions were found in this design.
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---------------------------
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=========================================================================
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TIMING REPORT
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NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
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FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
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GENERATED AFTER PLACE-and-ROUTE.
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Clock Information:
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------------------
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No clock signals found in this design
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Asynchronous Control Signals Information:
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----------------------------------------
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No asynchronous control signals found in this design
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Timing Summary:
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---------------
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Speed Grade: -4
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Minimum period: No path found
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Minimum input arrival time before clock: No path found
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Maximum output required time after clock: No path found
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Maximum combinational path delay: 16.849ns
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Timing Detail:
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--------------
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All values displayed in nanoseconds (ns)
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=========================================================================
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Timing constraint: Default path analysis
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Total number of paths / destination ports: 209 / 4
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-------------------------------------------------------------------------
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Delay: 16.849ns (Levels of Logic = 8)
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Source: BUT<3> (PAD)
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Destination: LEDS<3> (PAD)
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Data Path: BUT<3> to LEDS<3>
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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IBUF:I->O 8 0.821 1.422 BUT_3_IBUF (BUT_3_IBUF)
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LUT3:I0->O 5 0.551 0.947 ULA0/OUTPUT_ALL_mux0001<0>51 (N4)
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LUT4:I3->O 1 0.551 0.827 ULA0/Maddsub_OUTPUT_ALL_share0000_cy<0>11 (ULA0/Maddsub_OUTPUT_ALL_share0000_cy<0>)
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LUT4:I3->O 2 0.551 1.072 ULA0/Maddsub_OUTPUT_ALL_share0000_cy<1>11 (ULA0/Maddsub_OUTPUT_ALL_share0000_cy<1>)
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LUT4:I1->O 1 0.551 1.140 ULA0/OUTPUT_ALL_mux0001<3>95_SW0 (N16)
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LUT4:I0->O 1 0.551 0.869 ULA0/OUTPUT_ALL_mux0001<3>111_SW0 (N18)
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LUT4:I2->O 1 0.551 0.801 ULA0/OUTPUT_ALL_mux0001<3>111 (LEDS_3_OBUFT)
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OBUFT:I->O 5.644 LEDS_3_OBUFT (LEDS<3>)
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----------------------------------------
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Total 16.849ns (9.771ns logic, 7.078ns route)
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(58.0% logic, 42.0% route)
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=========================================================================
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Total REAL time to Xst completion: 5.00 secs
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Total CPU time to Xst completion: 5.63 secs
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-->
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Total memory usage is 259544 kilobytes
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Number of errors : 0 ( 0 filtered)
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Number of warnings : 7 ( 0 filtered)
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Number of infos : 1 ( 0 filtered)
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