143 lines
4.5 KiB
Plaintext
143 lines
4.5 KiB
Plaintext
Release 14.7 par P.20131013 (nt64)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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GABRIEL-E5400:: Thu Jun 23 00:39:09 2022
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par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
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Constraints file: main.pcf.
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Loading device for application Rf_Device from file '3s400.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\.
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"main" is an NCD, version 3.2, device xc3s400, package ft256, speed -4
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Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
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Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
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INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
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-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
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internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
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reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
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Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
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Device speed data version: "PRODUCTION 1.39 2013-10-13".
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Device Utilization Summary:
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Number of External IOBs 21 out of 173 12%
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Number of LOCed IOBs 21 out of 21 100%
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Number of Slices 16 out of 3584 1%
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Number of SLICEMs 0 out of 1792 0%
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Overall effort level (-ol): High
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Placer effort level (-pl): High
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Placer cost table entry (-t): 1
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Router effort level (-rl): High
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Starting initial Timing Analysis. REAL time: 1 secs
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Finished initial Timing Analysis. REAL time: 1 secs
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WARNING:Par:288 - The signal CLK_IBUF has no load. PAR will not attempt to route this signal.
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Starting Placer
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Total REAL time at the beginning of Placer: 1 secs
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Total CPU time at the beginning of Placer: 1 secs
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Phase 1.1 Initial Placement Analysis
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Phase 1.1 Initial Placement Analysis (Checksum:d14ee8c4) REAL time: 1 secs
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Phase 2.7 Design Feasibility Check
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Phase 2.7 Design Feasibility Check (Checksum:d14ee8c4) REAL time: 1 secs
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Phase 3.31 Local Placement Optimization
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Phase 3.31 Local Placement Optimization (Checksum:d14ee8c4) REAL time: 1 secs
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Phase 4.2 Initial Clock and IO Placement
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Phase 4.2 Initial Clock and IO Placement (Checksum:d14ee8c4) REAL time: 1 secs
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Phase 5.36 Local Placement Optimization
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Phase 5.36 Local Placement Optimization (Checksum:d14ee8c4) REAL time: 1 secs
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Phase 6.8 Global Placement
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..
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Phase 6.8 Global Placement (Checksum:bed1a9c2) REAL time: 1 secs
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Phase 7.5 Local Placement Optimization
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Phase 7.5 Local Placement Optimization (Checksum:bed1a9c2) REAL time: 1 secs
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Phase 8.18 Placement Optimization
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Phase 8.18 Placement Optimization (Checksum:b90bb254) REAL time: 1 secs
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Phase 9.5 Local Placement Optimization
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Phase 9.5 Local Placement Optimization (Checksum:b90bb254) REAL time: 1 secs
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Total REAL time to Placer completion: 1 secs
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Total CPU time to Placer completion: 1 secs
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Writing design to file main.ncd
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Starting Router
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Phase 1 : 130 unrouted; REAL time: 1 secs
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Phase 2 : 130 unrouted; REAL time: 1 secs
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Phase 3 : 59 unrouted; REAL time: 1 secs
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Phase 4 : 59 unrouted; (Par is working to improve performance) REAL time: 1 secs
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Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 1 secs
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Updating file: main.ncd with current fully routed design.
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Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 1 secs
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Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 1 secs
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Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 1 secs
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Total REAL time to Router completion: 1 secs
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Total CPU time to Router completion: 1 secs
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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Generating "PAR" statistics.
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Timing Score: 0 (Setup: 0, Hold: 0)
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Generating Pad Report.
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All signals are completely routed.
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WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
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Total REAL time to PAR completion: 2 secs
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Total CPU time to PAR completion: 2 secs
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Peak Memory Usage: 250 MB
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Placement: Completed - No errors found.
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Routing: Completed - No errors found.
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Number of error messages: 0
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Number of warning messages: 3
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Number of info messages: 1
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Writing design to file main.ncd
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PAR done!
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