36 lines
881 B
VHDL
36 lines
881 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity CONTBIN_4BIT is
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Port ( CLK : in STD_LOGIC;
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CLR : in STD_LOGIC;
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UP : in STD_LOGIC;
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EN : in STD_LOGIC;
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ENOUT : out STD_LOGIC;
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Q : out STD_LOGIC_VECTOR (3 downto 0));
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end CONTBIN_4BIT;
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architecture Behavioral of CONTBIN_4BIT is
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signal cont, proxcont: std_logic_vector (3 downto 0);
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begin
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Q <= cont;
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proxcont <= cont+(not UP & not UP & not UP & '1') when EN='1' else
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cont;
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ENOUT <= '1' when (EN = '1' and UP = '1' and cont = "1111") else
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'1' when (EN = '1' and UP = '0' and cont = "0000") else
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'0';
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process (CLK, CLR)
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begin
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if (CLR = '1') then
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cont <= "0000";
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elsif (CLK'event and CLK = '1') then
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cont <= proxcont;
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end if;
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end process;
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end Behavioral;
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