125 lines
3.4 KiB
VHDL
125 lines
3.4 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 08:45:23 04/26/2023
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-- Design Name:
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-- Module Name: main - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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--use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity main is
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Port ( BUT : in STD_LOGIC_VECTOR (3 downto 0);
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DIPSW : in STD_LOGIC_VECTOR (3 downto 0);
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GPIO : inout STD_LOGIC_VECTOR (7 downto 0);
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CLK27MHz : in STD_LOGIC;
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LEDS : out STD_LOGIC_VECTOR (3 downto 0)
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);
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end main;
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architecture Behavioral of main is
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component display port( NUM7, NUM6, NUM5, NUM4, NUM3, NUM2, NUM1, NUM0: in std_logic_vector(3 downto 0);
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CLK: in std_logic; CS, Dout: out std_logic); end component;
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signal num7,num6,num5,num4,num3,num2,num1,num0: std_logic_vector(3 downto 0);
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signal clkdisp,cs,din: std_logic;
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signal cont100k, contaux: std_logic_vector(23 downto 0);
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signal clk1Hz: std_logic;
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signal clkRX, clkTX, recebendo: std_logic;
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signal cont, cont2: std_logic_vector(23 downto 0);
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signal cont160: std_logic_vector(7 downto 0);
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signal prox, atual, palavra: std_logic_vector(9 downto 0);
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begin
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LEDS <="ZZZZ";
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clk1Hz <= contaux(23);
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process(CLK27MHz)
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begin
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if(CLK27MHz'event and CLK27MHz = '1') then
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if (cont100k = "000000000000000000000000") then cont100k <= "000000000000000100001101";
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else cont100k <= cont100k-"000000000000000000000001";
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end if;
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contaux <= contaux + "000000000000000000000001";
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cont <= cont + "000000000000000000000001";
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cont2 <= cont2 + "000000000000000000000001";
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if(cont = "000000000000101011111100") then
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cont <= "000000000000000000000000";
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end if;
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if(cont2 = "000000000000000010110000") then
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cont2 <= "000000000000000000000000";
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end if;
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end if;
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end process;
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clkTX <= cont(11); --9600bauds
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clkRX <= cont2(7); --9600bauds x16
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prox <= "10" & DIPSW & "1100" when BUT(0) = '1' else
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atual (8 downto 0) & '1';
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GPIO(4) <= atual(9);
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process(clkTX)
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begin
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if (clkTX'event and clkTX = '1') then
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atual <= prox;
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end if;
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end process;
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process(clkRX)
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begin
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if (clkRX'event and clkRX = '1') then
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if(recebendo = '0') then
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if(GPIO(5) = '1') then
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cont160 <= "00000000";
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else
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recebendo <= '1'; --detec<65><63>o do start bit
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end if;
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end if;
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if(recebendo = '1') then
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cont160 <= cont160 + "00000001";
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if (cont160 = "10011100") then
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palavra <= GPIO(5) & palavra (9 downto 1);
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end if;
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if (cont160 = "10011100") then
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recebendo <= '0';
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LEDS <= palavra (4 downto 1);
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end if;
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end if;
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end if;
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end process;
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UDISP: display port map (num7 => num7,num6 => num6,num5 => num5,num4 => num4,num3 => num3,num2 => num2,
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num1 => num1,num0 => num0,clk => clkdisp,cs => cs,dout => din);
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clkdisp <= contaux(5); -- 421875 Hz
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GPIO(0) <= clkdisp;
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GPIO(1) <= cs;
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GPIO(2) <= din;
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end behavioral; |