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-- Company: 
-- Engineer: 
-- 
-- Create Date:    08:45:23 04/26/2023 
-- Design Name: 
-- Module Name:    main - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity main is
	Port ( BUT : in  STD_LOGIC_VECTOR (3 downto 0);
	       DIPSW : in  STD_LOGIC_VECTOR (3 downto 0);
			 GPIO : inout STD_LOGIC_VECTOR (7 downto 0);
			 CLK27MHz : in STD_LOGIC;
          LEDS : out  STD_LOGIC_VECTOR (3 downto 0)
			 );
end main;

architecture Behavioral of main is

component display port( NUM7, NUM6, NUM5, NUM4, NUM3, NUM2, NUM1, NUM0: in std_logic_vector(3 downto 0);
		CLK: in std_logic; CS, Dout: out std_logic); end component;
component ULA_P379
    Port ( ULA1 : in  STD_LOGIC_VECTOR (3 downto 0);
           ULA2 : in  STD_LOGIC_VECTOR (3 downto 0);
           OE : in  STD_LOGIC;
           OPCODE: in STD_LOGIC_VECTOR (3 downto 0);
           CARRY : out  STD_LOGIC;
           OUTPUT : out  STD_LOGIC_VECTOR (3 downto 0));
end component;

signal num7,num6,num5,num4,num3,num2,num1,num0: std_logic_vector(3 downto 0);
signal clkdisp,cs,din: std_logic;
signal cont100k, contaux: std_logic_vector(23 downto 0);
signal clk1Hz: std_logic;

signal clkRX, clkTX, recebendo: std_logic;
signal cont, cont2: std_logic_vector(23 downto 0);
signal cont160: std_logic_vector(7 downto 0);
signal prox, atual, palavra: std_logic_vector(9 downto 0);

begin
LEDS <="ZZZZ";

clk1Hz <= contaux(23); 

process(CLK27MHz)
begin
	if(CLK27MHz'event and CLK27MHz = '1') then
		if (cont100k = "000000000000000000000000") then cont100k <= "000000000000000100001101";
		else cont100k <= cont100k-"000000000000000000000001";
		end if;
		contaux <= contaux + "000000000000000000000001";
		
		cont <= cont + "000000000000000000000001";
		cont2 <= cont2 + "000000000000000000000001";
		if(cont = "000000000000101011111100") then
			cont <= "000000000000000000000000";
		end if;
		if(cont2 = "000000000000000010110000") then
			cont2 <= "000000000000000000000000";
		end if;		
	end if;
end process;

clkTX <= cont(11); --9600bauds
clkRX <= cont2(7); --9600bauds x16

prox <= "10" & DIPSW & "1100" when BUT(0) = '1' else
			atual (8 downto 0) & '1';
GPIO(4) <= atual(9);

process(clkTX)
begin
	if (clkTX'event and clkTX = '1') then
		atual <= prox;
	end if;
end process;

process(clkRX)
begin
	if (clkRX'event and clkRX = '1') then
		if(recebendo = '0') then
			if(GPIO(5) = '1') then
				cont160 <= "00000000";
			else
				recebendo <= '1'; --detecção do start bit
			end if;
		end if;
		if(recebendo = '1') then
			cont160 <= cont160 + "00000001";
			if (cont160(3 downto 0) = "1000") then
				palavra <= GPIO(5) & palavra (9 downto 1);
			end if;
			if (cont160 = "10011100") then
				recebendo <= '0';
				LEDS <= palavra (4 downto 1);
				num0 <= palavra (4 downto 1);
				num1 <= num0;
				num2 <= num1;
				num3 <= num2;
				num4 <= num3;
				num5 <= num4;
				num6 <= num5;
			end if;
		end if;
	end if;
end process;

UDISP: display port map (num7 => num7,num6 => num6,num5 => num5,num4 => num4,num3 => num3,num2 => num2,
                       num1 => num1,num0 => num0,clk => clkdisp,cs => cs,dout => din); 

ULA: ULA_P379 port map (ULA1 => NUM0, ULA2 => NUM1, OE => '1', OPCODE => NUM2, CARRY => GPIO(7), OUTPUT => NUM7);

clkdisp <= contaux(5); -- 421875 Hz
GPIO(0) <= clkdisp;
GPIO(1) <= cs;
GPIO(2) <= din;
end behavioral;