diff --git a/Bluetooth_VHDL.xise b/Bluetooth_VHDL.xise
index 24de74d..c3527cd 100644
--- a/Bluetooth_VHDL.xise
+++ b/Bluetooth_VHDL.xise
@@ -16,6 +16,14 @@
 
   <files>
     <file xil_pn:name="constraints.ucf" xil_pn:type="FILE_UCF">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="main.vhdl" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+    </file>
+    <file xil_pn:name="display.vhdl" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
   </files>
@@ -153,8 +161,9 @@
     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|main|Behavioral" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="main.vhdl" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/main" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -171,6 +180,9 @@
     <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -217,13 +229,14 @@
     <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="main" xil_pn:valueState="default"/>
     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="default"/>
     <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
     <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
     <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -231,10 +244,10 @@
     <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
     <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
     <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="_map.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="_timesim.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="_synthesis.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="_translate.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="main_map.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="main_timesim.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="main_synthesis.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="main_translate.vhd" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
@@ -259,7 +272,7 @@
     <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="main" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -344,6 +357,7 @@
     <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
     <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
     <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-200X" xil_pn:valueState="non-default"/>
diff --git a/display.vhdl b/display.vhdl
new file mode 100644
index 0000000..81c25c6
--- /dev/null
+++ b/display.vhdl
@@ -0,0 +1,77 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity display is		--Implementao do componente Display
+port( NUM7, NUM6, NUM5, NUM4, NUM3, NUM2, NUM1, NUM0: in std_logic_vector(3 downto 0);
+		CLK: in std_logic; 
+		CS, Dout: out std_logic);
+end display;
+
+architecture comportamento of display is
+
+--Declarao e inicializao das variveis---------------------
+signal EN: std_logic_vector(8 downto 0):="000000000"; --ontador de 9 bits
+signal palavra, proxpalavra: std_logic_vector(15 downto 0):="0000000000000000"; --palavra na fila de bits e proxpalavra
+signal proxnum, proxdisplay: std_logic_vector(3 downto 0); --sinais de controle de algarismo e posicao do display
+signal Dis: std_logic_vector(2 downto 0); --Sinal da posicao da posicao a partir do contador de 9 bits
+signal proxfig,Fig: std_logic_vector(1 downto 0):="00"; --Sinal que pega o bit mais significativo e o sexto bit, para a logica de configuraao da palavra
+signal configur: std_logic:='0';
+---------------------------------------------------------------
+
+begin
+
+		Dis<=EN(7 downto 5); --Posicao do display baseada no contador de 9 bits
+		
+		proxnum <= NUM1 when Dis="001" else 
+					  NUM2 when Dis="010" else
+					  NUM3 when Dis="011" else
+					  NUM4 when Dis="100" else
+					  NUM5 when Dis="101" else
+					  NUM6 when Dis="110" else
+					  NUM7 when Dis="111" else
+					  NUM0;
+
+		proxdisplay <= 	"0010" when Dis="001" else 
+								"0011" when Dis="010" else
+								"0100" when Dis="011" else
+								"0101" when Dis="100" else
+								"0110" when Dis="101" else
+								"0111" when Dis="110" else
+								"1000" when Dis="111" else
+								"0001";
+	
+		proxpalavra<=	"0000110000000001" when (configur = '0' and Dis = "000") else -- modo normal
+							"0000101111111111" when (configur = '0' and Dis = "001") else -- scan todos
+							"0000101000001111" when (configur = '0' and Dis = "010") else -- intensidade
+							"0000100111111111" when (configur = '0' and Dis = "011") else -- BCD
+							--"1111111111111111" when (configur = '0' and Dis = "100") else
+							--"0000001100000111";
+							--"0000001101010101";
+							--"0000"&"0001"&"01010111";
+							"0000"&proxdisplay&"0000"&proxnum;
+						
+		 
+	process(CLK) --Processo que atualiza os valores do componente
+	begin
+			if(CLK'event and CLK='0') then -- As configuraes de proximo estado podem ser feitas a qualquer momento
+				EN<=EN+"000000001";
+				configur <= EN(8) or configur;
+
+				if(EN(4) = '0') then --Coloca a proxpalavra na fila de bits no "final" do CS='1' 
+					palavra<=proxpalavra;
+				else
+					palavra<=palavra(14 downto 0)&'0'; --Coloca o proximo bit da fila no bus a cada clock quando CS='0'					
+--					palavra<='0'&palavra(15 downto 1); --Coloca o proximo bit da fila no bus a cada clock quando CS='0'
+				end if;
+			end if;
+	end process;
+
+
+	Dout<=palavra(15); --Bus: sinal sendo passado para o display
+--	Dout<=palavra(0); --Bus: sinal sendo passado para o display
+	CS <= not EN(4);  --Sinal CS que controla a habilitao da escrita no display
+
+end comportamento;
+
diff --git a/main.vhdl b/main.vhdl
index d86bff0..f4212c3 100644
--- a/main.vhdl
+++ b/main.vhdl
@@ -32,12 +32,94 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL;
 --use UNISIM.VComponents.all;
 
 entity main is
+	Port ( BUT : in  STD_LOGIC_VECTOR (3 downto 0);
+	       DIPSW : in  STD_LOGIC_VECTOR (3 downto 0);
+			 GPIO : inout STD_LOGIC_VECTOR (7 downto 0);
+			 CLK27MHz : in STD_LOGIC;
+          LEDS : out  STD_LOGIC_VECTOR (3 downto 0)
+			 );
 end main;
 
 architecture Behavioral of main is
 
+component display port( NUM7, NUM6, NUM5, NUM4, NUM3, NUM2, NUM1, NUM0: in std_logic_vector(3 downto 0);
+		CLK: in std_logic; CS, Dout: out std_logic); end component;
+signal num7,num6,num5,num4,num3,num2,num1,num0: std_logic_vector(3 downto 0);
+signal clkdisp,cs,din: std_logic;
+signal cont100k, contaux: std_logic_vector(23 downto 0);
+signal clk1Hz: std_logic;
+
+signal clkRX, clkTX, recebendo: std_logic;
+signal cont, cont2: std_logic_vector(23 downto 0);
+signal cont160: std_logic_vector(7 downto 0);
+signal prox, atual, palavra: std_logic_vector(9 downto 0);
+
+begin
+LEDS <="ZZZZ";
+
+clk1Hz <= contaux(23); 
+
+process(CLK27MHz)
+begin
+	if(CLK27MHz'event and CLK27MHz = '1') then
+		if (cont100k = "000000000000000000000000") then cont100k <= "000000000000000100001101";
+		else cont100k <= cont100k-"000000000000000000000001";
+		end if;
+		contaux <= contaux + "000000000000000000000001";
+		
+		cont <= cont + "000000000000000000000001";
+		cont2 <= cont2 + "000000000000000000000001";
+		if(cont = "000000000000101011111100") then
+			cont <= "000000000000000000000000";
+		end if;
+		if(cont2 = "000000000000000010110000") then
+			cont2 <= "000000000000000000000000";
+		end if;		
+	end if;
+end process;
+
+clkTX <= cont(11); --9600bauds
+clkRX <= cont2(7); --9600bauds x16
+
+prox <= "10" & DIPSW & "1100" when BUT(0) = '1' else
+			atual (8 downto 0) & '1';
+GPIO(4) <= atual(9);
+
+process(clkTX)
 begin
+	if (clkTX'event and clkTX = '1') then
+		atual <= prox;
+	end if;
+end process;
 
-
-end Behavioral;
-
+process(clkRX)
+begin
+	if (clkRX'event and clkRX = '1') then
+		if(recebendo = '0') then
+			if(GPIO(5) = '1') then
+				cont160 <= "00000000";
+			else
+				recebendo <= '1'; --detecção do start bit
+			end if;
+		end if;
+		if(recebendo = '1') then
+			cont160 <= cont160 + "00000001";
+			if (cont160 = "10011100") then
+				palavra <= GPIO(5) & palavra (9 downto 1);
+			end if;
+			if (cont160 = "10011100") then
+				recebendo <= '0';
+				LEDS <= palavra (4 downto 1);
+			end if;
+		end if;
+	end if;
+end process;
+
+UDISP: display port map (num7 => num7,num6 => num6,num5 => num5,num4 => num4,num3 => num3,num2 => num2,
+                       num1 => num1,num0 => num0,clk => clkdisp,cs => cs,dout => din); 
+
+clkdisp <= contaux(5); -- 421875 Hz
+GPIO(0) <= clkdisp;
+GPIO(1) <= cs;
+GPIO(2) <= din;
+end behavioral;
\ No newline at end of file