]> Release 14.7 Trace (nt64)Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml textovhdl.twx textovhdl.ncd -o textovhdl.twr textovhdl.pcf -ucf restricoes.ucf textovhdl.ncdtextovhdl.ncdtextovhdl.pcftextovhdl.pcfxc6slx16C-2PRODUCTION 1.23 2013-10-1313INFO:Timing:2698 - No timing constraints found, doing default enumeration.INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.CLK27MHzCLK27MHzCLK27MHz3.836GPIO<6>LEDS<3>9.433Wed Jun 08 12:53:12 2022 TraceTrace Settings Peak Memory Usage: 219 MB