208 lines
11 KiB
Plaintext
208 lines
11 KiB
Plaintext
Release 14.7 par P.20131013 (nt64)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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GABRIEL-E5400:: Fri Jun 10 12:44:49 2022
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par -w -intstyle ise -ol high -mt off textovhdl_map.ncd textovhdl.ncd
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textovhdl.pcf
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Constraints file: textovhdl.pcf.
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Loading device for application Rf_Device from file '6slx16.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\.
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"textovhdl" is an NCD, version 3.2, device xc6slx16, package csg324, speed -2
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Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
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Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
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INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
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-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
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internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
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reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
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Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
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Device speed data version: "PRODUCTION 1.23 2013-10-13".
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Device Utilization Summary:
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Slice Logic Utilization:
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Number of Slice Registers: 232 out of 18,224 1%
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Number used as Flip Flops: 232
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Number used as Latches: 0
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Number used as Latch-thrus: 0
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Number used as AND/OR logics: 0
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Number of Slice LUTs: 249 out of 9,112 2%
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Number used as logic: 227 out of 9,112 2%
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Number using O6 output only: 131
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Number using O5 output only: 13
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Number using O5 and O6: 83
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Number used as ROM: 0
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Number used as Memory: 0 out of 2,176 0%
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Number used exclusively as route-thrus: 22
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Number with same-slice register load: 20
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Number with same-slice carry load: 2
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Number with other load: 0
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Slice Logic Distribution:
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Number of occupied Slices: 79 out of 2,278 3%
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Number of MUXCYs used: 68 out of 4,556 1%
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Number of LUT Flip Flop pairs used: 275
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Number with an unused Flip Flop: 92 out of 275 33%
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Number with an unused LUT: 26 out of 275 9%
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Number of fully used LUT-FF pairs: 157 out of 275 57%
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Number of slice register sites lost
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to control set restrictions: 0 out of 18,224 0%
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A LUT Flip Flop pair for this architecture represents one LUT paired with
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one Flip Flop within a slice. A control set is a unique combination of
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clock, reset, set, and enable signals for a registered element.
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The Slice Logic Distribution report is not meaningful if the design is
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over-mapped for a non-slice resource or if Placement fails.
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IO Utilization:
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Number of bonded IOBs: 21 out of 232 9%
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Number of LOCed IOBs: 21 out of 21 100%
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Specific Feature Utilization:
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Number of RAMB16BWERs: 0 out of 32 0%
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Number of RAMB8BWERs: 0 out of 64 0%
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Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
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Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
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Number of BUFG/BUFGMUXs: 6 out of 16 37%
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Number used as BUFGs: 6
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Number used as BUFGMUX: 0
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Number of DCM/DCM_CLKGENs: 0 out of 4 0%
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Number of ILOGIC2/ISERDES2s: 0 out of 248 0%
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Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 248 0%
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Number of OLOGIC2/OSERDES2s: 0 out of 248 0%
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Number of BSCANs: 0 out of 4 0%
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Number of BUFHs: 0 out of 128 0%
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Number of BUFPLLs: 0 out of 8 0%
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Number of BUFPLL_MCBs: 0 out of 4 0%
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Number of DSP48A1s: 0 out of 32 0%
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Number of ICAPs: 0 out of 1 0%
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Number of MCBs: 0 out of 2 0%
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Number of PCILOGICSEs: 0 out of 2 0%
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Number of PLL_ADVs: 0 out of 2 0%
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Number of PMVs: 0 out of 1 0%
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Number of STARTUPs: 0 out of 1 0%
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Number of SUSPEND_SYNCs: 0 out of 1 0%
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Overall effort level (-ol): High
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Router effort level (-rl): High
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Starting initial Timing Analysis. REAL time: 4 secs
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Finished initial Timing Analysis. REAL time: 4 secs
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WARNING:Par:288 - The signal BUT<1>_IBUF has no load. PAR will not attempt to route this signal.
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WARNING:Par:288 - The signal BUT<2>_IBUF has no load. PAR will not attempt to route this signal.
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WARNING:Par:288 - The signal BUT<3>_IBUF has no load. PAR will not attempt to route this signal.
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WARNING:Par:288 - The signal DIPSW<0>_IBUF has no load. PAR will not attempt to route this signal.
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WARNING:Par:288 - The signal DIPSW<1>_IBUF has no load. PAR will not attempt to route this signal.
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WARNING:Par:288 - The signal DIPSW<2>_IBUF has no load. PAR will not attempt to route this signal.
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WARNING:Par:288 - The signal DIPSW<3>_IBUF has no load. PAR will not attempt to route this signal.
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WARNING:Par:288 - The signal GPIO<3>_IBUF has no load. PAR will not attempt to route this signal.
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WARNING:Par:288 - The signal GPIO<6>_IBUF has no load. PAR will not attempt to route this signal.
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WARNING:Par:288 - The signal GPIO<7>_IBUF has no load. PAR will not attempt to route this signal.
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Starting Router
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Phase 1 : 1150 unrouted; REAL time: 4 secs
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Phase 2 : 992 unrouted; REAL time: 4 secs
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Phase 3 : 232 unrouted; REAL time: 5 secs
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Phase 4 : 235 unrouted; (Par is working to improve performance) REAL time: 6 secs
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Updating file: textovhdl.ncd with current fully routed design.
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Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs
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Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs
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Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs
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Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs
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Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs
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Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs
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Total REAL time to Router completion: 7 secs
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Total CPU time to Router completion: 7 secs
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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Generating "PAR" statistics.
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INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode.
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Timing Score: 29 (Setup: 29, Hold: 0)
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Asterisk (*) preceding a constraint indicates it was not met.
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This may be due to a setup or hold violation.
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----------------------------------------------------------------------------------------------------------
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Constraint | Check | Worst Case | Best Case | Timing | Timing
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| | Slack | Achievable | Errors | Score
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----------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net con | SETUP | N/A| 4.530ns| N/A| 0
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t100k_8_BUFG | HOLD | 0.419ns| | 0| 0
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----------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net clk | SETUP | N/A| 2.401ns| N/A| 0
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contbits | HOLD | 0.444ns| | 0| 0
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----------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net clk | SETUP | N/A| 2.125ns| N/A| 0
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shift_BUFG | HOLD | 0.382ns| | 0| 0
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----------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net con | SETUP | N/A| 3.381ns| N/A| 0
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taux_5_BUFG | HOLD | 0.424ns| | 0| 0
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----------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net con | SETUP | N/A| 1.765ns| N/A| 29
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t37915<8> | HOLD | 0.585ns| | 0| 0
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----------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net CLK | SETUP | N/A| 3.572ns| N/A| 0
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27MHz_BUFGP | HOLD | 0.505ns| | 0| 0
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----------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net GPI | SETUP | N/A| 1.818ns| N/A| 0
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O_4_IBUF_BUFG | HOLD | 0.496ns| | 0| 0
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----------------------------------------------------------------------------------------------------------
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1 constraint not met.
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INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
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constraint is not analyzed due to the following: No paths covered by this
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constraint; Other constraints intersect with this constraint; or This
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constraint was disabled by a Path Tracing Control. Please run the Timespec
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Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
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Generating Pad Report.
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All signals are completely routed.
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WARNING:Par:283 - There are 10 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
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Total REAL time to PAR completion: 7 secs
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Total CPU time to PAR completion: 7 secs
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Peak Memory Usage: 313 MB
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Placer: Placement generated during map.
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Routing: Completed - No errors found.
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Number of error messages: 0
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Number of warning messages: 12
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Number of info messages: 2
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Writing design to file textovhdl.ncd
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PAR done!
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