library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity textovhdl is
    Port ( CLK27MHz : in  STD_LOGIC;
           LEDS : out  STD_LOGIC_VECTOR (3 downto 0);
			  BUT : in  STD_LOGIC_VECTOR (3 downto 0);
			  DIPSW : in  STD_LOGIC_VECTOR (3 downto 0);
			  GPIO : inout  STD_LOGIC_VECTOR (7 downto 0)
			  );
end textovhdl;

architecture comportamento of textovhdl is
signal cont100k,contaux: std_logic_vector(23 downto 0);
signal CLK100k,clk621ms,clk25k: std_logic;
signal clkdisp,cs,din: std_logic;
signal num7,num6,num5,num4,num3,num2,num1,num0: std_logic_vector(3 downto 0);
signal EO: std_logic_vector (7 downto 0);
signal S_IR, CLR_cont_S: std_logic;
signal prox_S, atual_S: std_logic_vector(1 downto 0);
signal Q1ms, Q4ms, Q8ms: std_logic;
signal proxshift, atualshift, codigo32: std_logic_vector(31 downto 0);
signal SIshift, ENshift: std_logic;
signal proxnum7: std_logic_vector( 3 downto 0);

signal cont32TXIR: std_logic_vector(7 downto 0);
signal conttimeTXIR: std_logic_vector(11 downto 0);
signal clkcontbits, clrcontbits, contbitsigual32: std_logic;
signal EOTX8: std_logic_vector (1 downto 0);
signal EOTX12: std_logic_vector (2 downto 0);
signal clr12bits, Q900, Q450, Q55, Q165: std_logic;
signal loadshift, clkshift, Q0, outir, clk37915: std_logic;
signal proxTX, atualTX: std_logic_vector(3 downto 0);
signal proxshift32, atualshift32: std_logic_vector (31 downto 0);
signal cont37915: std_logic_vector(23 downto 0);
signal proxCLRCONTBITS, proxCLKCONTBITS, proxCLR12BITS, proxLOADSHIFT, proxCLKSHIFT, proxOUTIR: std_logic;

component display port(	NUM7, NUM6, NUM5, NUM4, NUM3, NUM2, NUM1, NUM0: in std_logic_vector(3 downto 0);
								CLK: in std_logic; 
								CS, Dout: out std_logic
								);
end component;

component CONTBCD_C port( CLK, CLR, UP, EN: in std_logic;
								  ENOUT: out std_logic;
								  Q: out std_logic_vector(3 downto 0)
								  );
end component;

begin

GPIO <= "ZZZZZZZZ";
LEDS <= "ZZZZ";

--contador 8 bits de transmissão, conta até 32
UT0: CONTBCD_C port map(CLK => clkcontbits, CLR => clrcontbits, UP => '1', EN => '1', ENOUT => EOTX8(0), Q => cont32TXIR(3 downto 0));
UT1: CONTBCD_C port map(CLK => clkcontbits, CLR => clrcontbits, UP => '1', EN => EOTX8(0), ENOUT => EOTX8(1), Q => cont32TXIR(7 downto 4));
contbitsigual32 <= '1' when cont32TXIR="00110010" else '0';

--contador de 12 bits transmissão, conta até 900 x 10us
UT2: CONTBCD_C port map(CLK => clk100k, CLR => clr12bits, UP => '1', EN => '1', ENOUT => EOTX12(0), Q => conttimeTXIR(3 downto 0));
UT3: CONTBCD_C port map(CLK => clk100k, CLR => clr12bits, UP => '1', EN => EOTX12(0), ENOUT => EOTX12(1), Q => conttimeTXIR(7 downto 4));
UT4: CONTBCD_C port map(CLK => clk100k, CLR => clr12bits, UP => '1', EN => EOTX12(1), ENOUT => EOTX12(2), Q => conttimeTXIR(11 downto 8));
Q900 <= '0' when conttimeTXIR(11 downto 8)="1001" else '1';
Q450 <= '0' when conttimeTXIR(11 downto 4)="01000101" else '1';
Q55 <= '0' when conttimeTXIR(7 downto 0)="01010101" else '1';
Q165 <= '0' when conttimeTXIR="000101100101" else '1';

--shift register
proxshift32 <= codigo32 when loadshift='1' else '0'&atualshift32(31 downto 1);
Q0 <= atualshift32(0);

process (clkshift)
begin
	if (clkshift'event and clkshift='1') then
		atualshift32 <=proxshift32;
	end if;
end process;


--gera 37915Hz
process(CLK27MHz)
begin
	if(CLK27MHz'event and CLK27MHz = '1') then
		if (cont37915 = "000000000000000000000000") then cont37915 <= "000000000000000101100011";
		else cont37915 <= cont37915-"000000000000000000000001";
		end if;
	end if;
end process;
process(cont37915(8))
begin
	if(cont37915(8)'event and cont37915(8) = '1') then
		clk37915 <= not clk37915;
	end if;
end process;

proxTX <= "000"&BUT(0) when atualTX="0000" else
			 "00"&(not BUT(0))&'1' when atualTX="0001" else
			 "001"&Q900 when atualTX="0011" else
			 "0110" when atualTX="0010" else
			 "011"&(not Q450) when atualTX="0110" else
			 "1111" when atualTX="0111" else
			 "111"&Q55 when atualTX="1111" else
			 "1010" when atualTX="1110" else
			 "1010" when (atualTX="1010" and Q0='1' and Q165='0') else
			 "1010" when (atualTX="1010" and Q0='0' and Q55='0') else
			 "1011" when atualTX="1010" else
			 contbitsigual32&(not contbitsigual32)&(not contbitsigual32)&'1' when atualTX="1011" else
			 "100"&Q55 when atualTX="1001" else
			 "0000";

proxCLRCONTBITS <= '1' when proxTX="0110" else '0';
proxCLKCONTBITS <= '1' when proxTX="1010" else '0';
proxCLR12BITS <= '1' when proxTX="0001" else
					  '1' when proxTX="0010" else
					  '1' when proxTX="0111" else
					  '1' when proxTX="1110" else
					  '1' when proxTX="1011" else '0';
proxLOADSHIFT <= '1' when proxTX="0001" else
					  '1' when proxTX="0011" else '0';
proxCLKSHIFT <= '1' when proxTX="0011" else
					 '1' when proxTX="1010" else '0';
proxOUTIR <= '1' when proxTX="0011" else
				 '1' when proxTX="0111" else
				 '1' when proxTX="1111" else
				 '1' when proxTX="1011" else
				 '1' when proxTX="1001" else '0';











UDISP: display port map(num7=>num7, num6=>num6, num5=>num5, num4=>num4, num3=>num3, num2=>num2,
                        num1=>num1, num0=>num0, clk=>clkdisp, cs=>cs, dout=>din); 

CLR_cont_S <= atual_S(1) and atual_S(0);
prox_S <= '0'&(not S_IR) when atual_S="00" else
			 "11" when atual_S="01" else
			 "10" when atual_S="11" else
			 (not S_IR & '0');
			 
proxshift <= atualshift when ENshift = '0' else
				 SIshift & atualshift (31 downto 1);
				 
process (S_IR)
begin
	if (S_IR'event and S_IR='0') then
		atualshift <= proxshift;
	end if;
end process;

process (Q8ms)
begin
	if (Q8ms'event and Q8ms='1') then
		codigo32 <= atualshift;
	end if;
end process;

process (CLK100k)
begin
	if (CLK100k'event and CLK100k='1') then
		atual_S <= prox_S;
		num7 <= proxnum7;
		atualTX <= proxTX;
		clrcontbits <= proxCLRCONTBITS;
		clkcontbits <= proxCLKCONTBITS;
		clr12bits <= proxCLR12BITS;
		loadshift <= proxLOADSHIFT;
		clkSHIFT <= proxCLKSHIFT;
		outIR <= proxOUTIR;
	end if;
end process;

UC0: CONTBCD_C port map(CLK => CLK100k, CLR => CLR_cont_S, UP => '1', EN => (S_IR and not Q8ms), ENOUT => EO(0), Q => num0);
UC1: CONTBCD_C port map(CLK => CLK100k, CLR => CLR_cont_S, UP => '1', EN => EO(0), ENOUT => EO(1), Q => num1);
UC2: CONTBCD_C port map(CLK => CLK100k, CLR => CLR_cont_S, UP => '1', EN => EO(1), ENOUT => EO(2), Q => num2);

Q1ms <= num2(0);
Q4ms <= num2(2);
Q8ms <= num2(3);

ENshift <= not Q8ms and not Q4ms;
SIshift <= Q1ms;

proxnum7 <= "0000" when codigo32(31 downto 24)="11101001" else -- 0 = E9
		  "0001" when codigo32(31 downto 24)="11110011" else -- 1 = F3
		  "0010" when codigo32(31 downto 24)="11100111" else -- 2 = E7
		  "0011" when codigo32(31 downto 24)="10100001" else -- 3 = A1
		  "0100" when codigo32(31 downto 24)="11110111" else -- 4 = F7
		  "0101" when codigo32(31 downto 24)="11100011" else -- 5 = E3
		  "0110" when codigo32(31 downto 24)="10100101" else -- 6 = A5
		  "0111" when codigo32(31 downto 24)="10111101" else -- 7 = BD
		  "1000" when codigo32(31 downto 24)="10101101" else -- 8 = AD
		  "1001" when codigo32(31 downto 24)="10110101" else -- 9 = B5
		  num7;

process(CLK27MHz)
begin
	if(CLK27MHz'event and CLK27MHz = '1') then
		if (cont100k = "000000000000000000000000") then cont100k <= "000000000000000100001101";
		else cont100k <= cont100k-"000000000000000000000001";
		end if;
		contaux <= contaux + "000000000000000000000001";
	end if;
end process;

CLK100k <= cont100k(8);
CLK25k <= contaux(9);
clk621ms <= contaux(23); -- aprox. 1,6 Hz
clkdisp <= contaux(5); -- 421875 Hz
GPIO(0) <= clkdisp;
GPIO(1) <= cs;
GPIO(2) <= din;
S_IR <= GPIO(4);
LEDS <= atualTX;
num6 <= atualTX;
num5 <= proxTX;
GPIO(5) <= CLK37915 and OUTIR;


end comportamento;





library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity CONTBCD_C is
	port (CLK, CLR, UP, EN: in std_logic;
			ENOUT: out std_logic;
			Q: out std_logic_vector(3 downto 0)
			);
end CONTBCD_C;

architecture comportamento of CONTBCD_C is

signal cont, proxcont: std_logic_vector (3 downto 0);
begin
	Q <= cont;
--	proxcont <= cont + "0001" when (EN+UP)="11" else
--					cont - "0001" when (EN+UP)="10" else
	proxcont <=	"0000" when (cont = "1001" and EN = '1' and UP = '1') else
					"1001" when (cont = "0000" and EN = '1' and UP = '0') else
					cont+(not UP & not UP & not UP & '1') when EN='1' else
					cont;
	ENOUT <= '1' when (EN = '1' and UP = '1' and cont = "1001") else
				'1' when (EN = '1' and UP = '0' and cont = "0000") else
				'0';
	process (CLK, CLR)
	begin
		if (CLR = '1') then
			cont <= "0000";
		elsif (CLK'event and CLK = '1') then
			cont <= proxcont;
		end if;
	end process;
end comportamento;







library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity display is		--Implementao do componente Display
port( NUM7, NUM6, NUM5, NUM4, NUM3, NUM2, NUM1, NUM0: in std_logic_vector(3 downto 0);
		CLK: in std_logic; 
		CS, Dout: out std_logic);
end display;

architecture comportamento of display is

--Declarao e inicializao das variveis---------------------
signal EN: std_logic_vector(8 downto 0):="000000000"; --ontador de 9 bits
signal palavra, proxpalavra: std_logic_vector(15 downto 0):="0000000000000000"; --palavra na fila de bits e proxpalavra
signal proxnum, proxdisplay: std_logic_vector(3 downto 0); --sinais de controle de algarismo e posicao do display
signal Dis: std_logic_vector(2 downto 0); --Sinal da posicao da posicao a partir do contador de 9 bits
signal proxfig,Fig: std_logic_vector(1 downto 0):="00"; --Sinal que pega o bit mais significativo e o sexto bit, para a logica de configuraao da palavra
signal configur: std_logic:='0';
---------------------------------------------------------------

begin

		Dis<=EN(7 downto 5); --Posicao do display baseada no contador de 9 bits
		
		proxnum <= NUM1 when Dis="001" else 
					  NUM2 when Dis="010" else
					  NUM3 when Dis="011" else
					  NUM4 when Dis="100" else
					  NUM5 when Dis="101" else
					  NUM6 when Dis="110" else
					  NUM7 when Dis="111" else
					  NUM0;

		proxdisplay <= 	"0010" when Dis="001" else 
								"0011" when Dis="010" else
								"0100" when Dis="011" else
								"0101" when Dis="100" else
								"0110" when Dis="101" else
								"0111" when Dis="110" else
								"1000" when Dis="111" else
								"0001";
	
		proxpalavra<=	"0000110000000001" when (configur = '0' and Dis = "000") else -- modo normal
							"0000101111111111" when (configur = '0' and Dis = "001") else -- scan todos
							"0000101000001111" when (configur = '0' and Dis = "010") else -- intensidade
							"0000100111111111" when (configur = '0' and Dis = "011") else -- BCD
							--"1111111111111111" when (configur = '0' and Dis = "100") else
							--"0000001100000111";
							--"0000001101010101";
							--"0000"&"0001"&"01010111";
							"0000"&proxdisplay&"0000"&proxnum;
						
		 
	process(CLK) --Processo que atualiza os valores do componente
	begin
			if(CLK'event and CLK='0') then -- As configuraes de proximo estado podem ser feitas a qualquer momento
				EN<=EN+"000000001";
				configur <= EN(8) or configur;

				if(EN(4) = '0') then --Coloca a proxpalavra na fila de bits no "final" do CS='1' 
					palavra<=proxpalavra;
				else
					palavra<=palavra(14 downto 0)&'0'; --Coloca o proximo bit da fila no bus a cada clock quando CS='0'					
--					palavra<='0'&palavra(15 downto 1); --Coloca o proximo bit da fila no bus a cada clock quando CS='0'
				end if;
			end if;
	end process;


	Dout<=palavra(15); --Bus: sinal sendo passado para o display
--	Dout<=palavra(0); --Bus: sinal sendo passado para o display
	CS <= not EN(4);  --Sinal CS que controla a habilitao da escrita no display
end comportamento;