Release 14.7 - xst P.20131013 (nt64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to xst/projnav.tmp Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.12 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.12 secs --> Reading design: textovhdl.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Parsing 3) HDL Elaboration 4) HDL Synthesis 4.1) HDL Synthesis Report 5) Advanced HDL Synthesis 5.1) Advanced HDL Synthesis Report 6) Low Level Synthesis 7) Partition Report 8) Design Summary 8.1) Primitive and Black Box Usage 8.2) Device utilization summary 8.3) Partition Resource Summary 8.4) Timing Report 8.4.1) Clock Information 8.4.2) Asynchronous Control Signals Information 8.4.3) Timing Summary 8.4.4) Timing Details 8.4.5) Cross Clock Domains Report ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "textovhdl.prj" Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "textovhdl" Output Format : NGC Target Device : xc6slx16-2-csg324 ---- Source Options Top Module Name : textovhdl Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No FSM Style : LUT RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes Shift Register Extraction : YES ROM Style : Auto Resource Sharing : YES Asynchronous To Synchronous : NO Shift Register Minimum Size : 2 Use DSP Block : Auto Automatic Register Balancing : No ---- Target Options LUT Combining : Auto Reduce Control Sets : Auto Add IO Buffers : YES Global Maximum Fanout : 100000 Add Generic Clock Buffer(BUFG) : 16 Register Duplication : YES Optimize Instantiated Primitives : NO Use Clock Enable : Auto Use Synchronous Set : Auto Use Synchronous Reset : Auto Pack IO Registers into IOBs : Auto Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 Power Reduction : NO Keep Hierarchy : No Netlist Hierarchy : As_Optimized RTL Output : Yes Global Optimization : AllClockNets Read Cores : YES Write Timing Constraints : NO Cross Clock Analysis : NO Hierarchy Separator : / Bus Delimiter : <> Case Specifier : Maintain Slice Utilization Ratio : 100 BRAM Utilization Ratio : 100 DSP48 Utilization Ratio : 100 Auto BRAM Packing : NO Slice Utilization Ratio Delta : 5 ========================================================================= ========================================================================= * HDL Parsing * ========================================================================= Parsing VHDL file "C:\Users\Gabriel\Xilinx\Aula20220603\textovhdl.vhd" into library work Parsing entity . Parsing architecture of entity . WARNING:HDLCompiler:946 - "C:\Users\Gabriel\Xilinx\Aula20220603\textovhdl.vhd" Line 183: Actual for formal port en is neither a static name nor a globally static expression Parsing entity . Parsing architecture of entity . Parsing entity . Parsing architecture of entity . ========================================================================= * HDL Elaboration * ========================================================================= Elaborating entity (architecture ) from library . Elaborating entity (architecture ) from library . Elaborating entity (architecture ) from library . WARNING:HDLCompiler:1127 - "C:\Users\Gabriel\Xilinx\Aula20220603\textovhdl.vhd" Line 217: Assignment to clk25k ignored, since the identifier is never used WARNING:HDLCompiler:1127 - "C:\Users\Gabriel\Xilinx\Aula20220603\textovhdl.vhd" Line 218: Assignment to clk621ms ignored, since the identifier is never used WARNING:HDLCompiler:634 - "C:\Users\Gabriel\Xilinx\Aula20220603\textovhdl.vhd" Line 20: Net does not have a driver. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "C:\Users\Gabriel\Xilinx\Aula20220603\textovhdl.vhd". WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. INFO:Xst:3210 - "C:\Users\Gabriel\Xilinx\Aula20220603\textovhdl.vhd" line 60: Output port of the instance is unconnected or connected to loadless signal. INFO:Xst:3210 - "C:\Users\Gabriel\Xilinx\Aula20220603\textovhdl.vhd" line 66: Output port of the instance is unconnected or connected to loadless signal. INFO:Xst:3210 - "C:\Users\Gabriel\Xilinx\Aula20220603\textovhdl.vhd" line 185: Output port of the instance is unconnected or connected to loadless signal. Always blocking tristate driving signal > is removed. Always blocking tristate driving signal > is removed. Always blocking tristate driving signal > is removed. Always blocking tristate driving signal > is removed. Always blocking tristate driving signal > is removed. Always blocking tristate driving signal > is removed. Always blocking tristate driving signal > is removed. Always blocking tristate driving signal > is removed. WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. Found 24-bit register for signal . Found 1-bit register for signal . Found 32-bit register for signal . Found 32-bit register for signal . Found 2-bit register for signal . Found 4-bit register for signal . Found 4-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 24-bit register for signal . Found 24-bit register for signal . Found 32-bit register for signal . Found 24-bit adder for signal created at line 212. Found 24-bit subtractor for signal > created at line 89. Found 24-bit subtractor for signal > created at line 210. Found 2-bit 4-to-1 multiplexer for signal created at line 23. HDL ADVISOR - Describing an operational reset or an explicit power-up state for register would allow inference of a finite state machine and as consequence better performance and smaller area. HDL ADVISOR - Describing an operational reset or an explicit power-up state for register would allow inference of a finite state machine and as consequence better performance and smaller area. Summary: inferred 3 Adder/Subtractor(s). inferred 185 D-type flip-flop(s). inferred 15 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is "C:\Users\Gabriel\Xilinx\Aula20220603\textovhdl.vhd". Found 4-bit register for signal . Found 4-bit adder for signal created at line 257. Summary: inferred 1 Adder/Subtractor(s). inferred 4 D-type flip-flop(s). inferred 3 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is "C:\Users\Gabriel\Xilinx\Aula20220603\textovhdl.vhd". Found 1-bit register for signal . Found 16-bit register for signal . Found 9-bit register for signal . Found 9-bit adder for signal created at line 336. Found 8x4-bit Read Only RAM for signal Found 4-bit 8-to-1 multiplexer for signal created at line 294. Summary: inferred 1 RAM(s). inferred 1 Adder/Subtractor(s). inferred 26 D-type flip-flop(s). inferred 6 Multiplexer(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # RAMs : 1 8x4-bit single-port Read Only RAM : 1 # Adders/Subtractors : 12 24-bit adder : 1 24-bit subtractor : 2 4-bit adder : 8 9-bit adder : 1 # Registers : 27 1-bit register : 8 16-bit register : 1 2-bit register : 1 24-bit register : 3 32-bit register : 3 4-bit register : 10 9-bit register : 1 # Multiplexers : 45 1-bit 2-to-1 multiplexer : 10 16-bit 2-to-1 multiplexer : 5 2-bit 4-to-1 multiplexer : 1 24-bit 2-to-1 multiplexer : 1 32-bit 2-to-1 multiplexer : 1 4-bit 2-to-1 multiplexer : 26 4-bit 8-to-1 multiplexer : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Synthesizing (advanced) Unit . The following registers are absorbed into counter : 1 register on signal . INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. ----------------------------------------------------------------------- | ram_type | Distributed | | ----------------------------------------------------------------------- | Port A | | aspect ratio | 8-word x 4-bit | | | weA | connected to signal | high | | addrA | connected to signal > | | | diA | connected to signal | | | doA | connected to signal | | ----------------------------------------------------------------------- Unit synthesized (advanced). Synthesizing (advanced) Unit . The following registers are absorbed into counter : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . The following registers are absorbed into counter : 1 register on signal . Unit synthesized (advanced). ========================================================================= Advanced HDL Synthesis Report Macro Statistics # RAMs : 1 8x4-bit single-port distributed Read Only RAM : 1 # Adders/Subtractors : 8 4-bit adder : 8 # Counters : 4 24-bit down counter : 2 24-bit up counter : 1 9-bit up counter : 1 # Registers : 162 Flip-Flops : 162 # Multiplexers : 44 1-bit 2-to-1 multiplexer : 10 16-bit 2-to-1 multiplexer : 5 2-bit 4-to-1 multiplexer : 1 32-bit 2-to-1 multiplexer : 1 4-bit 2-to-1 multiplexer : 26 4-bit 8-to-1 multiplexer : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . Optimizing unit ... Optimizing unit ... Optimizing unit ... Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block textovhdl, actual ratio is 4. Final Macro Processing ... ========================================================================= Final Register Report Macro Statistics # Registers : 225 Flip-Flops : 225 ========================================================================= ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Design Summary * ========================================================================= Top Level Output File Name : textovhdl.ngc Primitive and Black Box Usage: ------------------------------ # BELS : 358 # GND : 1 # INV : 58 # LUT1 : 15 # LUT2 : 10 # LUT3 : 45 # LUT4 : 19 # LUT5 : 56 # LUT6 : 31 # MUXCY : 59 # VCC : 1 # XORCY : 63 # FlipFlops/Latches : 225 # FD : 115 # FD_1 : 17 # FDC : 8 # FDCE : 24 # FDE : 4 # FDE_1 : 32 # FDR : 20 # FDS : 5 # Clock Buffers : 6 # BUFG : 5 # BUFGP : 1 # IO Buffers : 10 # IBUF : 2 # OBUF : 8 Device utilization summary: --------------------------- Selected Device : 6slx16csg324-2 Slice Logic Utilization: Number of Slice Registers: 225 out of 18224 1% Number of Slice LUTs: 234 out of 9112 2% Number used as Logic: 234 out of 9112 2% Slice Logic Distribution: Number of LUT Flip Flop pairs used: 294 Number with an unused Flip Flop: 69 out of 294 23% Number with an unused LUT: 60 out of 294 20% Number of fully used LUT-FF pairs: 165 out of 294 56% Number of unique control sets: 18 IO Utilization: Number of IOs: 21 Number of bonded IOBs: 11 out of 232 4% Specific Feature Utilization: Number of BUFG/BUFGCTRLs: 6 out of 16 37% --------------------------- Partition Resource Summary: --------------------------- No Partitions were found in this design. --------------------------- ========================================================================= Timing Report NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ cont100k_8 | BUFG | 40 | cont37915_8 | NONE(clk37915) | 1 | clkshift | BUFG | 32 | GPIO<4> | IBUF+BUFG | 32 | UC2/cont_3 | BUFG | 32 | CLK27MHz | BUFGP | 54 | clkcontbits | NONE(UT1/cont_3) | 8 | contaux_5 | BUFG | 26 | -----------------------------------+------------------------+-------+ INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. Asynchronous Control Signals Information: ---------------------------------------- No asynchronous control signals found in this design Timing Summary: --------------- Speed Grade: -2 Minimum period: 5.302ns (Maximum Frequency: 188.608MHz) Minimum input arrival time before clock: 6.062ns Maximum output required time after clock: 5.607ns Maximum combinational path delay: No path found Timing Details: --------------- All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default period analysis for Clock 'cont100k_8' Clock period: 5.302ns (frequency: 188.608MHz) Total number of paths / destination ports: 720 / 80 ------------------------------------------------------------------------- Delay: 5.302ns (Levels of Logic = 4) Source: UT3/cont_3 (FF) Destination: atualTX_0 (FF) Source Clock: cont100k_8 rising Destination Clock: cont100k_8 rising Data Path: UT3/cont_3 to atualTX_0 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDCE:C->Q 5 0.525 1.117 UT3/cont_3 (UT3/cont_3) LUT4:I0->O 2 0.254 0.726 proxTX<0>421 (proxTX<0>41) LUT5:I4->O 2 0.254 0.834 conttimeTXIR[7]_GND_5_o_equal_6_o<7>1 (conttimeTXIR[7]_GND_5_o_equal_6_o) LUT6:I4->O 7 0.250 1.018 proxTX<0>4 (proxTX<0>4) LUT6:I4->O 1 0.250 0.000 Mmux_proxCLR12BITS11 (proxCLR12BITS) FD:D 0.074 clr12bits ---------------------------------------- Total 5.302ns (1.607ns logic, 3.695ns route) (30.3% logic, 69.7% route) ========================================================================= Timing constraint: Default period analysis for Clock 'cont37915_8' Clock period: 1.709ns (frequency: 585.138MHz) Total number of paths / destination ports: 1 / 1 ------------------------------------------------------------------------- Delay: 1.709ns (Levels of Logic = 0) Source: clk37915 (FF) Destination: clk37915 (FF) Source Clock: cont37915_8 rising Destination Clock: cont37915_8 rising Data Path: clk37915 to clk37915 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDR:C->Q 2 0.525 0.725 clk37915 (clk37915) FDR:R 0.459 clk37915 ---------------------------------------- Total 1.709ns (0.984ns logic, 0.725ns route) (57.6% logic, 42.4% route) ========================================================================= Timing constraint: Default period analysis for Clock 'clkshift' Clock period: 1.639ns (frequency: 610.128MHz) Total number of paths / destination ports: 31 / 31 ------------------------------------------------------------------------- Delay: 1.639ns (Levels of Logic = 1) Source: atualshift32_1 (FF) Destination: atualshift32_0 (FF) Source Clock: clkshift rising Destination Clock: clkshift rising Data Path: atualshift32_1 to atualshift32_0 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FD:C->Q 1 0.525 0.790 atualshift32_1 (atualshift32_1) LUT3:I1->O 1 0.250 0.000 Mmux_proxshift3211 (proxshift32<0>) FD:D 0.074 atualshift32_0 ---------------------------------------- Total 1.639ns (0.849ns logic, 0.790ns route) (51.8% logic, 48.2% route) ========================================================================= Timing constraint: Default period analysis for Clock 'GPIO<4>' Clock period: 1.324ns (frequency: 755.287MHz) Total number of paths / destination ports: 31 / 31 ------------------------------------------------------------------------- Delay: 1.324ns (Levels of Logic = 0) Source: atualshift_1 (FF) Destination: atualshift_0 (FF) Source Clock: GPIO<4> falling Destination Clock: GPIO<4> falling Data Path: atualshift_1 to atualshift_0 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDE_1:C->Q 2 0.525 0.725 atualshift_1 (atualshift_1) FDE_1:D 0.074 atualshift_0 ---------------------------------------- Total 1.324ns (0.599ns logic, 0.725ns route) (45.2% logic, 54.8% route) ========================================================================= Timing constraint: Default period analysis for Clock 'CLK27MHz' Clock period: 5.010ns (frequency: 199.601MHz) Total number of paths / destination ports: 1773 / 78 ------------------------------------------------------------------------- Delay: 5.010ns (Levels of Logic = 2) Source: cont37915_13 (FF) Destination: cont37915_1 (FF) Source Clock: CLK27MHz rising Destination Clock: CLK27MHz rising Data Path: cont37915_13 to cont37915_1 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDR:C->Q 2 0.525 1.181 cont37915_13 (cont37915_13) LUT6:I0->O 1 0.254 0.958 cont37915[23]_GND_5_o_equal_10_o<23>1 (cont37915[23]_GND_5_o_equal_10_o<23>) LUT4:I0->O 24 0.254 1.379 cont37915[23]_GND_5_o_equal_10_o<23>5 (cont37915[23]_GND_5_o_equal_10_o) FDS:S 0.459 cont37915_1 ---------------------------------------- Total 5.010ns (1.492ns logic, 3.518ns route) (29.8% logic, 70.2% route) ========================================================================= Timing constraint: Default period analysis for Clock 'clkcontbits' Clock period: 3.273ns (frequency: 305.530MHz) Total number of paths / destination ports: 48 / 12 ------------------------------------------------------------------------- Delay: 3.273ns (Levels of Logic = 2) Source: UT0/cont_0 (FF) Destination: UT1/cont_3 (FF) Source Clock: clkcontbits rising Destination Clock: clkcontbits rising Data Path: UT0/cont_0 to UT1/cont_3 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDC:C->Q 7 0.525 1.186 UT0/cont_0 (UT0/cont_0) LUT4:I0->O 6 0.254 0.984 UT0/Mmux_ENOUT11 (EOTX8<0>) LUT5:I3->O 1 0.250 0.000 UT1/Mmux_proxcont41 (UT1/proxcont<3>) FDCE:D 0.074 UT1/cont_3 ---------------------------------------- Total 3.273ns (1.103ns logic, 2.170ns route) (33.7% logic, 66.3% route) ========================================================================= Timing constraint: Default period analysis for Clock 'contaux_5' Clock period: 3.637ns (frequency: 274.952MHz) Total number of paths / destination ports: 127 / 26 ------------------------------------------------------------------------- Delay: 3.637ns (Levels of Logic = 2) Source: UDISP/EN_5 (FF) Destination: UDISP/palavra_3 (FF) Source Clock: contaux_5 falling Destination Clock: contaux_5 falling Data Path: UDISP/EN_5 to UDISP/palavra_3 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FD:C->Q 17 0.525 1.639 UDISP/EN_5 (UDISP/EN_5) LUT5:I0->O 1 0.254 0.910 UDISP/Mmux_palavra[14]_proxpalavra[15]_mux_38_OUT92 (UDISP/Mmux_palavra[14]_proxpalavra[15]_mux_38_OUT91) LUT5:I2->O 1 0.235 0.000 UDISP/Mmux_palavra[14]_proxpalavra[15]_mux_38_OUT93 (UDISP/palavra[14]_proxpalavra[15]_mux_38_OUT<2>) FD_1:D 0.074 UDISP/palavra_2 ---------------------------------------- Total 3.637ns (1.088ns logic, 2.549ns route) (29.9% logic, 70.1% route) ========================================================================= Timing constraint: Default OFFSET IN BEFORE for Clock 'cont100k_8' Total number of paths / destination ports: 33 / 28 ------------------------------------------------------------------------- Offset: 5.281ns (Levels of Logic = 4) Source: GPIO<4> (PAD) Destination: UC2/cont_3 (FF) Destination Clock: cont100k_8 rising Data Path: GPIO<4> to UC2/cont_3 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 6 1.328 1.331 GPIO_4_IBUF (GPIO_4_IBUF) LUT6:I0->O 7 0.254 0.910 UC0/Mmux_ENOUT11 (EO<0>) LUT5:I4->O 6 0.254 0.876 UC1/Mmux_ENOUT11 (EO<1>) LUT5:I4->O 1 0.254 0.000 UC2/Mmux_proxcont21 (UC2/proxcont<1>) FDCE:D 0.074 UC2/cont_1 ---------------------------------------- Total 5.281ns (2.164ns logic, 3.117ns route) (41.0% logic, 59.0% route) ========================================================================= Timing constraint: Default OFFSET IN BEFORE for Clock 'contaux_5' Total number of paths / destination ports: 2 / 2 ------------------------------------------------------------------------- Offset: 6.062ns (Levels of Logic = 5) Source: BUT<0> (PAD) Destination: UDISP/palavra_0 (FF) Destination Clock: contaux_5 falling Data Path: BUT<0> to UDISP/palavra_0 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 4 1.328 0.912 BUT_0_IBUF (BUT_0_IBUF) LUT4:I2->O 7 0.250 1.138 proxTX<0>9 (proxTX<0>9) LUT4:I1->O 2 0.235 0.954 proxTX<0>10 (proxTX<0>) LUT5:I2->O 1 0.235 0.682 UDISP/Mmux_palavra[14]_proxpalavra[15]_mux_38_OUT12 (UDISP/Mmux_palavra[14]_proxpalavra[15]_mux_38_OUT11) LUT4:I3->O 1 0.254 0.000 UDISP/Mmux_palavra[14]_proxpalavra[15]_mux_38_OUT13 (UDISP/palavra[14]_proxpalavra[15]_mux_38_OUT<0>) FD_1:D 0.074 UDISP/palavra_0 ---------------------------------------- Total 6.062ns (2.376ns logic, 3.686ns route) (39.2% logic, 60.8% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'cont100k_8' Total number of paths / destination ports: 5 / 5 ------------------------------------------------------------------------- Offset: 5.054ns (Levels of Logic = 2) Source: outir (FF) Destination: GPIO<5> (PAD) Source Clock: cont100k_8 rising Data Path: outir to GPIO<5> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FD:C->Q 1 0.525 0.682 outir (outir) LUT2:I1->O 1 0.254 0.681 GPIO<5>1 (GPIO_5_OBUF) OBUF:I->O 2.912 GPIO_5_OBUF (GPIO<5>) ---------------------------------------- Total 5.054ns (3.691ns logic, 1.363ns route) (73.0% logic, 27.0% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'cont37915_8' Total number of paths / destination ports: 1 / 1 ------------------------------------------------------------------------- Offset: 5.202ns (Levels of Logic = 2) Source: clk37915 (FF) Destination: GPIO<5> (PAD) Source Clock: cont37915_8 rising Data Path: clk37915 to GPIO<5> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDR:C->Q 2 0.525 0.834 clk37915 (clk37915) LUT2:I0->O 1 0.250 0.681 GPIO<5>1 (GPIO_5_OBUF) OBUF:I->O 2.912 GPIO_5_OBUF (GPIO<5>) ---------------------------------------- Total 5.202ns (3.687ns logic, 1.515ns route) (70.9% logic, 29.1% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'contaux_5' Total number of paths / destination ports: 2 / 2 ------------------------------------------------------------------------- Offset: 5.607ns (Levels of Logic = 2) Source: UDISP/EN_4 (FF) Destination: GPIO<1> (PAD) Source Clock: contaux_5 falling Data Path: UDISP/EN_4 to GPIO<1> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FD:C->Q 18 0.525 1.234 UDISP/EN_4 (UDISP/EN_4) INV:I->O 1 0.255 0.681 UDISP/CS1_INV_0 (GPIO_1_OBUF) OBUF:I->O 2.912 GPIO_1_OBUF (GPIO<1>) ---------------------------------------- Total 5.607ns (3.692ns logic, 1.915ns route) (65.8% logic, 34.2% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK27MHz' Total number of paths / destination ports: 1 / 1 ------------------------------------------------------------------------- Offset: 4.162ns (Levels of Logic = 1) Source: contaux_5 (FF) Destination: GPIO<0> (PAD) Source Clock: CLK27MHz rising Data Path: contaux_5 to GPIO<0> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FD:C->Q 2 0.525 0.725 contaux_5 (contaux_5) OBUF:I->O 2.912 GPIO_0_OBUF (GPIO<0>) ---------------------------------------- Total 4.162ns (3.437ns logic, 0.725ns route) (82.6% logic, 17.4% route) ========================================================================= Cross Clock Domains Report: -------------------------- Clock to Setup on destination clock CLK27MHz ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ CLK27MHz | 5.010| | | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock GPIO<4> ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ GPIO<4> | | | 1.324| | cont100k_8 | | | 3.648| | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock UC2/cont_3 ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ GPIO<4> | | 1.324| | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock clkcontbits ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clkcontbits | 3.273| | | | cont100k_8 | 1.927| | | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock clkshift ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ UC2/cont_3 | 1.729| | | | clkshift | 1.639| | | | cont100k_8 | 2.582| | | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock cont100k_8 ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ UC2/cont_3 | 4.126| | | | clkcontbits | 7.052| | | | clkshift | 3.154| | | | cont100k_8 | 5.302| | | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock cont37915_8 ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ cont37915_8 | 1.709| | | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock contaux_5 ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clkcontbits | | | 7.157| | clkshift | | | 5.279| | cont100k_8 | | | 7.427| | contaux_5 | | | 3.637| | ---------------+---------+---------+---------+---------+ ========================================================================= Total REAL time to Xst completion: 8.00 secs Total CPU time to Xst completion: 8.09 secs --> Total memory usage is 260168 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 26 ( 0 filtered) Number of infos : 5 ( 0 filtered)