Release 14.7 par P.20131013 (nt64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. GABRIEL-E5400:: Fri Jun 10 13:05:17 2022 par -w -intstyle ise -ol high -mt off textovhdl_map.ncd textovhdl.ncd textovhdl.pcf Constraints file: textovhdl.pcf. Loading device for application Rf_Device from file '6slx16.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\. "textovhdl" is an NCD, version 3.2, device xc6slx16, package csg324, speed -2 Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". Device speed data version: "PRODUCTION 1.23 2013-10-13". Device Utilization Summary: Slice Logic Utilization: Number of Slice Registers: 225 out of 18,224 1% Number used as Flip Flops: 225 Number used as Latches: 0 Number used as Latch-thrus: 0 Number used as AND/OR logics: 0 Number of Slice LUTs: 218 out of 9,112 2% Number used as logic: 192 out of 9,112 2% Number using O6 output only: 94 Number using O5 output only: 13 Number using O5 and O6: 85 Number used as ROM: 0 Number used as Memory: 0 out of 2,176 0% Number used exclusively as route-thrus: 26 Number with same-slice register load: 24 Number with same-slice carry load: 2 Number with other load: 0 Slice Logic Distribution: Number of occupied Slices: 70 out of 2,278 3% Number of MUXCYs used: 68 out of 4,556 1% Number of LUT Flip Flop pairs used: 235 Number with an unused Flip Flop: 62 out of 235 26% Number with an unused LUT: 17 out of 235 7% Number of fully used LUT-FF pairs: 156 out of 235 66% Number of slice register sites lost to control set restrictions: 0 out of 18,224 0% A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice. A control set is a unique combination of clock, reset, set, and enable signals for a registered element. The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. IO Utilization: Number of bonded IOBs: 21 out of 232 9% Number of LOCed IOBs: 21 out of 21 100% Specific Feature Utilization: Number of RAMB16BWERs: 0 out of 32 0% Number of RAMB8BWERs: 0 out of 64 0% Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0% Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0% Number of BUFG/BUFGMUXs: 6 out of 16 37% Number used as BUFGs: 6 Number used as BUFGMUX: 0 Number of DCM/DCM_CLKGENs: 0 out of 4 0% Number of ILOGIC2/ISERDES2s: 0 out of 248 0% Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 248 0% Number of OLOGIC2/OSERDES2s: 0 out of 248 0% Number of BSCANs: 0 out of 4 0% Number of BUFHs: 0 out of 128 0% Number of BUFPLLs: 0 out of 8 0% Number of BUFPLL_MCBs: 0 out of 4 0% Number of DSP48A1s: 0 out of 32 0% Number of ICAPs: 0 out of 1 0% Number of MCBs: 0 out of 2 0% Number of PCILOGICSEs: 0 out of 2 0% Number of PLL_ADVs: 0 out of 2 0% Number of PMVs: 0 out of 1 0% Number of STARTUPs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0% Overall effort level (-ol): High Router effort level (-rl): High Starting initial Timing Analysis. REAL time: 4 secs Finished initial Timing Analysis. REAL time: 4 secs WARNING:Par:288 - The signal BUT<1>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal BUT<2>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal BUT<3>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal DIPSW<0>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal DIPSW<1>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal DIPSW<2>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal DIPSW<3>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal GPIO<3>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal GPIO<6>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal GPIO<7>_IBUF has no load. PAR will not attempt to route this signal. Starting Router Phase 1 : 973 unrouted; REAL time: 4 secs Phase 2 : 819 unrouted; REAL time: 4 secs Phase 3 : 212 unrouted; REAL time: 5 secs Phase 4 : 218 unrouted; (Par is working to improve performance) REAL time: 6 secs Updating file: textovhdl.ncd with current fully routed design. Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs Total REAL time to Router completion: 7 secs Total CPU time to Router completion: 7 secs Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- Generating "PAR" statistics. INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode. Timing Score: 33 (Setup: 33, Hold: 0) Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation. ---------------------------------------------------------------------------------------------------------- Constraint | Check | Worst Case | Best Case | Timing | Timing | | Slack | Achievable | Errors | Score ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net con | SETUP | N/A| 4.182ns| N/A| 0 t100k_8_BUFG | HOLD | 0.412ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net clk | SETUP | N/A| 2.853ns| N/A| 0 contbits | HOLD | 0.452ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net clk | SETUP | N/A| 1.924ns| N/A| 0 shift_BUFG | HOLD | 0.405ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net con | SETUP | N/A| 4.054ns| N/A| 0 taux_5_BUFG | HOLD | 0.424ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net CLK | SETUP | N/A| 3.584ns| N/A| 0 27MHz_BUFGP | HOLD | 0.463ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net con | SETUP | N/A| 1.769ns| N/A| 33 t37915<8> | HOLD | 0.589ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net GPI | SETUP | N/A| 1.706ns| N/A| 0 O_4_IBUF_BUFG | HOLD | 0.496ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- 1 constraint not met. INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI. Generating Pad Report. All signals are completely routed. WARNING:Par:283 - There are 10 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. Total REAL time to PAR completion: 8 secs Total CPU time to PAR completion: 7 secs Peak Memory Usage: 312 MB Placer: Placement generated during map. Routing: Completed - No errors found. Number of error messages: 0 Number of warning messages: 12 Number of info messages: 2 Writing design to file textovhdl.ncd PAR done!