250 lines
12 KiB
Plaintext
250 lines
12 KiB
Plaintext
Release 14.7 Map P.20131013 (nt64)
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Xilinx Mapping Report File for Design 'textovhdl'
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Design Information
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------------------
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Command Line : map -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol
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high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
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-pr off -lc off -power off -o textovhdl_map.ncd textovhdl.ngd textovhdl.pcf
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Target Device : xc6slx16
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Target Package : csg324
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Target Speed : -2
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Mapper Version : spartan6 -- $Revision: 1.55 $
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Mapped Date : Wed Jun 01 11:28:39 2022
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Design Summary
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--------------
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Number of errors: 0
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Number of warnings: 4
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Slice Logic Utilization:
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Number of Slice Registers: 32 out of 18,224 1%
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Number used as Flip Flops: 32
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Number used as Latches: 0
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Number used as Latch-thrus: 0
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Number used as AND/OR logics: 0
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Number of Slice LUTs: 31 out of 9,112 1%
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Number used as logic: 29 out of 9,112 1%
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Number using O6 output only: 14
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Number using O5 output only: 11
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Number using O5 and O6: 4
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Number used as ROM: 0
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Number used as Memory: 0 out of 2,176 0%
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Number used exclusively as route-thrus: 2
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Number with same-slice register load: 0
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Number with same-slice carry load: 2
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Number with other load: 0
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Slice Logic Distribution:
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Number of occupied Slices: 11 out of 2,278 1%
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Number of MUXCYs used: 20 out of 4,556 1%
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Number of LUT Flip Flop pairs used: 31
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Number with an unused Flip Flop: 1 out of 31 3%
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Number with an unused LUT: 0 out of 31 0%
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Number of fully used LUT-FF pairs: 30 out of 31 96%
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Number of unique control sets: 2
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Number of slice register sites lost
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to control set restrictions: 8 out of 18,224 1%
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A LUT Flip Flop pair for this architecture represents one LUT paired with
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one Flip Flop within a slice. A control set is a unique combination of
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clock, reset, set, and enable signals for a registered element.
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The Slice Logic Distribution report is not meaningful if the design is
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over-mapped for a non-slice resource or if Placement fails.
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IO Utilization:
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Number of bonded IOBs: 17 out of 232 7%
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Number of LOCed IOBs: 17 out of 17 100%
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Specific Feature Utilization:
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Number of RAMB16BWERs: 0 out of 32 0%
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Number of RAMB8BWERs: 0 out of 64 0%
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Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
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Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
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Number of BUFG/BUFGMUXs: 2 out of 16 12%
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Number used as BUFGs: 2
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Number used as BUFGMUX: 0
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Number of DCM/DCM_CLKGENs: 0 out of 4 0%
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Number of ILOGIC2/ISERDES2s: 0 out of 248 0%
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Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 248 0%
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Number of OLOGIC2/OSERDES2s: 0 out of 248 0%
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Number of BSCANs: 0 out of 4 0%
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Number of BUFHs: 0 out of 128 0%
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Number of BUFPLLs: 0 out of 8 0%
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Number of BUFPLL_MCBs: 0 out of 4 0%
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Number of DSP48A1s: 0 out of 32 0%
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Number of ICAPs: 0 out of 1 0%
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Number of MCBs: 0 out of 2 0%
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Number of PCILOGICSEs: 0 out of 2 0%
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Number of PLL_ADVs: 0 out of 2 0%
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Number of PMVs: 0 out of 1 0%
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Number of STARTUPs: 0 out of 1 0%
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Number of SUSPEND_SYNCs: 0 out of 1 0%
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Average Fanout of Non-Clock Nets: 1.88
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Peak Memory Usage: 345 MB
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Total REAL time to MAP completion: 7 secs
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Total CPU time to MAP completion: 6 secs
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Table of Contents
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-----------------
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Section 1 - Errors
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Section 2 - Warnings
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Section 3 - Informational
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Section 4 - Removed Logic Summary
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Section 5 - Removed Logic
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Section 6 - IOB Properties
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Section 7 - RPMs
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Section 8 - Guide Report
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Section 9 - Area Group and Partition Summary
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Section 10 - Timing Report
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Section 11 - Configuration String Information
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Section 12 - Control Set Information
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Section 13 - Utilization by Hierarchy
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Section 1 - Errors
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------------------
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Section 2 - Warnings
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--------------------
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WARNING:MapLib:701 - Signal LEDS<3> connected to top level port LEDS<3> has been
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removed.
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WARNING:MapLib:701 - Signal LEDS<2> connected to top level port LEDS<2> has been
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removed.
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WARNING:MapLib:701 - Signal LEDS<1> connected to top level port LEDS<1> has been
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removed.
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WARNING:MapLib:701 - Signal LEDS<0> connected to top level port LEDS<0> has been
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removed.
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Section 3 - Informational
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-------------------------
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INFO:LIT:243 - Logical network BUT<3>_IBUF has no load.
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INFO:LIT:395 - The above info message is repeated 12 more times for the
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following (max. 5 shown):
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BUT<2>_IBUF,
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BUT<1>_IBUF,
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BUT<0>_IBUF,
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DIPSW<3>_IBUF,
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DIPSW<2>_IBUF
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To see the details of these info messages, please use the -detail switch.
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INFO:MapLib:562 - No environment variables are currently set.
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INFO:LIT:244 - All of the single ended outputs in this design are using slew
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rate limited output drivers. The delay on speed critical single ended outputs
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can be dramatically reduced by designating them as fast outputs.
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INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
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0.000 to 85.000 Celsius)
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INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
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1.260 Volts)
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INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
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(.mrp).
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INFO:Pack:1650 - Map created a placed design.
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Section 4 - Removed Logic Summary
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---------------------------------
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8 block(s) removed
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2 block(s) optimized away
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4 signal(s) removed
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Section 5 - Removed Logic
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-------------------------
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The trimmed logic reported below is either:
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1. part of a cycle
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2. part of disabled logic
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3. a side-effect of other trimmed logic
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The signal "LEDS<3>" is unused and has been removed.
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Unused block "LEDS_3_OBUFT" (TRI) removed.
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The signal "LEDS<2>" is unused and has been removed.
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Unused block "LEDS_2_OBUFT" (TRI) removed.
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The signal "LEDS<1>" is unused and has been removed.
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Unused block "LEDS_1_OBUFT" (TRI) removed.
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The signal "LEDS<0>" is unused and has been removed.
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Unused block "LEDS_0_OBUFT" (TRI) removed.
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Unused block "LEDS<0>" (PAD) removed.
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Unused block "LEDS<1>" (PAD) removed.
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Unused block "LEDS<2>" (PAD) removed.
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Unused block "LEDS<3>" (PAD) removed.
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Optimized Block(s):
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TYPE BLOCK
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GND XST_GND
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VCC XST_VCC
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To enable printing of redundant blocks removed and signals merged, set the
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detailed map report option and rerun map.
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Section 6 - IOB Properties
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--------------------------
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+---------------------------------------------------------------------------------------------------------------------------------------------------------+
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| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
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| | | | | Term | Strength | Rate | | | Delay |
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+---------------------------------------------------------------------------------------------------------------------------------------------------------+
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| BUT<0> | IOB | INPUT | LVCMOS25 | | | | | | |
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| BUT<1> | IOB | INPUT | LVCMOS25 | | | | | | |
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| BUT<2> | IOB | INPUT | LVCMOS25 | | | | | | |
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| BUT<3> | IOB | INPUT | LVCMOS25 | | | | | | |
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| CLK27MHz | IOB | INPUT | LVCMOS25 | | | | | | |
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| DIPSW<0> | IOB | INPUT | LVCMOS25 | | | | | | |
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| DIPSW<1> | IOB | INPUT | LVCMOS25 | | | | | | |
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| DIPSW<2> | IOB | INPUT | LVCMOS25 | | | | | | |
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| DIPSW<3> | IOB | INPUT | LVCMOS25 | | | | | | |
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| GPIO<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
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| GPIO<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
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| GPIO<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
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| GPIO<3> | IOB | INPUT | LVCMOS25 | | | | | | |
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| GPIO<4> | IOB | INPUT | LVCMOS25 | | | | | | |
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| GPIO<5> | IOB | INPUT | LVCMOS25 | | | | | | |
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| GPIO<6> | IOB | INPUT | LVCMOS25 | | | | | | |
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| GPIO<7> | IOB | INPUT | LVCMOS25 | | | | | | |
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+---------------------------------------------------------------------------------------------------------------------------------------------------------+
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Section 7 - RPMs
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----------------
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Section 8 - Guide Report
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------------------------
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Guide not run on this design.
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Section 9 - Area Group and Partition Summary
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--------------------------------------------
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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Area Group Information
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----------------------
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No area groups were found in this design.
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----------------------
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Section 10 - Timing Report
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--------------------------
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A logic-level (pre-route) timing report can be generated by using Xilinx static
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timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
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mapped NCD and PCF files. Please note that this timing report will be generated
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using estimated delay information. For accurate numbers, please generate a
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timing report with the post Place and Route NCD file.
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For more information about the Timing Analyzer, consult the Xilinx Timing
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Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
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Command Line Tools User Guide "TRACE" chapter.
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Section 11 - Configuration String Details
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-----------------------------------------
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Use the "-detail" map option to print out Configuration Strings
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Section 12 - Control Set Information
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------------------------------------
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Use the "-detail" map option to print out Control Set Information.
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Section 13 - Utilization by Hierarchy
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-------------------------------------
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Use the "-detail" map option to print out the Utilization by Hierarchy section.
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