517 lines
24 KiB
Plaintext
517 lines
24 KiB
Plaintext
Release 14.7 - xst P.20131013 (nt64)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.12 secs
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--> Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.12 secs
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--> Reading design: textovhdl.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Parsing
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3) HDL Elaboration
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4) HDL Synthesis
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4.1) HDL Synthesis Report
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5) Advanced HDL Synthesis
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5.1) Advanced HDL Synthesis Report
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6) Low Level Synthesis
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7) Partition Report
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8) Design Summary
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8.1) Primitive and Black Box Usage
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8.2) Device utilization summary
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8.3) Partition Resource Summary
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8.4) Timing Report
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8.4.1) Clock Information
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8.4.2) Asynchronous Control Signals Information
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8.4.3) Timing Summary
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8.4.4) Timing Details
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8.4.5) Cross Clock Domains Report
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "textovhdl.prj"
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "textovhdl"
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Output Format : NGC
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Target Device : xc6slx16-2-csg324
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---- Source Options
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Top Module Name : textovhdl
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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Safe Implementation : No
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FSM Style : LUT
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RAM Extraction : Yes
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RAM Style : Auto
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ROM Extraction : Yes
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Shift Register Extraction : YES
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ROM Style : Auto
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Resource Sharing : YES
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Asynchronous To Synchronous : NO
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Shift Register Minimum Size : 2
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Use DSP Block : Auto
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Automatic Register Balancing : No
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---- Target Options
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LUT Combining : Auto
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Reduce Control Sets : Auto
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Add IO Buffers : YES
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Global Maximum Fanout : 100000
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Add Generic Clock Buffer(BUFG) : 16
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Register Duplication : YES
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Optimize Instantiated Primitives : NO
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Use Clock Enable : Auto
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Use Synchronous Set : Auto
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Use Synchronous Reset : Auto
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Pack IO Registers into IOBs : Auto
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Power Reduction : NO
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Keep Hierarchy : No
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Netlist Hierarchy : As_Optimized
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RTL Output : Yes
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Global Optimization : AllClockNets
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Read Cores : YES
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Write Timing Constraints : NO
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Cross Clock Analysis : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : Maintain
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Slice Utilization Ratio : 100
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BRAM Utilization Ratio : 100
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DSP48 Utilization Ratio : 100
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Auto BRAM Packing : NO
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Slice Utilization Ratio Delta : 5
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=========================================================================
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=========================================================================
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* HDL Parsing *
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=========================================================================
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Parsing VHDL file "C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd" into library work
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Parsing entity <textovhdl>.
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Parsing architecture <comportamento> of entity <textovhdl>.
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Parsing entity <CONTBCD_C>.
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Parsing architecture <comportamento> of entity <contbcd_c>.
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Parsing entity <display>.
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Parsing architecture <comportamento> of entity <display>.
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=========================================================================
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* HDL Elaboration *
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=========================================================================
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Elaborating entity <textovhdl> (architecture <comportamento>) from library <work>.
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Elaborating entity <display> (architecture <comportamento>) from library <work>.
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WARNING:HDLCompiler:1127 - "C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd" Line 54: Assignment to clk100k ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd" Line 55: Assignment to clk25k ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd" Line 56: Assignment to clk621ms ignored, since the identifier is never used
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WARNING:HDLCompiler:634 - "C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd" Line 20: Net <num7[3]> does not have a driver.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Synthesizing Unit <textovhdl>.
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Related source file is "C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd".
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WARNING:Xst:647 - Input <BUT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <DIPSW> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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Always blocking tristate driving signal <GPIO<7>> is removed.
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Always blocking tristate driving signal <GPIO<6>> is removed.
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Always blocking tristate driving signal <GPIO<5>> is removed.
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Always blocking tristate driving signal <GPIO<4>> is removed.
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Always blocking tristate driving signal <GPIO<3>> is removed.
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Always blocking tristate driving signal <GPIO<2>> is removed.
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Always blocking tristate driving signal <GPIO<1>> is removed.
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Always blocking tristate driving signal <GPIO<0>> is removed.
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WARNING:Xst:653 - Signal <num7> is used but never assigned. This sourceless signal will be automatically connected to value GND.
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WARNING:Xst:653 - Signal <num6> is used but never assigned. This sourceless signal will be automatically connected to value GND.
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WARNING:Xst:653 - Signal <num5> is used but never assigned. This sourceless signal will be automatically connected to value GND.
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WARNING:Xst:653 - Signal <num4> is used but never assigned. This sourceless signal will be automatically connected to value GND.
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WARNING:Xst:653 - Signal <num3> is used but never assigned. This sourceless signal will be automatically connected to value GND.
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WARNING:Xst:653 - Signal <num2> is used but never assigned. This sourceless signal will be automatically connected to value GND.
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WARNING:Xst:653 - Signal <num1> is used but never assigned. This sourceless signal will be automatically connected to value GND.
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WARNING:Xst:653 - Signal <num0> is used but never assigned. This sourceless signal will be automatically connected to value GND.
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Found 24-bit register for signal <contaux>.
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Found 24-bit adder for signal <contaux[23]_GND_5_o_add_5_OUT> created at line 50.
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Found 1-bit tristate buffer for signal <LEDS<3>> created at line 39
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Found 1-bit tristate buffer for signal <LEDS<2>> created at line 39
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Found 1-bit tristate buffer for signal <LEDS<1>> created at line 39
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Found 1-bit tristate buffer for signal <LEDS<0>> created at line 39
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Summary:
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inferred 1 Adder/Subtractor(s).
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inferred 24 D-type flip-flop(s).
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inferred 4 Tristate(s).
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Unit <textovhdl> synthesized.
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Synthesizing Unit <display>.
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Related source file is "C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd".
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Found 1-bit register for signal <configur>.
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Found 16-bit register for signal <palavra>.
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Found 9-bit register for signal <EN>.
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Found 9-bit adder for signal <EN[8]_GND_18_o_add_37_OUT> created at line 169.
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Found 8x4-bit Read Only RAM for signal <proxdisplay>
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Summary:
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inferred 1 RAM(s).
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inferred 1 Adder/Subtractor(s).
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inferred 26 D-type flip-flop(s).
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inferred 4 Multiplexer(s).
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Unit <display> synthesized.
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=========================================================================
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HDL Synthesis Report
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Macro Statistics
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# RAMs : 1
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8x4-bit single-port Read Only RAM : 1
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# Adders/Subtractors : 2
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24-bit adder : 1
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9-bit adder : 1
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# Registers : 4
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1-bit register : 1
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16-bit register : 1
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24-bit register : 1
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9-bit register : 1
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# Multiplexers : 4
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16-bit 2-to-1 multiplexer : 4
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# Tristates : 4
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1-bit tristate buffer : 4
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=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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=========================================================================
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Synthesizing (advanced) Unit <display>.
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The following registers are absorbed into counter <EN>: 1 register on signal <EN>.
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INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_proxdisplay> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
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-----------------------------------------------------------------------
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| ram_type | Distributed | |
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-----------------------------------------------------------------------
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| Port A |
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| aspect ratio | 8-word x 4-bit | |
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| weA | connected to signal <GND> | high |
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| addrA | connected to signal <EN<7:5>> | |
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| diA | connected to signal <GND> | |
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| doA | connected to signal <proxdisplay> | |
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-----------------------------------------------------------------------
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Unit <display> synthesized (advanced).
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Synthesizing (advanced) Unit <textovhdl>.
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The following registers are absorbed into counter <contaux>: 1 register on signal <contaux>.
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Unit <textovhdl> synthesized (advanced).
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=========================================================================
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Advanced HDL Synthesis Report
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Macro Statistics
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# RAMs : 1
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8x4-bit single-port distributed Read Only RAM : 1
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# Counters : 2
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24-bit up counter : 1
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9-bit up counter : 1
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# Registers : 17
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Flip-Flops : 17
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# Multiplexers : 4
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16-bit 2-to-1 multiplexer : 4
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=========================================================================
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=========================================================================
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* Low Level Synthesis *
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=========================================================================
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WARNING:Xst:2677 - Node <contaux_6> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_7> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_8> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_9> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_10> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_11> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_12> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_13> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_14> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_15> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_16> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_17> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_18> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_19> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_20> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_21> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_22> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_23> of sequential type is unconnected in block <textovhdl>.
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Optimizing unit <textovhdl> ...
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Optimizing unit <display> ...
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Mapping all equations...
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Building and optimizing final netlist ...
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Found area constraint ratio of 100 (+ 5) on block textovhdl, actual ratio is 0.
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Final Macro Processing ...
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=========================================================================
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Final Register Report
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Macro Statistics
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# Registers : 32
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Flip-Flops : 32
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=========================================================================
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=========================================================================
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* Partition Report *
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=========================================================================
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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=========================================================================
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* Design Summary *
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=========================================================================
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Top Level Output File Name : textovhdl.ngc
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Primitive and Black Box Usage:
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------------------------------
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# BELS : 64
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# GND : 1
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# INV : 4
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# LUT1 : 13
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# LUT2 : 5
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# LUT3 : 1
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# LUT4 : 1
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# LUT5 : 5
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# LUT6 : 5
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# MUXCY : 13
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# VCC : 1
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# XORCY : 15
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# FlipFlops/Latches : 32
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# FD : 15
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# FD_1 : 17
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# Clock Buffers : 2
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# BUFG : 1
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# BUFGP : 1
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# IO Buffers : 7
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# OBUF : 3
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# OBUFT : 4
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Device utilization summary:
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---------------------------
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Selected Device : 6slx16csg324-2
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Slice Logic Utilization:
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Number of Slice Registers: 32 out of 18224 0%
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Number of Slice LUTs: 34 out of 9112 0%
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Number used as Logic: 34 out of 9112 0%
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Slice Logic Distribution:
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Number of LUT Flip Flop pairs used: 34
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Number with an unused Flip Flop: 2 out of 34 5%
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Number with an unused LUT: 0 out of 34 0%
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Number of fully used LUT-FF pairs: 32 out of 34 94%
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Number of unique control sets: 3
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IO Utilization:
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Number of IOs: 21
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Number of bonded IOBs: 8 out of 232 3%
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Specific Feature Utilization:
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Number of BUFG/BUFGCTRLs: 2 out of 16 12%
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---------------------------
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Partition Resource Summary:
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---------------------------
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No Partitions were found in this design.
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---------------------------
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=========================================================================
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Timing Report
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NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
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FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
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GENERATED AFTER PLACE-and-ROUTE.
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Clock Information:
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------------------
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-----------------------------------+------------------------+-------+
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Clock Signal | Clock buffer(FF name) | Load |
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-----------------------------------+------------------------+-------+
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CLK27MHz | BUFGP | 6 |
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contaux_5 | BUFG | 26 |
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-----------------------------------+------------------------+-------+
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Asynchronous Control Signals Information:
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----------------------------------------
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No asynchronous control signals found in this design
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Timing Summary:
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---------------
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Speed Grade: -2
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Minimum period: 2.579ns (Maximum Frequency: 387.785MHz)
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Minimum input arrival time before clock: No path found
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Maximum output required time after clock: 5.607ns
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Maximum combinational path delay: No path found
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Timing Details:
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---------------
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All values displayed in nanoseconds (ns)
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=========================================================================
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Timing constraint: Default period analysis for Clock 'CLK27MHz'
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Clock period: 2.049ns (frequency: 488.043MHz)
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Total number of paths / destination ports: 21 / 6
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-------------------------------------------------------------------------
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Delay: 2.049ns (Levels of Logic = 7)
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Source: contaux_0 (FF)
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Destination: contaux_5 (FF)
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Source Clock: CLK27MHz rising
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Destination Clock: CLK27MHz rising
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Data Path: contaux_0 to contaux_5
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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FD:C->Q 1 0.525 0.681 contaux_0 (contaux_0)
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INV:I->O 1 0.255 0.000 Mcount_contaux_lut<0>_INV_0 (Mcount_contaux_lut<0>)
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MUXCY:S->O 1 0.215 0.000 Mcount_contaux_cy<0> (Mcount_contaux_cy<0>)
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MUXCY:CI->O 1 0.023 0.000 Mcount_contaux_cy<1> (Mcount_contaux_cy<1>)
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MUXCY:CI->O 1 0.023 0.000 Mcount_contaux_cy<2> (Mcount_contaux_cy<2>)
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MUXCY:CI->O 1 0.023 0.000 Mcount_contaux_cy<3> (Mcount_contaux_cy<3>)
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MUXCY:CI->O 0 0.023 0.000 Mcount_contaux_cy<4> (Mcount_contaux_cy<4>)
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XORCY:CI->O 1 0.206 0.000 Mcount_contaux_xor<5> (Result<5>)
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FD:D 0.074 contaux_5
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----------------------------------------
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Total 2.049ns (1.368ns logic, 0.681ns route)
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(66.8% logic, 33.2% route)
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=========================================================================
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Timing constraint: Default period analysis for Clock 'contaux_5'
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Clock period: 2.579ns (frequency: 387.785MHz)
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Total number of paths / destination ports: 117 / 26
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-------------------------------------------------------------------------
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Delay: 2.579ns (Levels of Logic = 6)
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Source: UDISP/EN_4 (FF)
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Destination: UDISP/EN_8 (FF)
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Source Clock: contaux_5 falling
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Destination Clock: contaux_5 falling
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Data Path: UDISP/EN_4 to UDISP/EN_8
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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FD:C->Q 18 0.525 1.235 UDISP/EN_4 (UDISP/EN_4)
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LUT1:I0->O 1 0.254 0.000 UDISP/Mcount_EN_cy<4>_rt (UDISP/Mcount_EN_cy<4>_rt)
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MUXCY:S->O 1 0.215 0.000 UDISP/Mcount_EN_cy<4> (UDISP/Mcount_EN_cy<4>)
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MUXCY:CI->O 1 0.023 0.000 UDISP/Mcount_EN_cy<5> (UDISP/Mcount_EN_cy<5>)
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MUXCY:CI->O 1 0.023 0.000 UDISP/Mcount_EN_cy<6> (UDISP/Mcount_EN_cy<6>)
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MUXCY:CI->O 0 0.023 0.000 UDISP/Mcount_EN_cy<7> (UDISP/Mcount_EN_cy<7>)
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XORCY:CI->O 1 0.206 0.000 UDISP/Mcount_EN_xor<8> (UDISP/Result<8>)
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FD:D 0.074 UDISP/EN_8
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----------------------------------------
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Total 2.579ns (1.344ns logic, 1.235ns route)
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(52.1% logic, 47.9% route)
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=========================================================================
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Timing constraint: Default OFFSET OUT AFTER for Clock 'contaux_5'
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Total number of paths / destination ports: 2 / 2
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-------------------------------------------------------------------------
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Offset: 5.607ns (Levels of Logic = 2)
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Source: UDISP/EN_4 (FF)
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Destination: GPIO<1> (PAD)
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Source Clock: contaux_5 falling
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Data Path: UDISP/EN_4 to GPIO<1>
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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FD:C->Q 18 0.525 1.234 UDISP/EN_4 (UDISP/EN_4)
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INV:I->O 1 0.255 0.681 UDISP/CS1_INV_0 (GPIO_1_OBUF)
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OBUF:I->O 2.912 GPIO_1_OBUF (GPIO<1>)
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----------------------------------------
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Total 5.607ns (3.692ns logic, 1.915ns route)
|
|
(65.8% logic, 34.2% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK27MHz'
|
|
Total number of paths / destination ports: 1 / 1
|
|
-------------------------------------------------------------------------
|
|
Offset: 4.162ns (Levels of Logic = 1)
|
|
Source: contaux_5 (FF)
|
|
Destination: GPIO<0> (PAD)
|
|
Source Clock: CLK27MHz rising
|
|
|
|
Data Path: contaux_5 to GPIO<0>
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FD:C->Q 2 0.525 0.725 contaux_5 (contaux_5)
|
|
OBUF:I->O 2.912 GPIO_0_OBUF (GPIO<0>)
|
|
----------------------------------------
|
|
Total 4.162ns (3.437ns logic, 0.725ns route)
|
|
(82.6% logic, 17.4% route)
|
|
|
|
=========================================================================
|
|
|
|
Cross Clock Domains Report:
|
|
--------------------------
|
|
|
|
Clock to Setup on destination clock CLK27MHz
|
|
---------------+---------+---------+---------+---------+
|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
|
---------------+---------+---------+---------+---------+
|
|
CLK27MHz | 2.049| | | |
|
|
---------------+---------+---------+---------+---------+
|
|
|
|
Clock to Setup on destination clock contaux_5
|
|
---------------+---------+---------+---------+---------+
|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
|
---------------+---------+---------+---------+---------+
|
|
contaux_5 | | | 2.579| |
|
|
---------------+---------+---------+---------+---------+
|
|
|
|
=========================================================================
|
|
|
|
|
|
Total REAL time to Xst completion: 6.00 secs
|
|
Total CPU time to Xst completion: 6.49 secs
|
|
|
|
-->
|
|
|
|
Total memory usage is 258888 kilobytes
|
|
|
|
Number of errors : 0 ( 0 filtered)
|
|
Number of warnings : 32 ( 0 filtered)
|
|
Number of infos : 1 ( 0 filtered)
|
|
|