25 lines
482 B
Plaintext
25 lines
482 B
Plaintext
Release 14.7 - par P.20131013 (nt64)
|
|
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
|
|
|
Wed Jun 01 13:06:17 2022
|
|
|
|
All signals are completely routed.
|
|
|
|
WARNING:ParHelpers:361 - There are 12 loadless signals in this design. This design will cause Bitgen to issue DRC
|
|
warnings.
|
|
|
|
BUT<0>_IBUF
|
|
BUT<1>_IBUF
|
|
BUT<2>_IBUF
|
|
BUT<3>_IBUF
|
|
DIPSW<0>_IBUF
|
|
DIPSW<1>_IBUF
|
|
DIPSW<2>_IBUF
|
|
DIPSW<3>_IBUF
|
|
GPIO<3>_IBUF
|
|
GPIO<5>_IBUF
|
|
GPIO<6>_IBUF
|
|
GPIO<7>_IBUF
|
|
|
|
|