724 lines
37 KiB
Plaintext
724 lines
37 KiB
Plaintext
Release 14.7 - xst P.20131013 (nt64)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 1.00 secs
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Total CPU time to Xst completion: 0.11 secs
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--> Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 1.00 secs
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Total CPU time to Xst completion: 0.11 secs
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--> Reading design: textovhdl.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Parsing
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3) HDL Elaboration
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4) HDL Synthesis
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4.1) HDL Synthesis Report
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5) Advanced HDL Synthesis
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5.1) Advanced HDL Synthesis Report
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6) Low Level Synthesis
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7) Partition Report
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8) Design Summary
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8.1) Primitive and Black Box Usage
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8.2) Device utilization summary
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8.3) Partition Resource Summary
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8.4) Timing Report
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8.4.1) Clock Information
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8.4.2) Asynchronous Control Signals Information
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8.4.3) Timing Summary
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8.4.4) Timing Details
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8.4.5) Cross Clock Domains Report
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "textovhdl.prj"
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "textovhdl"
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Output Format : NGC
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Target Device : xc6slx16-2-csg324
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---- Source Options
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Top Module Name : textovhdl
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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Safe Implementation : No
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FSM Style : LUT
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RAM Extraction : Yes
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RAM Style : Auto
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ROM Extraction : Yes
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Shift Register Extraction : YES
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ROM Style : Auto
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Resource Sharing : YES
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Asynchronous To Synchronous : NO
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Shift Register Minimum Size : 2
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Use DSP Block : Auto
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Automatic Register Balancing : No
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---- Target Options
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LUT Combining : Auto
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Reduce Control Sets : Auto
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Add IO Buffers : YES
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Global Maximum Fanout : 100000
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Add Generic Clock Buffer(BUFG) : 16
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Register Duplication : YES
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Optimize Instantiated Primitives : NO
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Use Clock Enable : Auto
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Use Synchronous Set : Auto
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Use Synchronous Reset : Auto
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Pack IO Registers into IOBs : Auto
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Power Reduction : NO
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Keep Hierarchy : No
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Netlist Hierarchy : As_Optimized
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RTL Output : Yes
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Global Optimization : AllClockNets
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Read Cores : YES
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Write Timing Constraints : NO
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Cross Clock Analysis : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : Maintain
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Slice Utilization Ratio : 100
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BRAM Utilization Ratio : 100
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DSP48 Utilization Ratio : 100
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Auto BRAM Packing : NO
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Slice Utilization Ratio Delta : 5
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=========================================================================
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=========================================================================
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* HDL Parsing *
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=========================================================================
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Parsing VHDL file "C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd" into library work
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Parsing entity <textovhdl>.
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Parsing architecture <comportamento> of entity <textovhdl>.
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WARNING:HDLCompiler:946 - "C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd" Line 80: Actual for formal port en is neither a static name nor a globally static expression
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Parsing entity <CONTBCD_C>.
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Parsing architecture <comportamento> of entity <contbcd_c>.
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Parsing entity <display>.
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Parsing architecture <comportamento> of entity <display>.
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=========================================================================
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* HDL Elaboration *
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=========================================================================
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Elaborating entity <textovhdl> (architecture <comportamento>) from library <work>.
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Elaborating entity <display> (architecture <comportamento>) from library <work>.
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Elaborating entity <CONTBCD_C> (architecture <comportamento>) from library <work>.
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WARNING:HDLCompiler:1127 - "C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd" Line 114: Assignment to clk25k ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd" Line 115: Assignment to clk621ms ignored, since the identifier is never used
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WARNING:HDLCompiler:634 - "C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd" Line 20: Net <num6[3]> does not have a driver.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Synthesizing Unit <textovhdl>.
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Related source file is "C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd".
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WARNING:Xst:647 - Input <BUT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <DIPSW> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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INFO:Xst:3210 - "C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd" line 82: Output port <ENOUT> of the instance <UC2> is unconnected or connected to loadless signal.
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Always blocking tristate driving signal <GPIO<7>> is removed.
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Always blocking tristate driving signal <GPIO<6>> is removed.
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Always blocking tristate driving signal <GPIO<5>> is removed.
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Always blocking tristate driving signal <GPIO<4>> is removed.
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Always blocking tristate driving signal <GPIO<3>> is removed.
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Always blocking tristate driving signal <GPIO<2>> is removed.
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Always blocking tristate driving signal <GPIO<1>> is removed.
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Always blocking tristate driving signal <GPIO<0>> is removed.
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WARNING:Xst:653 - Signal <num6> is used but never assigned. This sourceless signal will be automatically connected to value GND.
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WARNING:Xst:653 - Signal <num5> is used but never assigned. This sourceless signal will be automatically connected to value GND.
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WARNING:Xst:653 - Signal <num4> is used but never assigned. This sourceless signal will be automatically connected to value GND.
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WARNING:Xst:653 - Signal <num3> is used but never assigned. This sourceless signal will be automatically connected to value GND.
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Found 8-bit register for signal <codigo32<31:24>>.
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Found 2-bit register for signal <atual_S>.
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Found 4-bit register for signal <_n0101>.
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Found 24-bit register for signal <cont100k>.
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Found 24-bit register for signal <contaux>.
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Found 32-bit register for signal <atualshift>.
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Found 24-bit adder for signal <contaux[23]_GND_5_o_add_36_OUT> created at line 109.
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Found 24-bit subtractor for signal <GND_5_o_GND_5_o_sub_35_OUT<23:0>> created at line 107.
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Found 2-bit 4-to-1 multiplexer for signal <prox_S> created at line 23.
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HDL ADVISOR - Describing an operational reset or an explicit power-up state for register <atual_S> would allow inference of a finite state machine and as consequence better performance and smaller area.
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Summary:
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inferred 2 Adder/Subtractor(s).
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inferred 94 D-type flip-flop(s).
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inferred 7 Multiplexer(s).
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Unit <textovhdl> synthesized.
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Synthesizing Unit <display>.
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Related source file is "C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd".
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Found 1-bit register for signal <configur>.
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Found 16-bit register for signal <palavra>.
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Found 9-bit register for signal <EN>.
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Found 9-bit adder for signal <EN[8]_GND_18_o_add_37_OUT> created at line 230.
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Found 8x4-bit Read Only RAM for signal <proxdisplay>
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Found 4-bit 7-to-1 multiplexer for signal <proxnum> created at line 188.
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Summary:
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inferred 1 RAM(s).
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inferred 1 Adder/Subtractor(s).
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inferred 26 D-type flip-flop(s).
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inferred 6 Multiplexer(s).
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Unit <display> synthesized.
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Synthesizing Unit <CONTBCD_C>.
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Related source file is "C:\Users\Gabriel\Xilinx\Aula20220601\textovhdl.vhd".
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Found 4-bit register for signal <cont>.
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Found 4-bit adder for signal <cont[3]_UP_add_3_OUT> created at line 151.
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Summary:
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inferred 1 Adder/Subtractor(s).
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inferred 4 D-type flip-flop(s).
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inferred 3 Multiplexer(s).
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Unit <CONTBCD_C> synthesized.
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=========================================================================
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HDL Synthesis Report
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Macro Statistics
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# RAMs : 1
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8x4-bit single-port Read Only RAM : 1
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# Adders/Subtractors : 6
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24-bit adder : 1
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24-bit subtractor : 1
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4-bit adder : 3
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9-bit adder : 1
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# Registers : 12
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1-bit register : 1
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16-bit register : 1
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2-bit register : 1
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24-bit register : 2
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32-bit register : 1
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4-bit register : 4
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8-bit register : 1
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9-bit register : 1
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# Multiplexers : 22
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1-bit 2-to-1 multiplexer : 3
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16-bit 2-to-1 multiplexer : 5
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2-bit 4-to-1 multiplexer : 1
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24-bit 2-to-1 multiplexer : 1
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4-bit 2-to-1 multiplexer : 11
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4-bit 7-to-1 multiplexer : 1
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=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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=========================================================================
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WARNING:Xst:2677 - Node <atualshift_0> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_1> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_2> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_3> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_4> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_5> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_6> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_7> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_8> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_9> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_10> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_11> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_12> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_13> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_14> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_15> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_16> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_17> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_18> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_19> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_20> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_21> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_22> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_23> of sequential type is unconnected in block <textovhdl>.
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Synthesizing (advanced) Unit <display>.
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The following registers are absorbed into counter <EN>: 1 register on signal <EN>.
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INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_proxdisplay> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
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-----------------------------------------------------------------------
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| ram_type | Distributed | |
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-----------------------------------------------------------------------
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| Port A |
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| aspect ratio | 8-word x 4-bit | |
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| weA | connected to signal <GND> | high |
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| addrA | connected to signal <EN<7:5>> | |
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| diA | connected to signal <GND> | |
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| doA | connected to signal <proxdisplay> | |
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-----------------------------------------------------------------------
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Unit <display> synthesized (advanced).
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Synthesizing (advanced) Unit <textovhdl>.
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The following registers are absorbed into counter <cont100k>: 1 register on signal <cont100k>.
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The following registers are absorbed into counter <contaux>: 1 register on signal <contaux>.
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Unit <textovhdl> synthesized (advanced).
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WARNING:Xst:2677 - Node <atualshift_0> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_1> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_2> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_3> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_4> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_5> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_6> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_7> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_8> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_9> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_10> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_11> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_12> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_13> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_14> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_15> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_16> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_17> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_18> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_19> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_20> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_21> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_22> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <atualshift_23> of sequential type is unconnected in block <textovhdl>.
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=========================================================================
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Advanced HDL Synthesis Report
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Macro Statistics
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# RAMs : 1
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8x4-bit single-port distributed Read Only RAM : 1
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# Adders/Subtractors : 3
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4-bit adder : 3
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# Counters : 3
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24-bit down counter : 1
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24-bit up counter : 1
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9-bit up counter : 1
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# Registers : 51
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Flip-Flops : 51
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# Multiplexers : 21
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1-bit 2-to-1 multiplexer : 3
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16-bit 2-to-1 multiplexer : 5
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2-bit 4-to-1 multiplexer : 1
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4-bit 2-to-1 multiplexer : 11
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4-bit 7-to-1 multiplexer : 1
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=========================================================================
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=========================================================================
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* Low Level Synthesis *
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=========================================================================
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WARNING:Xst:2677 - Node <contaux_6> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_7> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_8> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_9> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_10> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_11> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_12> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_13> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_14> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_15> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_16> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_17> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_18> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_19> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_20> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_21> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_22> of sequential type is unconnected in block <textovhdl>.
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WARNING:Xst:2677 - Node <contaux_23> of sequential type is unconnected in block <textovhdl>.
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Optimizing unit <textovhdl> ...
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Optimizing unit <CONTBCD_C> ...
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Optimizing unit <display> ...
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Mapping all equations...
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Building and optimizing final netlist ...
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Found area constraint ratio of 100 (+ 5) on block textovhdl, actual ratio is 1.
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FlipFlop num7_3 has been replicated 1 time(s) to handle iob=true attribute.
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FlipFlop num7_2 has been replicated 1 time(s) to handle iob=true attribute.
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FlipFlop num7_1 has been replicated 1 time(s) to handle iob=true attribute.
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FlipFlop num7_0 has been replicated 1 time(s) to handle iob=true attribute.
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Final Macro Processing ...
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=========================================================================
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Final Register Report
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Macro Statistics
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# Registers : 94
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Flip-Flops : 94
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=========================================================================
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=========================================================================
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* Partition Report *
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=========================================================================
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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=========================================================================
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* Design Summary *
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=========================================================================
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Top Level Output File Name : textovhdl.ngc
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Primitive and Black Box Usage:
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------------------------------
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# BELS : 196
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# GND : 1
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# INV : 30
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# LUT1 : 14
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# LUT2 : 9
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# LUT3 : 8
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# LUT4 : 6
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# LUT5 : 35
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# LUT6 : 17
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# MUXCY : 36
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# VCC : 1
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# XORCY : 39
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# FlipFlops/Latches : 94
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# FD : 49
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# FD_1 : 17
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# FDCE : 12
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# FDE : 8
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# FDE_1 : 8
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# Clock Buffers : 3
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# BUFG : 2
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# BUFGP : 1
|
|
# IO Buffers : 8
|
|
# IBUF : 1
|
|
# OBUF : 7
|
|
|
|
Device utilization summary:
|
|
---------------------------
|
|
|
|
Selected Device : 6slx16csg324-2
|
|
|
|
|
|
Slice Logic Utilization:
|
|
Number of Slice Registers: 90 out of 18224 0%
|
|
Number of Slice LUTs: 119 out of 9112 1%
|
|
Number used as Logic: 119 out of 9112 1%
|
|
|
|
Slice Logic Distribution:
|
|
Number of LUT Flip Flop pairs used: 130
|
|
Number with an unused Flip Flop: 40 out of 130 30%
|
|
Number with an unused LUT: 11 out of 130 8%
|
|
Number of fully used LUT-FF pairs: 79 out of 130 60%
|
|
Number of unique control sets: 10
|
|
|
|
IO Utilization:
|
|
Number of IOs: 21
|
|
Number of bonded IOBs: 9 out of 232 3%
|
|
IOB Flip Flops/Latches: 4
|
|
|
|
Specific Feature Utilization:
|
|
Number of BUFG/BUFGCTRLs: 3 out of 16 18%
|
|
|
|
---------------------------
|
|
Partition Resource Summary:
|
|
---------------------------
|
|
|
|
No Partitions were found in this design.
|
|
|
|
---------------------------
|
|
|
|
|
|
=========================================================================
|
|
Timing Report
|
|
|
|
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
|
|
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
|
|
GENERATED AFTER PLACE-and-ROUTE.
|
|
|
|
Clock Information:
|
|
------------------
|
|
-----------------------------------+------------------------+-------+
|
|
Clock Signal | Clock buffer(FF name) | Load |
|
|
-----------------------------------+------------------------+-------+
|
|
cont100k_8 | NONE(atual_S_0) | 22 |
|
|
GPIO<4> | IBUF+BUFG | 8 |
|
|
UC2/cont_3 | NONE(codigo32_24) | 8 |
|
|
CLK27MHz | BUFGP | 30 |
|
|
contaux_5 | BUFG | 26 |
|
|
-----------------------------------+------------------------+-------+
|
|
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
|
|
|
|
Asynchronous Control Signals Information:
|
|
----------------------------------------
|
|
No asynchronous control signals found in this design
|
|
|
|
Timing Summary:
|
|
---------------
|
|
Speed Grade: -2
|
|
|
|
Minimum period: 4.375ns (Maximum Frequency: 228.571MHz)
|
|
Minimum input arrival time before clock: 5.275ns
|
|
Maximum output required time after clock: 5.607ns
|
|
Maximum combinational path delay: No path found
|
|
|
|
Timing Details:
|
|
---------------
|
|
All values displayed in nanoseconds (ns)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default period analysis for Clock 'cont100k_8'
|
|
Clock period: 4.375ns (frequency: 228.571MHz)
|
|
Total number of paths / destination ports: 156 / 38
|
|
-------------------------------------------------------------------------
|
|
Delay: 4.375ns (Levels of Logic = 3)
|
|
Source: UC0/cont_3 (FF)
|
|
Destination: UC2/cont_3 (FF)
|
|
Source Clock: cont100k_8 rising
|
|
Destination Clock: cont100k_8 rising
|
|
|
|
Data Path: UC0/cont_3 to UC2/cont_3
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FDCE:C->Q 4 0.525 1.234 UC0/cont_3 (UC0/cont_3)
|
|
LUT6:I1->O 9 0.254 0.976 UC0/Mmux_ENOUT11 (EO<0>)
|
|
LUT5:I4->O 4 0.254 0.804 UC1/Mmux_ENOUT11 (EO<1>)
|
|
LUT5:I4->O 1 0.254 0.000 UC2/Mmux_proxcont21 (UC2/proxcont<1>)
|
|
FDCE:D 0.074 UC2/cont_1
|
|
----------------------------------------
|
|
Total 4.375ns (1.361ns logic, 3.014ns route)
|
|
(31.1% logic, 68.9% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default period analysis for Clock 'GPIO<4>'
|
|
Clock period: 1.324ns (frequency: 755.287MHz)
|
|
Total number of paths / destination ports: 7 / 7
|
|
-------------------------------------------------------------------------
|
|
Delay: 1.324ns (Levels of Logic = 0)
|
|
Source: atualshift_25 (FF)
|
|
Destination: atualshift_24 (FF)
|
|
Source Clock: GPIO<4> falling
|
|
Destination Clock: GPIO<4> falling
|
|
|
|
Data Path: atualshift_25 to atualshift_24
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FDE_1:C->Q 2 0.525 0.725 atualshift_25 (atualshift_25)
|
|
FDE_1:D 0.074 atualshift_24
|
|
----------------------------------------
|
|
Total 1.324ns (0.599ns logic, 0.725ns route)
|
|
(45.2% logic, 54.8% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default period analysis for Clock 'CLK27MHz'
|
|
Clock period: 4.206ns (frequency: 237.756MHz)
|
|
Total number of paths / destination ports: 897 / 30
|
|
-------------------------------------------------------------------------
|
|
Delay: 4.206ns (Levels of Logic = 12)
|
|
Source: cont100k_8 (FF)
|
|
Destination: cont100k_17 (FF)
|
|
Source Clock: CLK27MHz rising
|
|
Destination Clock: CLK27MHz rising
|
|
|
|
Data Path: cont100k_8 to cont100k_17
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FD:C->Q 24 0.525 1.379 cont100k_8 (cont100k_8)
|
|
INV:I->O 1 0.255 0.000 Mcount_cont100k_lut<8>_INV_0 (Mcount_cont100k_lut<8>)
|
|
MUXCY:S->O 1 0.215 0.000 Mcount_cont100k_cy<8> (Mcount_cont100k_cy<8>)
|
|
MUXCY:CI->O 1 0.023 0.000 Mcount_cont100k_cy<9> (Mcount_cont100k_cy<9>)
|
|
MUXCY:CI->O 1 0.023 0.000 Mcount_cont100k_cy<10> (Mcount_cont100k_cy<10>)
|
|
MUXCY:CI->O 1 0.023 0.000 Mcount_cont100k_cy<11> (Mcount_cont100k_cy<11>)
|
|
MUXCY:CI->O 1 0.023 0.000 Mcount_cont100k_cy<12> (Mcount_cont100k_cy<12>)
|
|
MUXCY:CI->O 1 0.023 0.000 Mcount_cont100k_cy<13> (Mcount_cont100k_cy<13>)
|
|
MUXCY:CI->O 1 0.023 0.000 Mcount_cont100k_cy<14> (Mcount_cont100k_cy<14>)
|
|
MUXCY:CI->O 1 0.023 0.000 Mcount_cont100k_cy<15> (Mcount_cont100k_cy<15>)
|
|
MUXCY:CI->O 1 0.023 0.000 Mcount_cont100k_cy<16> (Mcount_cont100k_cy<16>)
|
|
XORCY:CI->O 1 0.206 1.112 Mcount_cont100k_xor<17> (Result<17>1)
|
|
LUT5:I0->O 1 0.254 0.000 Mcount_cont100k_eqn_171 (Mcount_cont100k_eqn_17)
|
|
FD:D 0.074 cont100k_17
|
|
----------------------------------------
|
|
Total 4.206ns (1.715ns logic, 2.491ns route)
|
|
(40.8% logic, 59.2% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default period analysis for Clock 'contaux_5'
|
|
Clock period: 3.399ns (frequency: 294.204MHz)
|
|
Total number of paths / destination ports: 127 / 26
|
|
-------------------------------------------------------------------------
|
|
Delay: 3.399ns (Levels of Logic = 2)
|
|
Source: UDISP/EN_5 (FF)
|
|
Destination: UDISP/palavra_0 (FF)
|
|
Source Clock: contaux_5 falling
|
|
Destination Clock: contaux_5 falling
|
|
|
|
Data Path: UDISP/EN_5 to UDISP/palavra_0
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FD:C->Q 15 0.525 1.610 UDISP/EN_5 (UDISP/EN_5)
|
|
LUT6:I0->O 1 0.254 0.682 UDISP/Mmux_palavra[14]_proxpalavra[15]_mux_38_OUT21 (UDISP/Mmux_palavra[14]_proxpalavra[15]_mux_38_OUT2)
|
|
LUT6:I5->O 1 0.254 0.000 UDISP/Mmux_palavra[14]_proxpalavra[15]_mux_38_OUT22 (UDISP/palavra[14]_proxpalavra[15]_mux_38_OUT<0>)
|
|
FD_1:D 0.074 UDISP/palavra_0
|
|
----------------------------------------
|
|
Total 3.399ns (1.107ns logic, 2.292ns route)
|
|
(32.6% logic, 67.4% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default OFFSET IN BEFORE for Clock 'cont100k_8'
|
|
Total number of paths / destination ports: 20 / 20
|
|
-------------------------------------------------------------------------
|
|
Offset: 5.275ns (Levels of Logic = 4)
|
|
Source: GPIO<4> (PAD)
|
|
Destination: UC2/cont_3 (FF)
|
|
Destination Clock: cont100k_8 rising
|
|
|
|
Data Path: GPIO<4> to UC2/cont_3
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
IBUF:I->O 6 1.328 1.331 GPIO_4_IBUF (GPIO_4_IBUF)
|
|
LUT6:I0->O 9 0.254 0.976 UC0/Mmux_ENOUT11 (EO<0>)
|
|
LUT5:I4->O 4 0.254 0.804 UC1/Mmux_ENOUT11 (EO<1>)
|
|
LUT5:I4->O 1 0.254 0.000 UC2/Mmux_proxcont21 (UC2/proxcont<1>)
|
|
FDCE:D 0.074 UC2/cont_1
|
|
----------------------------------------
|
|
Total 5.275ns (2.164ns logic, 3.111ns route)
|
|
(41.0% logic, 59.0% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'cont100k_8'
|
|
Total number of paths / destination ports: 4 / 4
|
|
-------------------------------------------------------------------------
|
|
Offset: 4.118ns (Levels of Logic = 1)
|
|
Source: num7_3_1 (FF)
|
|
Destination: LEDS<3> (PAD)
|
|
Source Clock: cont100k_8 rising
|
|
|
|
Data Path: num7_3_1 to LEDS<3>
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FDE:C->Q 1 0.525 0.681 num7_3_1 (num7_3_1)
|
|
OBUF:I->O 2.912 LEDS_3_OBUF (LEDS<3>)
|
|
----------------------------------------
|
|
Total 4.118ns (3.437ns logic, 0.681ns route)
|
|
(83.5% logic, 16.5% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'contaux_5'
|
|
Total number of paths / destination ports: 2 / 2
|
|
-------------------------------------------------------------------------
|
|
Offset: 5.607ns (Levels of Logic = 2)
|
|
Source: UDISP/EN_4 (FF)
|
|
Destination: GPIO<1> (PAD)
|
|
Source Clock: contaux_5 falling
|
|
|
|
Data Path: UDISP/EN_4 to GPIO<1>
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FD:C->Q 18 0.525 1.234 UDISP/EN_4 (UDISP/EN_4)
|
|
INV:I->O 1 0.255 0.681 UDISP/CS1_INV_0 (GPIO_1_OBUF)
|
|
OBUF:I->O 2.912 GPIO_1_OBUF (GPIO<1>)
|
|
----------------------------------------
|
|
Total 5.607ns (3.692ns logic, 1.915ns route)
|
|
(65.8% logic, 34.2% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK27MHz'
|
|
Total number of paths / destination ports: 1 / 1
|
|
-------------------------------------------------------------------------
|
|
Offset: 4.162ns (Levels of Logic = 1)
|
|
Source: contaux_5 (FF)
|
|
Destination: GPIO<0> (PAD)
|
|
Source Clock: CLK27MHz rising
|
|
|
|
Data Path: contaux_5 to GPIO<0>
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FD:C->Q 2 0.525 0.725 contaux_5 (contaux_5)
|
|
OBUF:I->O 2.912 GPIO_0_OBUF (GPIO<0>)
|
|
----------------------------------------
|
|
Total 4.162ns (3.437ns logic, 0.725ns route)
|
|
(82.6% logic, 17.4% route)
|
|
|
|
=========================================================================
|
|
|
|
Cross Clock Domains Report:
|
|
--------------------------
|
|
|
|
Clock to Setup on destination clock CLK27MHz
|
|
---------------+---------+---------+---------+---------+
|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
|
---------------+---------+---------+---------+---------+
|
|
CLK27MHz | 4.206| | | |
|
|
---------------+---------+---------+---------+---------+
|
|
|
|
Clock to Setup on destination clock GPIO<4>
|
|
---------------+---------+---------+---------+---------+
|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
|
---------------+---------+---------+---------+---------+
|
|
GPIO<4> | | | 1.324| |
|
|
cont100k_8 | | | 3.310| |
|
|
---------------+---------+---------+---------+---------+
|
|
|
|
Clock to Setup on destination clock UC2/cont_3
|
|
---------------+---------+---------+---------+---------+
|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
|
---------------+---------+---------+---------+---------+
|
|
GPIO<4> | | 1.324| | |
|
|
---------------+---------+---------+---------+---------+
|
|
|
|
Clock to Setup on destination clock cont100k_8
|
|
---------------+---------+---------+---------+---------+
|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
|
---------------+---------+---------+---------+---------+
|
|
UC2/cont_3 | 4.231| | | |
|
|
cont100k_8 | 4.375| | | |
|
|
---------------+---------+---------+---------+---------+
|
|
|
|
Clock to Setup on destination clock contaux_5
|
|
---------------+---------+---------+---------+---------+
|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
|
---------------+---------+---------+---------+---------+
|
|
cont100k_8 | | | 3.247| |
|
|
contaux_5 | | | 3.399| |
|
|
---------------+---------+---------+---------+---------+
|
|
|
|
=========================================================================
|
|
|
|
|
|
Total REAL time to Xst completion: 8.00 secs
|
|
Total CPU time to Xst completion: 7.18 secs
|
|
|
|
-->
|
|
|
|
Total memory usage is 259144 kilobytes
|
|
|
|
Number of errors : 0 ( 0 filtered)
|
|
Number of warnings : 76 ( 0 filtered)
|
|
Number of infos : 3 ( 0 filtered)
|
|
|