| Project Statistics |
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PROP_Enable_Message_Filtering=false |
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PROP_LastAppliedGoal=Balanced |
| PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
| PROP_PropSpecInProjFile=Store all values |
PROP_Simulator=ISim (VHDL/Verilog) |
| PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
| PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
| PROP_intProjectCreationTimestamp=2022-06-01T11:23:26 |
PROP_intWbtProjectID=C59F24DEFAA841F7B8F7FB3A62750569 |
| PROP_intWbtProjectIteration=9 |
PROP_intWorkingDirLocWRTProjDir=Same |
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PROP_AutoTop=true |
| PROP_DevFamily=Spartan6 |
PROP_DevDevice=xc6slx16 |
| PROP_DevFamilyPMName=spartan6 |
PROP_DevPackage=csg324 |
| PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-2 |
| PROP_PreferredLanguage=VHDL |
FILE_UCF=1 |
| FILE_VHDL=1 |