Release 14.7 Map P.20131013 (nt64) Xilinx Map Application Log File for Design 'textovhdl' Design Information ------------------ Command Line : map -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o textovhdl_map.ncd textovhdl.ngd textovhdl.pcf Target Device : xc6slx16 Target Package : csg324 Target Speed : -2 Mapper Version : spartan6 -- $Revision: 1.55 $ Mapped Date : Wed Jun 01 13:05:59 2022 Mapping design into LUTs... Running directed packing... Running delay-based LUT packing... Updating timing models... INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report (.mrp). Running timing-driven placement... Total REAL time at the beginning of Placer: 5 secs Total CPU time at the beginning of Placer: 5 secs Phase 1.1 Initial Placement Analysis Phase 1.1 Initial Placement Analysis (Checksum:aaba704c) REAL time: 5 secs Phase 2.7 Design Feasibility Check Phase 2.7 Design Feasibility Check (Checksum:aaba704c) REAL time: 5 secs Phase 3.31 Local Placement Optimization Phase 3.31 Local Placement Optimization (Checksum:aaba704c) REAL time: 5 secs Phase 4.2 Initial Placement for Architecture Specific Features . WARNING:Place:1109 - A clock IOB / BUFGMUX clock component pair have been found that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock IOB component > is placed at site . The corresponding BUFG component is placed at site . There is only a select set of IOBs that can use the fast path to the Clocker buffer, and they are not being used. You may want to analyze why this problem exists and correct it. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN .PAD> allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. Phase 4.2 Initial Placement for Architecture Specific Features (Checksum:94831735) REAL time: 6 secs Phase 5.36 Local Placement Optimization Phase 5.36 Local Placement Optimization (Checksum:94831735) REAL time: 6 secs Phase 6.30 Global Clock Region Assignment Phase 6.30 Global Clock Region Assignment (Checksum:94831735) REAL time: 6 secs Phase 7.3 Local Placement Optimization Phase 7.3 Local Placement Optimization (Checksum:94831735) REAL time: 6 secs Phase 8.5 Local Placement Optimization Phase 8.5 Local Placement Optimization (Checksum:94831735) REAL time: 6 secs Phase 9.8 Global Placement ... ... Phase 9.8 Global Placement (Checksum:bf3a6a80) REAL time: 7 secs Phase 10.5 Local Placement Optimization Phase 10.5 Local Placement Optimization (Checksum:bf3a6a80) REAL time: 7 secs Phase 11.18 Placement Optimization Phase 11.18 Placement Optimization (Checksum:1543e850) REAL time: 7 secs Phase 12.5 Local Placement Optimization Phase 12.5 Local Placement Optimization (Checksum:1543e850) REAL time: 7 secs Phase 13.34 Placement Validation Phase 13.34 Placement Validation (Checksum:1543e850) REAL time: 7 secs Total REAL time to Placer completion: 7 secs Total CPU time to Placer completion: 7 secs Running post-placement packing... Writing output files... Design Summary -------------- Design Summary: Number of errors: 0 Number of warnings: 1 Slice Logic Utilization: Number of Slice Registers: 90 out of 18,224 1% Number used as Flip Flops: 90 Number used as Latches: 0 Number used as Latch-thrus: 0 Number used as AND/OR logics: 0 Number of Slice LUTs: 113 out of 9,112 1% Number used as logic: 103 out of 9,112 1% Number using O6 output only: 56 Number using O5 output only: 12 Number using O5 and O6: 35 Number used as ROM: 0 Number used as Memory: 0 out of 2,176 0% Number used exclusively as route-thrus: 10 Number with same-slice register load: 8 Number with same-slice carry load: 2 Number with other load: 0 Slice Logic Distribution: Number of occupied Slices: 36 out of 2,278 1% Number of MUXCYs used: 44 out of 4,556 1% Number of LUT Flip Flop pairs used: 117 Number with an unused Flip Flop: 40 out of 117 34% Number with an unused LUT: 4 out of 117 3% Number of fully used LUT-FF pairs: 73 out of 117 62% Number of unique control sets: 9 Number of slice register sites lost to control set restrictions: 30 out of 18,224 1% A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice. A control set is a unique combination of clock, reset, set, and enable signals for a registered element. The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. IO Utilization: Number of bonded IOBs: 21 out of 232 9% Number of LOCed IOBs: 21 out of 21 100% IOB Flip Flops: 4 Specific Feature Utilization: Number of RAMB16BWERs: 0 out of 32 0% Number of RAMB8BWERs: 0 out of 64 0% Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0% Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0% Number of BUFG/BUFGMUXs: 3 out of 16 18% Number used as BUFGs: 3 Number used as BUFGMUX: 0 Number of DCM/DCM_CLKGENs: 0 out of 4 0% Number of ILOGIC2/ISERDES2s: 0 out of 248 0% Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 248 0% Number of OLOGIC2/OSERDES2s: 4 out of 248 1% Number used as OLOGIC2s: 4 Number used as OSERDES2s: 0 Number of BSCANs: 0 out of 4 0% Number of BUFHs: 0 out of 128 0% Number of BUFPLLs: 0 out of 8 0% Number of BUFPLL_MCBs: 0 out of 4 0% Number of DSP48A1s: 0 out of 32 0% Number of ICAPs: 0 out of 1 0% Number of MCBs: 0 out of 2 0% Number of PCILOGICSEs: 0 out of 2 0% Number of PLL_ADVs: 0 out of 2 0% Number of PMVs: 0 out of 1 0% Number of STARTUPs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0% Average Fanout of Non-Clock Nets: 2.67 Peak Memory Usage: 348 MB Total REAL time to MAP completion: 7 secs Total CPU time to MAP completion: 7 secs Mapping completed. See MAP report file "textovhdl_map.mrp" for details.